JP2941387B2 - Multiplexing unit matching control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a coincidence control method for a multiplexed storage device in which a system storage device is multiplexed in order to secure data to be stored, and further increases the reliability of a highly reliable system using multiplexed SSUs. In a complex system comprising: a plurality of clusters each having at least a central processing unit; and a system storage device shared by each of the clusters. The multiplexed system storage device only detects defects independently detected in each of the system storage devices during processing of the data writing process performed in response to the command to write the same data to the specified system storage device. Equivalent damage detection means for detecting that the equivalence of the clusters has been lost, and a detection result of the equivalence damage detection means At least one equivalence damage reporting means for sending to one cluster is provided.

[Industrial applications]

The present invention relates to a complex system in which system storage devices are provided for a plurality of clusters, and more particularly, to a coincidence control method for a multiplex storage device in which system storage devices are multiplexed in order to guarantee data to be stored.

[Conventional technology]

With the development of computer processing technology, the central processing unit (CPU), the channel processing unit (CHP) that controls the data transfer of the channel, the main storage unit (MSU), the main storage access of the processing unit and the interface with the channel processing unit are controlled. SCMP (System Coup) consisting of multiple clusters consisting of main memory controllers (MCUs), etc., and system storage units (SSUs) arbitrarily accessible from the multiple clusters
led Multi Processor) has been put to practical use. This SCMP
In, the description area is multiplexed to secure the data of the system. 8 and 9 are multiplexed.
FIG. 3 is a configuration diagram of an SCMP having an SSU.

8 and 9, four clusters (CLE0 to CLE)
3) shares two SSUs (SSU0, SSU1) to constitute a highly reliable dual storage system.

In the type A shown in FIG. 8, the clusters CLE0, CLE
For writing from 1, writing to SSU0 and writing the same data to SSU1 via the interface. In addition, the clusters CLE2 and CLE3 store the same data in SSU0 via the interface while storing the same data in SSU1.

In the type B shown in FIG.
CLE0 to CL3 have two ports connected to SSU0 and SSU1, and when storing data, output from each port to SS
The same contents are stored in U0 and SSU1.

In order to obtain high reliability, it is common practice to multiplex storage areas. However, multiplexing in a single storage device makes it possible to use a single storage device when a failure occurs due to other factors. Can not cope. For this reason, as described above, in the current SCMP, as shown in FIGS. 8 and 9, two SSUs (S
(SU0, SSU1) are duplicated as storage areas holding the same contents, and the system can be continuously operated even if one SSU is disconnected due to a failure or the like.

[Problems to be solved by the invention]

As described above, the reliability of the system is increased by the duplication of two SSUs. However, due to this duplication, the same data must be written to both SSUs (SSU0, SSU1), and high-speed processing cannot be expected.
For this reason, in the current SCMP, an instruction for writing to two SSUs at the same time with one instruction is supported by hardware to increase the speed.

Similarly, in the SCMP configuration diagrams shown in FIGS. 8 and 9, the high-speed operation is enhanced by hardware. That is, in the type A, when a write command is emitted from the cluster, data is received by both SSUs via the inter-SSU interface, and the same contents are written to both SSUs. In the type B, the cluster side issues the same data to both SSUs by issuing a double write command to both SSUs with the double write command. The SSU is read by designating one of the SSUs by using a control table (including a flag indicating that reading is possible for each SSU) in each cluster.

In the above-mentioned SCMP, there is a case where the storage contents between the two SSUs do not match even though they are duplicated. For example, when a failure of the cluster itself or a failure of the SSU occurs, data in which an error is detected in the SSU is not written to the SSU, and the error is reported to the cluster.

The cluster during double writing is SCMP by another cluster
If the SSU is disconnected, the SSU stops the process at that point and reports an address exception to the cluster.

In the above description, since one instruction writes to both SSUs, each SSU performs processing independently in accordance with its own priority until the end of the instruction. There is a problem that the equivalence of the stored contents is broken between the SSUs. The state in which the contents of the two SSUs are inconsistent due to causes such as,, etc. is called an equivalence damage state, and the cause is called an equivalence damage error, and this equivalence damage state hinders the continued operation of SCMP. There is a problem that. This is because in SCMP, when a cluster is separated due to a failure or the like, the processing of that cluster is taken over by another cluster.
This will be described in more detail below.

When a cluster is separated for some reason, the processing of the separated cluster is taken over by another cluster, and the taken-over cluster reads the taken-over data from one of the SSUs according to the read flag in the cluster.
For example, if it specifies SSU0, the content is read from SSU0, and processing is proceeding with that content. On the other hand, SSU0 may be disconnected from SCMP for some reason such as maintenance. This takeover cluster performs its processing in SSU0
If this SSU0 disconnection occurs while performing the above operation, the cluster rewrites the read flag assuming that the other SSU1 has the same information, and attempts to continue processing with the content read from the SSU1. However, if the inherited contents cause the equivalence damage due to the reason described above and the data is inconsistent between SSU0 and SSU1, the processing cannot be continued. In other words, in the multiplexing system for high reliability described above, in order to take over the processing between clusters, the equivalence that the storage contents are always the same between SSUs must be guaranteed. Was spoiled, and processing was interrupted.

Furthermore, for example, when a failure occurs, a mismatch in storage contents occurs between the SSUs, and therefore, a process for restoring some equivalence must be performed. However, SCMP
Is writing to SSU at the same time using double-write instruction.Even if the above occurs, it is not possible to judge whether it is a double-write instruction by error report, and the equivalent interface has collapsed with the current interface Had the problem of not being able to report.

It is an object of the present invention to provide a multiplexed storage unit matching control method that further improves the reliability of a highly reliable system using multiplexed SSUs.

[Means for solving the problem]

 FIG. 1 is a block diagram showing the principle of the present invention.

The present invention relates to a decoding system including at least a plurality of clusters each having a central processing unit, and a system storage device in which the clusters are shared and multiplexed.

The equivalence damage detecting means 3 detects that the equivalence of the multiplexed system storage device 2 has been lost.

The equivalence damage reporting unit 4 sends the detection result of the equivalence damage detection unit 3 to at least one of the plurality of clusters. For example, the equivalent damage reporting unit 4 sends the detection result to all of the clusters.

[Action]

When one of the multiplexed system storage devices 2 has a write failure due to, for example, a failure or the like, the equivalence damage detection means 3 detects that the equivalence of the system storage device 2 has been lost. The equivalent damage report means 4 sends the detection result to at least one of the plurality of clusters. It is also sent to all clusters. Since the cluster can recognize the equivalence damage by this report, for example, it is possible to disconnect one of the multiplexed system storage devices 2 or to perform a process for ensuring the equivalence.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a configuration diagram of an A-type SCMP according to an embodiment of the present invention,
FIG. 3 is a block diagram of the B type of SCMP according to the embodiment of the present invention. The system storage device SSU0 has a storage circuit for storing data from the cluster and a control circuit (both not shown) for controlling the storage circuit. Basically, data from the cluster is stored in this storage circuit by the control of the control circuit. When storing and reading, the data is read through a control circuit. In addition to these circuits, the system storage devices SSU0 and SSU1 have equivalent damage error propagation circuits C and C ′ and equivalent damage error detection circuits a0 to a3,
a'0 to a'3 and equivalent damage error reporting circuits b0 to b3, b '
0 to b'3. The equivalent damage error propagation circuits C and C 'are configured by circuits divided into circuits corresponding to respective clusters, as described later. These equivalent damage error detection circuits a0 to a3 and a'0 to a'3 are provided corresponding to the clusters CLE0 to CLE3, respectively. When the data is not written, an equivalence damage error is detected. Equivalence damage error detection circuits a0 to a3,
The results detected by a'0 to a'3 are applied to the equivalent damage error propagation circuits C and C '.

The equivalent damage error reporting circuits b0-b3, b'0-b'3 are connected to the equivalent damage error propagation circuits C, C ', and the equivalent damage error detection circuits a0-a3, a'0-a The detection result of '3 is applied to the corresponding equivalent damage error reporting circuit. still,
The equivalence damage error reporting circuits b0, b1, b'0, b'1 are clusters.
Equivalent damage error reporting circuit connected to CLE0 to CLE3
The output signal (error report) from the equivalent damage error propagation circuit C 'is added to b0 via the equivalent damage error report circuit b'2, and further the output signal from the equivalent damage error propagation circuit C is added to the cluster CLE0. I do. The equivalent damage error reporting circuit b1 outputs to the cluster CLE1 an output signal applied from the equivalent damage error propagation circuit C and the equivalent damage error propagation circuit C 'via the equivalent damage error reporting circuit b'3. Similarly, signals are output to the clusters 2 and 3 in a corresponding manner.

In the case of FIG. 3, the equivalent damage error detection circuits a0 to a3, a'0 to a'3 are provided similarly to the case of FIG. 2, and the equivalent damage error reporting circuits b10 to b13, b 'Ten~
b'13 is connected to the equivalent damage error propagation circuits C and C ', and adds error reports from the corresponding equivalent damage error propagation circuits C and C' to the cluster separately. The outputs of the equivalent damage error reporting circuits b10 and b'12 are added to the cluster CLE10. Also, the cluster 11 has an equivalence damage error reporting circuit b1
1, b'13, Equivalent damage error reporting circuit b for cluster CLE12
Equivalent damage error reporting circuit for 12, b'10, cluster CLE13
The outputs of b13 and b'11 are added. In the A type, the clusters CLE0 to CLE3 detect that an equivalent damage error has occurred by one error report, and therefore, the equivalent damage error reporting circuits b0, b1, b'0, b'1 have two One error is reported to the cluster in total. On the other hand, in the B type, clusters CLE10 to CLE13 have two ports,
Information from each of the equivalent damage error reporting circuits is input, and it is collectively recognized that an equivalent damage error has occurred in the cluster.

In the prior art, the equivalent damage error could not be obtained because there was no such report. However, the equivalent damage error detection circuits a0 to a3, a'0 to a'3 and the equivalent damage error report circuit b0 to b3, b'0 to b'3, b10 to b13, b'10 to
b'13 reports the equivalence damage error.

FIG. 4 shows an equivalent damage error detection circuit according to an embodiment of the present invention.
a0 to a3, a'0 to a'3 and the equivalent damage error propagation circuit C,
It is a circuit diagram of C '. The equivalence damage error detection circuit a0 has a plurality of error detection circuits 30, and any one of the error detection circuits
Even if 30 detects an error, it detects through the OR gate 31 that an error has occurred. The output of the OR gate 31 is added to the AND gate 32 together with a signal indicating whether or not the instruction is a dual write instruction. When the instruction is a double write instruction, an error is output. When the instruction is not a double write instruction, no error is output. In the embodiment of the present invention, since the equivalent damage error detection signal is output only at the time of multiplexing (duplexing) and the duplication is performed, the gate is turned off by the AND gate 32 when the instruction is not a double write command, and the detection signal is output. It does not output.

On the other hand, cluster CLE0 causes the ONLINE signal to
And the judgment input of the AND gate 34. Also, a signal indicating whether or not the instruction is a double write instruction is added to the AND gate 34.
When the signal and the output of the G latch 33 are added, the on-line signal switches from H to L, and the instruction is a double write command, the AND gate 34 outputs a pulse, and this pulse is stored in the G latch 35. That is, when an error occurs in the double write command, the G latch 35 outputs an equivalent damage error detection signal corresponding to the cluster CLE0.

Equivalent damage error detection circuits a1-a3, a'1-
a'3 is the same as the equivalent damage error detection circuit a0, and is provided corresponding to each of the clusters CLE1, CLE2, and CLE3. The error is reported to the corresponding cluster in the same manner as in the prior art.

The equivalence damage error detection signal is a signal for reporting that the equivalence has been lost due to signal damage. In the CLE1 portion of the equivalence damage error propagation circuit C, the equivalent damage error detection signal for the cluster CLE1 is used. The outputs of the three equivalent damage error detection circuits a0, a2, and a3 for the clusters CLE0, CLE2, and CLE3 except for the output of the circuit a1 are added to the CLE1 portion of the equivalent damage error propagation circuit C.

The aforementioned three signals, that is, three signals excluding the equivalent damage error detection signal of the corresponding equivalent damage error detection circuit are added to the OR gate 41 and OR-added. And
It joins AND gate 42 with the online (ON LINE) signal of cluster CLE1. The gate is turned on by the online signal of the cluster CLE1, and the above-described equivalent damage error detection signal is applied to the clock synchronization circuit H via the OR gate 41 and the AND gate. The output of the AND gate 42 is applied to the series circuit of the G latch 43, G latch 44, and G latch 45 of the clock synchronization circuit H, and the output of the G latch 43 to G latch 45 is applied to the G latch 47 via the OR gate 46. . G latch
47 captures and stores the output level of the AND gate 42 according to the output of the OR gate 46. The circuit according to the embodiment of the present invention has two types of clocks CLOCKG and CLOCKC.
Latch is clock CLOCKG, C latch is clock CLOC
Capture input data with KC. The above-mentioned G latch 33 is for generating a pulse having a width of one clock CLOCKG together with the gate 34, and includes the G latches 43, 44, 45 and the OR gate 46.
Is a delay circuit for counting a clock CLOCKG and enabling the G latch 47 to which the time equivalent damage error detection signal is added after a predetermined time.

The output of the G latch 47 is applied to an OR gate 48. Also, the OR gate 48 is provided with a cluster CLE1 equivalent damage error detection signal (added from the equivalent damage error detection circuit CLE1), and when one of these signals goes to the H level, the signal is generated after an error occurs. Is set to the H level.
The output of the OR gate 48 is applied to the AND gate 51 via the two-stage C latches 49 and 50.

The latch and the clock synchronizing circuit H for h1 and h2 are circuits for transferring signals from the circuit synchronized with the G clock CLOCKG to the circuit operating with the clock CLOCKC which is the operation clock of each cluster.

The output of the C latch 55 described later is applied to the inverting input terminal of the AND gate 51. When the output of the C latch 55 is at the L level, the AND gate 51 is turned on, and the C latch 52
Capture the output of latch 50. And for A type, SS
Report the equivalent damage report for U to another SSU, for example, in Figure 4.
Output to SSU1. The second output of the C latch 52 is applied to an AND gate 53. The output of the C latch 55 is also applied to the AND gate 53. The AND gate 53 outputs the input signal until this signal becomes H level, and the C latch 52 transmits the equivalent damage report by this loop. Store the data.

Further, the output of the C latch 52 is applied to an AND gate 54. The other inverting input of the AND gate 54 has a BUSY signal J indicating that the cluster is in operation for each cluster.
And the data stored in the local SSU error storage circuit M of the equivalence damage error reporting circuit B, and when the cluster CLE1 is not performing the operation and there is no local SSU error, its output becomes the same level as the output of the C latch 52. . The C latch 55 receives this signal and outputs it to the equivalent damage error reporting circuit B. That is, the C latch 55 stores the level by the next clock CLOCKC when the C latch 52 becomes H level, and as a result, the C latch outputs an equivalent damage report during one clock pulse.

The AND gates 54 and 56 are turned on by the L level output from the C latch 63 in the equivalent damage error reporting circuit described later. The C latch 63 outputs an equivalent damage error signal, and the equivalent damage described later. When the error report circuit B stores the signal, it is turned off. When the AND gates 54 and 56 are turned off, the output of the C latch 55 is set to L level to clear data.

The equivalent damage error reporting circuit B has the cluster 1
BUSY signal is applied.

By the above-described operation, the C latch 52 stores the equivalent damage report to the other SSUs, and the C latch 55 stores the equivalent damage error signal. By the above operation, the signal detected by the equivalent damage error detection circuit a is added to the equivalent damage error propagation circuit C, stored, and added to the equivalent damage error report circuit B.

FIG. 5 is a circuit diagram of the equivalent damage error reporting circuit and its peripheral circuits. Equivalence damage error reporting circuit B is local
It has an SSU error storage circuit M and a remote SSU error storage circuit N. These memory circuits M and N are AND gate 6
1 and 62 and a C latch 63, and AND gates 64 and 65 and a C latch 66. RESET-LSSU is connected to the inverting inputs of AND gates 61 and 62.
−ERROR signal is reset to the inverting input of AND gates 64 and 65.
-RSSU-ERROR signal is added, and when not reset, these signals are at L level and AND gate.
61, 62, 64 and 65 are turned on. An equivalent damage error signal is added to the input of the AND gate 61, and the RESET-LSSU-E
When the RROR signal is L, the AND gate 61 is on, so that signal is applied to the C latch 63 and its output is
Will be input again. Thereby, the equivalent damage error signal is stored. In addition, AND gate 64 has other SSU
And the RESET-RSSU-E
When the RROR signal is not H, the output is similarly applied to the C-latch 66, and the output of the C-latch 66 is applied to the input section again via the AND gate 65, and is stored in the C-latch 66 as a result. The AND gates 64 and 65 have a signal n indicating the type.
1 is added, and it becomes 1 for Type A and SSU
Remember the equivalent damage report from 1. In the case of type B, since this level n1 is 0, the AND gates 64 and 65 are turned off and they are not stored. As described above, the output of the C latch 63 is added to the inverting inputs of the AND gates 54 and 56, so that the H level of the equivalent damage error signal is
Goes to the H level and the AND gate 5
Turn off 4, 56 and reset the contents of latch 55.

The outputs of the C latches 63 and 66 are applied to an AND gate 68 via an OR gate 67. The output of the NOR gate 69 is added to the other input of the AND gate 68. The NOR gate 69 receives the BUSY signal of the cluster CLE1 and the outputs of the C latches 70 and 71. In the NOR gate 69, the C latches 70 and 71 store 0, that is, both VALID1 and VALID2 are at L level and BUSY
When the signal is not H, it outputs an H level. In other words, when the BUSY signal is not at H and the C latches 70 and 71 both store an error, the AND gate 68 is turned on, and the local and remote SSU error storage circuits M and N added via the AND gate 67. Outputs error from. The output of this error causes the C latches 70 and 71 to shift the error. The outputs of the C latches 70 and 71 are applied to selectors 72 and 73,
One of them is selected by U-ID, and RESET-LSSU-ER
Output as R signal and RESET-RSSU-ERR signal. The output of the other AND gate 68 is added to the OR gate 74. If at least one of the added signals has an error, C
Add to latch 75. C latch 75 stores this error,
Output to the cluster CLE1 as an equivalence damage error signal.

The above operation has been described for the cluster CLE1, but signals are output to other clusters by the same circuit.

 The above operation will be described in more detail.

For example, as shown in FIG. 4, when an instruction from the cluster CLE0 results in an error in one of the SSUs, for example, SSU0, the error is detected by each error detection circuit in the SSU, and is OR-added to another equivalent damage. Joins the error propagation circuit. The disconnection by another cluster is performed by detecting the falling of the ONLINE signal in the request control unit of each cluster in the SSU indicating whether each cluster is incorporated in the SCMP system.

If at least one of the above errors is detected during the CLEO double write command, the error detection signal of the equivalence damage error detection circuit a is turned on, and all the equivalence damage error propagation circuits other than the corresponding ones are turned on. Report an error to C. The signal obtained by OR-adding the detection signals of the other clusters is synchronized by the clock synchronization circuit H with the clock of the cluster to which an error is to be reported. The SSU has a latch circuit that operates with its own clock. The above-mentioned G latch is a G clock CLOCKG, and the C latch is a latch circuit operated by the clock CLOCKC. Latched with output h1 of OR gate 46
The detection signal is synchronized by prohibiting control of 47 clocks.

In the figure, a BUSY signal J exists for a cluster and indicates that an operation between the clusters is being executed. In the embodiment of the present invention, this signal is off (L level).
Report an equivalence damage error to the cluster only if
The synchronized detection signals are temporarily held by the outputs K and L of the latches 52 and 55. In the case of type A, the output K of the latch 52 is connected to another SSU (SSU1 in the figure). This is because, in the case of type A, unlike type B, each cluster is not directly connected to one SSU.

The C latch 66 of the remote SSU error storage circuit N in FIG. 5 is a circuit that holds the output K from another SSU.
In the type B, the error is not accepted by the control line n1.

Thus, the local SSU error storage circuit M and the remote SSU
The equivalent damage error stored in the SC error storage circuit N is timed by the logic P and reported to the cluster CLE1 as an equivalent damage interrupt at the equivalent damage error interface.

FIG. 6 is a timing chart of an equivalent damage error report. When this equivalence damage interrupt is received in each cluster, the cluster performs a restoration process for matching to eliminate a mismatch that causes inconsistency between SSUs. A cluster in the SCMP determines one representative by inter-cluster communication and performs one of the following processes.

(A) If the error is caused by an SSU failure and only one of the SSU errors in FIG. 5 is ON, the cluster performs processing to disconnect that SSU from SCMP. Further, the separated SSU is subjected to replacement of inspection parts and the like, and then is re-incorporated into the system.

(B) When a cluster failure or a cluster disconnection during a double write instruction by another cluster is the cause, it is when both SSU errors in FIG. 5 are on and the SSU itself is not a failure, so the cluster Perform processing to ensure restoration of equivalence. Then, the cluster serving as the representative first prohibits the reading of one of the SSU1, for example. Next, the contents of SSU0 are read out, and the contents are again written to both SSUs (SSU0, SSU1) by a double write instruction. After this is completed, the prohibition of reading SSU1 is released. This restores SSU equivalence.

FIG. 7 is a processing flowchart summarizing the processing at the time of the above-described equivalence damage error. When an equivalence damage error occurs and an equivalence damage interrupt is involved, it is determined whether the cause is a cluster or an SSU (S1). If the cause is an SSU, the representative cluster is first determined and a failure occurs. SS
Disconnect U from the SCMP system (S2). Then, maintenance work such as replacement of inspection parts of the SSU (S3) and re-installation of the SPM CPM system (S4) are performed. If the cause is a cluster in the determination (S1), or after the process S4, a representative cluster is determined and reading of one SSU is prohibited. For example, SSU1
Is prohibited (S5). Then, the representative cluster sequentially reads the contents of the SSU, and writes the same data to both SSUs by a double write instruction (S6). Then, the read prohibition of SSU1 is released and the equivalence is restored.

If the logic is configured as in the embodiment of the present invention as described above,
The equivalence of the contents in the duplicated storage device can be maintained, and a highly reliable system is constructed.

〔The invention's effect〕

As described above, according to the present invention, a cluster can accurately recognize an equivalence damage state, an equivalence damage interrupt is generated by the report, and a matching process for resynchronization is performed based on the interrupted cluster. By doing
The reliability of a highly reliable system can be improved by multiplexing SSUs.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a configuration diagram of an SCMP (A type) of an embodiment of the present invention, FIG. 3 is a configuration diagram of an SCMP (B type) of an embodiment of the present invention, 4 is a circuit diagram of an equivalent damage error detection circuit and an equivalent damage error propagation circuit according to the embodiment of the present invention, FIG. 5 is a circuit diagram of an equivalent damage error report circuit and its peripheral circuits, and FIG. FIG. 7 is a timing chart of a damage error report, FIG. 7 is a processing flowchart at the time of an equivalent damage error, FIG. 8 is a configuration diagram of SCMP (A type), and FIG. 9 is a configuration diagram of SCMP (B type). 1-1, 1-1-2 ... central processing unit, 1-1, 1-2 ... cluster, 2 ... system storage device, 3 ... equivalent damage detection means, 4 ... equivalent damage Reporting means.

Claims (6)

(57) [Claims] At least a central processing unit (1-1-1,1-1)
1-2) each having a plurality of clusters (1-1,1-
2) and a multiplexed system storage device (2) in which the clusters are common and multiplexed, respectively, in response to an instruction to write the same data to the multiplexed system storage device (2). Equivalence for detecting only a defect independently detected in each of the system storage devices (2) during the data writing process as a loss of equivalence of the multiplexed system storage device (2). And equivalence damage detection means (3), and equivalence damage report means (4) for sending a detection result of the equivalence damage detection means (3) to at least one of the plurality of clusters. Multiplexing device matching control method. 2. A matching control method for a multiplexing apparatus according to claim 1, wherein said equivalence damage reporting means (4) sends said detection result to all of said plurality of clusters. 3. At least one of the plurality of clusters (1-1, 1-2), when the detection result is added, determines whether one of the multiplexed system storage devices (2) is separated or equivalent. 3. The matching control method for a multiplexing device according to claim 2, wherein one of the processes for ensuring recovery is performed. 4. The system storage device in a complex system comprising a plurality of clusters each having at least a central processing unit and a system storage device shared by each of the clusters, wherein the multiplexed system Only defects detected during the data write processing performed by itself in response to an instruction to write the same data to the storage device are detected as the equivalence of the multiplexed system storage device has been lost. A system storage device comprising: equivalence damage detection means; and equivalence damage report means for sending a detection result of the equivalence damage detection means to at least one of the plurality of clusters. 5. The system storage device according to claim 4, wherein said equivalence damage reporting means sends the detection result to all of the plurality of clusters. 6. The system storage device according to claim 1, wherein at least one of the plurality of clusters to which the detection result is added performs one of a process of disconnecting from the complex system and a process of restoring the equivalence. The system storage device according to claim 5, wherein