JP2938453B2 - Memory system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a memory system which can use memory elements of different capacities in a mixed manner, and aims to realize the memory system with a simple control mechanism. An address control circuit for converting an address into an address for each of the plurality of memory elements; and a configuration control register for setting memory configuration information relating to the memory capacity and the like of each of the plurality of memory elements in advance. Based on the memory configuration information, the plurality of memory elements are divided into a first memory element group (6
a) and a second memory element group (7
a), the upper and lower physical addresses of the physical address space of the memory system are assigned to the first memory element group (6a) and the second memory element group (7a), respectively. Control is performed to allocate and separate access to the first and second groups of memory elements (6a, 7a) according to the value of the most significant bit of the physical address, 1 and 0, respectively. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system for a computer, and more particularly to a memory system that can use memory elements having different capacities in a mixed manner. [Prior Art] With recent advances in LSI manufacturing technology, the capacity of memory devices has been increased from 16KBIT to 64KBIT, 256KBIT, and 1MBIT, which is quadrupling every few years. For this reason, in the design and manufacture of memory systems, even if the memory element that was supposed to be used at the time of design was, for example, 64 KBIT, there was a case where 256 KBIT was already mainstream at the time of mass production. . However, since memory elements have different bit widths of addresses if their memory capacities are different, it is not usually possible to use a memory printed board as it is. Conventionally, in consideration of such a case, in order to be able to use memory elements of different capacities in a mixed manner, a memory printed board on which only memory elements of the same capacity are mounted in units of a certain memory (eg, segment) is used. use,
A separate floating memory address register is provided for each segment, and for each segment, an interface is provided between the physical address assigned to the segment and a unique control specification such as the address bit width of a memory printed board in the segment. A method is used. [Problems to be Solved by the Invention] In the conventional memory system, when memory elements having different capacities are used in a mixed manner, it is necessary to provide a floating address register for each segment and control them individually, which increases the amount of hardware. And the control becomes complicated. An object of the present invention is to realize a memory system in which memory elements having different memory capacities are mixed with a simple control mechanism. [Means for Solving the Problems] The present invention is directed to a case where a physical address space is divided into upper and lower areas, and two types of memory elements having different capacities are mixed to constitute a memory system. Device groups are arranged in separate areas, and the most significant bit (called U / L bit) of the physical address is used as an area segmentation signal to automatically control access to each memory element group. It is. In particular, in the present invention, a memory element or a memory printed board having a small memory capacity is placed in the upper (U)
By allocating to the areas, the physical address space can be contiguous, and the conventional floating address register can be eliminated, thereby simplifying the address control mechanism. FIG. 1 is a diagram illustrating the principle of the present invention. The configuration shown is simplified and illustrated in an exemplary manner for convenience of explanation. Reference numeral 1 denotes an access source CPU (central processing unit). Reference numeral 2 denotes an MCU (storage control device). An address control circuit 3 converts a physical address into an MSU address and performs access control. Reference numeral 4 denotes a configuration control register including memory configuration information. Reference numeral 5 denotes an MSU (main storage device). Reference numeral 6 denotes an upper (U) area of the physical address space, which is specified using the most significant bit of the physical address. In this area, only a group of memory elements having a small memory capacity or a group of memory printed boards on which these are mounted are allocated. In the illustrated example, a group of memory elements 6a of 64KBIT RAM is allocated. 7 is a lower (L) area of the same physical address space, and is specified by using the most significant bit of the physical address.
Here, only a group of memory elements having a large memory capacity or a group of memory printed boards on which these are mounted are assigned. In the illustrated example, a group 7a of memory elements of 256 KBIT RAM is assigned. The address control circuit 3 of the MCU 2 sets the most significant bit (U / L) of the given physical address at a predetermined bit position of the MSU address. The MSU detects the U / L bit, and when U / L = 1, accesses the memory element group in the upper (U) area.
When 0, the memory element group in the lower (L) area is accessed. In FIG. 1, the MCU 2 is a CPU 1 and a CHP (not shown).
Accepts an access request to MSU5. The access request is made using the physical address, and the MCU 2 converts the physical address into a corresponding MSU address and controls access to the memory element of the MSU 5. In the configuration control register 4 of the MCU 2, whether the MSU 5 includes memory elements having different memory capacities, only memory elements having small memory capacities, or only memory elements having large memory capacities , Etc., memory configuration information indicating the interleave format, the number of MSUs used, that is, the degree of multiplexing of the MSUs, are set in advance. The address control circuit 3 of the MCU 2 converts the physical address into an MSU address in a predetermined format according to the memory configuration information. The MSU address includes an address in a memory element (an address in a chip), an interleave address (a memory bank address), and the like. The most significant bit U / L of the physical address is a signal for separating the upper (U) area (when U / L = 1) and the lower (L) area (when U / L = 0) of the physical address space. Therefore, MS
It is directly moved to a predetermined bit position in the U address, for example, the position of the most significant bit or the third upper bit. In the MSU, the U / L bit in the MSU address is detected, and the upper (U) when U / L = 1 via the MSU internal address bus
Control so that only the memory element group in the area (64 KBIT RAM in the figure) can be accessed, and when U / L = 0, control so that only the memory element group in the lower (L) area (256 KBIT RAM in the figure) can be accessed . FIG. 2A shows the format of a physical address, and FIGS. 2B and 2C show the case where memory elements having different memory capacities are mixedly used by the address control circuit 3 of the MCU. Indicates the format of the MSU address to be translated. When the most significant U / L bit of the physical address shown in FIG. 2A is 0 (indicating the lower (L) area of the physical address space), the U / L of the MSU address in FIG. The bit is also 0, and the address portion in the chip is 25
Applied to the memory element group of 6KBIT RAM. When the U / L bit of the physical address is 1, the MSU address shown in FIG. 2C is output. Of this MSU address
The U / L bit is also 1, and the next upper 2 bits are "00". As a result, the lower address portion in the chip which is 2 bits shorter than that in FIG.
Applied to the memory element group of KBIT RAM. The lower fixed bits of each address shown in FIGS. 2A, 2B and 2C are used as an interleave address. It is also possible to configure the MSU 5 in FIG. 1 with a plurality of units that can be accessed independently, and to allocate a physical address space to each unit by dividing the physical address space into lower bits, thereby forming a multiplex structure. The lower MS in the physical address in FIG. 2 (a)
The address part indicates the multiplexed address. Such a format of the physical address and the MSU address can be easily adapted even when only a memory element having the same memory capacity is used. FIGS. 3 (a), (b) and (c) show the case where only a large-capacity memory element (for example, 256KBIT RAM) is used.
It shows the physical address and the format of the converted MSU address. Regarding the MSU address in the chip, the physical address (FIG. 3 (b)) or “1” (FIG. 3 (c)) is both used when the most significant bit U / L is “0” (FIG. 3 (b)). Third
The same bit width as in FIG. FIGS. 4 (a), (b), and (c) show the physical address and the converted MSU address when only a small-capacity memory element (for example, 64 KBIT RAM) is used. In this example, the most significant bit U / L of the physical address is the third
It is at the bit position (Fig. 3 (a)), and in the case of this value (Fig.
In both cases (FIG. 3 (b)) and 1 (FIG. 3 (c)), the same bit width as the intra-chip address of the MSU address is used. As is apparent from the examples of FIGS. 2 to 4,
In the present invention, any case can be dealt with simply by dividing the area into upper (U) and lower (L) areas according to the value of the most significant bit U / L of the physical address. Embodiment FIG. 5 is a logical configuration diagram of a system according to an embodiment of the present invention. In the figure, reference numeral 20 denotes (n + 1) CPUs (CPU-0 to CPU
-N) and 21 are (m + 1) CHPs (CHP-0 to CHP-
m) and 22 are MCUs, 23 is an address control circuit, 23a is a configuration control register, 24 is an MSU frame, and 25 is eight independent MSU buses. The MSU frame 24 is divided into eight memory units MSU0 to MSU7. Each MSU is composed of a MAC (memory access controller) and segment 0 and segment 1, and each MSU is independently accessed to constitute a multiplexed MSU. One MSU has one MAC, segment SEG-0 and SEG-1
Each segment has a U area and an L area that divide the address space into two as shown in FIG. 6, and 16 interleaved memory banks LS (LOGICAL) that traverse the U and L areas. STORAGE). Each memory bank LS includes one or more memory elements (RAM chips)
, And can read and write 72-bit width data, for example. The MCU 22 has eight independent buses with the MSU frame 24, accepts access requests from each of the CPU-0 to CPU-n and each of the CHP-0 to CHP-m, and prevents access conflicts with the MSU frame 24. Check and, if accessible, MS
Access control is performed on each MAC of the MSU frame 24 in parallel via the U bus 25. The address control circuit 23 is a multiplexing control mechanism for that purpose. FIG. 7 shows an embodiment of the address control circuit 23 in FIG. In the figure, reference numeral 30 denotes a port PORT-A for receiving an access address (physical address) from the CPU-0 to CPU-n. Reference numeral 31 denotes a port PORT-B for receiving an access address (physical address) from CHP-0 to CHP-m. An address conversion unit 32 converts a physical address from PORT-A into an MSU address. An address conversion unit 33 converts a physical address from PORT-B into an MSU address. The address conversion units 32 and 33 are provided in the configuration control register shown in FIG.
The content of the address conversion is determined based on the memory configuration information set in advance in 23a. Reference numeral 34 denotes a priority circuit that detects an access conflict due to a match between the access addresses of the PORT-A and the PORT-B, and receives only one of the access requests based on a predetermined priority logic. Reference numeral 35 denotes the same number of selectors as the number of the MSU bus 25 for selecting one of the MSU addresses output from the address conversion units 32 and 33 by the output of the priority circuit 34. 36 is an M for which the MSU address is set via the selector 35
The same number of address registers MSAR as the SU bus 25, and the MSU frame 24 (fifth
MSU addresses are supplied in parallel to the memories MSU0 to MSU7 in FIG. FIG. 8 shows a specific example of the MSU address (see FIGS. 5 and 6). The illustrated MSU address is composed of the 2nd to 25th 24 bits, and the following information is set. Second bit: Switches between the upper (U) area and the lower (L) area of each segment SEG0, SEG1. 21st to 24th bits: 16 memory banks LS0 to LS in each segment are selected. 25th bit: Switching between segments SEG0 / SEG1. 0: Select SEG0 1: Select SEG1 Third, fourth, fifth to 20th bits: Allocated by the on-chip address of each segment. • For 256KBIT RAM, use all bits. • For 64KBIT RAM, use 5 to 20 bits. 9 and 10 show specific examples. Fig. 9 shows the multiplexed configuration of 8MSU, when only 256KBIT RAM is fully mounted and interleaved, and when 256KBIT RAM is used.
The figure shows physical addresses, MSU addresses, and address formats of the MSU internal address bus when a RAM and a 64 KB TI RAM are mixed. FIG. 10 shows each address format of a physical address, an MSU address, and an MSU internal address bus when a 64KBIT RAM is fully mounted and interleaved in an 8MSU multiplex configuration. As shown in FIG. 6, one MSU is interleaved by a plurality of memory banks LS. Each memory bank is divided into segments SEG0 and SEG1, and each segment is further divided into U / L. In FIG. 9, the lower 21 to 28 bits of the physical address given in response to an access request from the CPU 20 or CHP 21 in FIG. 5 are interleave addresses for selecting a memory bank and a segment having a 32-interleave structure. Section (bits 21 to 25) and MS address section (bits 26 to 28) for 8MSU address selection and valid control
, And the upper 2nd to 20th bits become an in-chip address section (3rd to 20th bits) and a U / L designation section (2nd bit). These configuration information are stored in the configuration control register 23 shown in FIG.
is set to a. The MSU address is configured using the 2nd to 25th bits of the physical address. In the MSU address, the U / L is used for a system using only large-capacity memory elements as shown in FIG. 3 and a system using memory elements having different capacities as shown in FIG. The bit is in the position of the second bit.
Therefore, at the time of conversion to the MSU address, the U / L bit in the second bit of the physical address is directly shifted to the second bit of the MSU address as shown in FIG. On the other hand, in the case of a system using only small-capacity memory elements as shown in FIG. 4, as shown in FIG.
The U / L bit in the fourth bit of the physical address is shifted upward by 2 bits to form an MSU address. Similarly, the present invention can be adapted to various memory configuration conditions such as an arbitrary number of MSUs and memory elements of an arbitrary capacity, or full mounting and half mounting. [Effects of the Invention] The present invention provides a simple method of arranging two groups of memory elements having different capacities in upper and lower areas of a physical address space, and separating those accesses by the most significant bit of the physical address. Means can easily configure a memory system in which groups of memory elements of different capacities are mixed,
Since the configuration information for designating the memory configuration can be realized by a simple means of setting it in the configuration control system, the flexibility in designing and manufacturing the memory system can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating an MSU address format when memory devices having different capacities are mixed, and FIG. 3 is a memory device having a large capacity (256 KBIT RAM) only. FIG. 4 is an explanatory diagram of an MSU address format when using only small-capacity memory elements (64 KBIT RAM). FIG. 5 is a logical configuration of a system according to an embodiment of the present invention. FIG. 6, FIG. 6 is a block diagram of the memory array card in the MSU in FIG. 5, FIG. 7 is a block diagram of one embodiment of the address control circuit in FIG. 5, and FIG.
FIG. 9 is an explanatory diagram of an address format, FIG. 9 is an explanatory diagram of address conversion of an interleaved system with a full 8MSU 256KBIT RAM and a mixed system of 64K-256K, and FIG. 10 is an explanatory diagram of an address conversion of an interleaved system with a full implementation of 8MSU 64KBIT RAM. In FIG. 1, 1 is a CPU, 2 is an MCU, 3 is an address control circuit, 5 is an MSU, 6 is an upper (U) area of the physical address space, 7 is a lower (L) area of the physical address space, and 6a is 64 KBIT. RAM memory element group, 7a is a 256KBIT RAM memory element group.

Claims (1)

(57) [Claims] An address control circuit for converting a physical address of an access request given from an access source into an address for each of the plurality of memory elements, and a configuration control register for presetting memory configuration information relating to a memory capacity or the like of each of the plurality of memory elements The address control circuit divides the plurality of memory elements into a first memory element group and a second memory element group based on the memory configuration information, The upper and lower physical addresses of the physical address space of the memory system are allocated to the group and the second memory element group, respectively, and the value of the most significant bit of the physical address is 1
And 0 to control access between the first memory element group and the second memory element group, respectively. At this time, when the plurality of memory elements is only a memory element group having a small memory capacity, In the physical addresses for the first memory element group and the second memory element group obtained as a result of the division, the first high-order bit between the above-mentioned most significant bit and the low-order in-chip address bit is set to 0. In the case where the plurality of memory elements consist only of a group of memory elements having a large memory capacity, the physical format for the first group of memory elements and the second group of memory elements as a result of the division is applied. For the address, a second address format in which an in-chip address bit is arranged following the most significant bit is applied, and the plurality of memory elements are stored in a memory having a small memory capacity. In the case of a group of elements and a group of memory elements having a large memory capacity, a group of memory elements having a small memory capacity is a first memory element group, and a group of elements having a large memory capacity is a second memory element. And the physical address for the first memory element group is the first memory element.
A memory system, wherein the second address format is applied to a physical address for the second group of memory elements. 2. 2. The memory system according to claim 1, wherein the plurality of memory elements are mounted on a plurality of memory printed boards, and the address control circuit performs control for separating access on a memory printed board basis.