JP2937459B2 - Method for forming contact hole in semiconductor device - Google Patents

Description

The present invention relates to a method for forming a contact hole for connecting between elements, between wirings, or between an element and a wiring in a silicon semiconductor device.

[Conventional technology]

Conventionally, an oxide film such as a SiO ₂ film, a PSG film, and a BPSG film has been used as an interlayer insulating film on elements and wirings in a semiconductor device. Those of the interlayer insulating film, for example, dry etching (plasma etching) using CF ₄ based gas, the contact hole has been formed in a semiconductor device.

[Problems to be solved by the invention]

For many current semiconductor devices, the conventional method of forming contact holes is still sufficiently applicable, but problems have arisen for some semiconductor devices.

As an example, SOI (S ilicon on I nsulator ) and can be given a fine device having a shallow junction. Reduction of stray capacitance, an increase in carrier mobility, it since it is effective in reducing the leakage current, especially TFT (T hin Among SOI
A study of F ilm T ransistor) has been actively carried out. In addition, a junction for suppressing a short channel effect in a fine element tends to be shallow.

In the case where the layer to be contacted is thin in this way, if a contact hole is to be formed in the interlayer insulating film by dry etching using a CF ₄ gas, the layer to be contacted is lost by dry etching. The problem came to arise.

That is, considering the non-uniformity in the wafer when using it or CF ₄ based gas contact size itself is smaller, than the time the conventional etching time which is predicted from the average etch rate I was over 50-100%.

However, the silicon thickness and the diffusion layer depth in the TFT are 0.1μ
When the etching rate becomes less than m, there is a possibility that if the etching is performed 50 to 100% more, there is no layer to be contacted.

As one solution, it is conceivable to shorten the dry etching and wet-etch the end with hydrofluoric acid. However, when the silicon film is not a perfect single crystal such as a TFT, but is a polycrystal with a relatively large grain size or a single crystal with many defects, hydrofluoric acid etches the underlying oxide film through the silicon film. (It is not possible to use another insulating film such as a silicon nitride film under the silicon film because of the interface state.)

Therefore, the conventional method of forming an interlayer insulating film mainly from an oxide film and forming a contact hole by dry etching has a drawback that it is difficult to use from the viewpoint of controllability.

[Means for solving the problem]

The method of forming a contact hole in a semiconductor device according to the present invention is a method for forming a contact hole, the method comprising: In a method of forming a contact hole for connecting a wiring or an element formed on a film, a first interlayer insulating film made of a silicon nitride film is formed on the semiconductor substrate along a surface of the concave portion and the convex portion. Covering the surface of the concave portion and the convex portion, and forming a second interlayer insulating film thicker than the first interlayer insulating film on the first interlayer insulating film on the concave portion than on the convex portion. Monitoring the exposure of the silicon nitride film by using a photoresist film as a mask in the second interlayer insulating film on the wiring or the diffusion layer formed in the concave portion. A step of forming a first opening by dry etching for removing the second interlayer insulating film and exposing the first interlayer insulating film; and subsequently, a step of forming the first opening immediately below the first opening. Using the photoresist film as a mask, a second opening is formed in the interlayer insulating film by dry etching under conditions that increase the etching rate of the silicon nitride film, and the wiring or diffusion layer formed in the recess is exposed. And a process.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are longitudinal sectional views in the order of steps for explaining a first embodiment of the present invention.

FIG. 1A shows a state in which a MOS transistor is formed on a silicon substrate 1. A silicon oxide film 4 is formed around a gate 2 and on the surface of an N-type or P-type high concentration diffusion layer 3. Are formed. The high-concentration diffusion layer 3 is formed by ion implantation. It is well known that the characteristics are degraded when directly implanted into the silicon substrate 1 at the time of ion implantation. This is usually done.

On this structure, a thin (20 to 30) first interlayer insulating film is formed.
FIG. 1 (b) shows a state in which a silicon nitride film 5 and a thick interlayer BPSG film 6 as a second interlayer insulating film are formed.

Next, using a photoresist film (not shown) as a mask,
First, the interlayer BPSG film 6 is dry-etched by a predetermined thickness with CF ₄ + H ₂ gas. Subsequently, without removing the photoresist film, the interlayer BPSG film 6 is subjected to wet etching using a buffered hydrofluoric acid solution to form a contact hole 7 as a first opening reaching the surface of the silicon nitride film 5. By using the silicon nitride film 5 as a stopper,
The contact hole 7 having the structure shown in FIG. 1C can be formed with good uniformity over the entire surface of the wafer.

After that, without removing the photoresist film, CF ₄ + H
Using dry etching with _two gases, the silicon nitride film 5 and the silicon oxide film 4 immediately below the contact hole 7 which is the first opening,
Is formed. Further, when the photoresist film is removed, as shown in FIG. 1 (d), a contact hole 7 as a first opening and a contact hole 7a including a second opening are formed.

Since the final dry etching only etches a film of about 30 to 45 nm, even if overetching of about 20% is performed in anticipation of non-uniformity, the high concentration diffusion layer 3 remains
Only 2nm is removed. At present, this high concentration diffusion layer 3
Is 0.2 to 0.25 μm, but in the future,
Since the thickness is required to be 0.1 to 0.15 μm, the necessity of reducing the over-etching is further increased.

FIGS. 2 (a) and 2 (b) are longitudinal sectional views in the order of steps for explaining a second embodiment of the present invention. The present embodiment relates to a silicon element formed on an insulating film, that is, a so-called SOI structure. In SOI, since the silicon layer can be expected to improve the characteristics when thin, SIMOX (S eparatio
n by Im planted Ox ygen) and studies in the direction of thinning the poly-Si based TFT is being promoted, 30 to 50 nm even at present
Some thin films are being considered.

FIG. 2A is a cross-sectional view corresponding to a view in which FIG. 1B of the first embodiment is applied to SOI. That is, a thick silicon oxide film 18 is formed on a silicon substrate 11, a silicon thin film 19 is further formed thereon, and a MOS transistor having a gate 12 and a high concentration diffusion layer 13 is formed thereon. On the surfaces of the gate 12 and the high concentration diffusion layer 13, a thin silicon oxide film 14, a thin silicon nitride film 1
5, and a thick interlayer PSG film 16, which is a second interlayer insulating film, is formed.

Subsequently, by the same method as in the first embodiment, first, while monitoring the exposure of the silicon nitride film 15, CF ₄
The first opening is formed by dry etching the thick interlayer PSG film 16 using a system gas. Next, the silicon nitride film 15 is etched under the condition that the etching rate of the silicon nitride film is increased, and further the thin silicon oxide film 14 is
Is etched to form a second opening,
As shown in FIG. 2 (b), contact holes 17 penetrating the three insulating films are formed.

In the case of this embodiment, the thickness of the high concentration diffusion layer 13 is
It is about 30 to 50 nm, and it is highly necessary to reduce over-etching compared to the first embodiment. In this case, the buffered hydrofluoric acid does not affect the silicon oxide film 18 under the silicon thin film 19 because the crystallinity is relatively good, and the shape is deteriorated because etching with the buffered hydrofluoric acid can be completed in a short time. For example, a buffered hydrofluoric acid solution can be used. As an advantage, there is no problem of reduction of the silicon thin film 19 or deterioration due to ion etching.

In the case of SOI, there is a problem of leakage current due to incompleteness of the silicon film.However, since the leakage current is suppressed by thinning the silicon film, there is a high possibility that further thinning will be achieved in the future. The effectiveness of the example is expected to increase.

〔The invention's effect〕

As described above, according to the present invention, in forming a contact hole in a semiconductor device, a thin first interlayer insulating film and a thick second interlayer insulating film are formed on a layer to be contacted, and the contact hole is formed. In the opening, only the second interlayer insulating film is first etched with good uniformity by using selective etching or monitoring the gas to be etched, and then the first thin interlayer insulating film is etched. By doing so, a contact hole penetrating to a portion of an element or the like to be contacted is formed, and the contact hole can be formed with almost no cutting of a layer to be contacted.

In a normal MOS transistor, a method of implanting phosphorus or boron ions after forming a contact hole for the purpose of compensating for the removal of the high-concentration diffusion layer by over-etching is also adopted. Requires activation of impurities by heat treatment. However, the need to make the junction shallower
It is necessary to reduce heat treatment more and more,
The present invention is also a desirable method in that it does not require such heat treatment.

[Brief description of the drawings]

1 (a) to 1 (d) are longitudinal sectional views in the order of steps for explaining a first embodiment of the present invention, and FIGS. 2 (a) and (b) are second embodiments of the present invention. FIG. 6 is a longitudinal sectional view in the order of steps for explaining the method. 1,11 ... silicon substrate, 2,12 ... gate, 3,13 ... high concentration diffusion layer, 4,14,18 ... silicon oxide film, 5,15 ... silicon oxide film, 6 ... interlayer BPSG film, 7,7a, 17… Contact hole, 1
6 ... interlayer PSG film, 19 ... silicon thin film.

Claims (1)

(57) [Claims] An interconnect or diffusion layer formed in a concave portion of a semiconductor substrate, penetrating an interlayer insulating film formed on a semiconductor substrate having an uneven surface, and a wiring or element formed on the interlayer insulating film. Forming a first interlayer insulating film made of a silicon nitride film on the semiconductor substrate along the surface of the concave portion and the convex portion, and forming a surface of the concave portion and the convex portion on the semiconductor substrate. A step of covering; a step of forming a second interlayer insulating film thicker than the first interlayer insulating film on the first interlayer insulating film so as to be thicker on the concave portion than on the convex portion; The second line on the wiring or diffusion layer formed in
Forming a first opening in the interlayer insulating film by dry etching using a photoresist film as a mask and removing the second interlayer insulating film while monitoring the exposure of the silicon nitride film; A step of exposing one interlayer insulating film; and a condition in which the etching rate of the silicon nitride film is increased by using the photoresist film as a mask in the first interlayer insulating film immediately below the first opening. Forming a second opening by dry etching, and exposing a wiring or a diffusion layer formed in the concave portion.