JP2936868B2 - Message packet routing method for array processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array processor for performing interprocessor communication by linking processors.

[0002]

2. Description of the Related Art Conventionally, as a method of realizing an array processor, there are 1) a method of performing only communication between adjacent processors, and 2) a method of realizing communication between remote processors using a router.

[0003] In the method in which only communication between adjacent processors is performed, the amount of hardware required for communication between the processors is relatively small, but when communication is performed between remote processors, a path from a sending processor to a receiving processor is required. Since communication between adjacent processors is repeated between the above processors, the communication time and the load on each processor on the communication path become problems. For an array processor that performs communication only between adjacent processors, see S.A. Y.
Kung, “Wavefront ArrayProc
essors-Concepts to Implem
entation ”, IEEE Computer, J
uly 1987, pp 18-33. On the other hand, in the method using a router, the amount of hardware required for inter-processor communication is large, but since communication is performed from the sending processor to the receiving processor via the router, the communication time is relatively short, and other processors are used. The load on the system does not matter.

[0004] The routing method in the method using a router is determined depending on the form of connection of the processors. For example, in the two-dimensional mesh connection method, routing is performed by specifying the number of steps in the east-west direction (the number of hops) and the number of steps in the north-south direction (the number of hops). W. J. Da
lly, "A VLSI Architectureref.
or Current Data Struct
ures ", Kluwer Academic Pre
Section 5.3.3 of ss, 1987 describes a system that performs the routing described above.

[0005]

However, since the route used in the conventional routing method is fixed,
Depending on the application, traffic may increase in one route, which may cause a communication bottleneck and hinder parallel processing. In the case of broadcasting data to a plurality of processors, communication has to be performed for each destination processor. Therefore, it is possible to use a rewritable routing table so that the routing can be freely set by a program through processing and the data can be broadcast from the transmitting processor to a plurality of processors in one message communication. There is a problem that the size of the routing table increases as the number increases.

An object of the present invention is to provide an array processor routing method capable of suppressing an increase in the size of a routing table when the number of processors increases.

[0007]

According to a first aspect of the present invention, there is provided an array processor comprising a plurality of arithmetic processors and a low-dimensional mesh interconnection network for performing communication between the processors. Alternatively, a method of routing a message packet to a plurality of destination processors, wherein for each of the arithmetic processors in the network, a message generated from the arithmetic processor or transmitted from one of a plurality of connected links connected thereto. Means for transferring a packet to a designated one or more destinations among a plurality of connection links or arithmetic processors, and an operation for designating one or more links or an arithmetic processor for transferring a message packet from address information in the message packet To the processor Dividing an array processor having rewritable routing information storage means into a plurality of clusters, and allocating all or some addresses in routing information storage means of all or some processors in the cluster to processors in another cluster Thus, a message can be transferred to a processor outside the cluster.

[0008] A second invention provides a plurality of arithmetic processors,
A method of routing message packets from a source processor to one or more destination processors in an array processor comprising a low-dimensional mesh interconnect network for communicating between the processors, the method comprising: For each arithmetic processor, a message packet generated from the arithmetic processor or transmitted from one of the plurality of connection links connected to the arithmetic processor is sent to one or more destinations designated by the plurality of connection links or the arithmetic processor. An array processor comprising: a transfer unit; and a routing information storage unit that can be rewritten by an arithmetic processor that specifies one or more links or an arithmetic processor that transfers the message packet from the address information in the message packet. When the message is divided into a plurality of clusters, one address is assigned to each cluster, and the sending processor sends a message packet to a destination processor belonging to a different cluster, a cluster address and a local address within the cluster are assigned in the packet, By performing routing by address, the packet is transferred to the gateway processor having the cluster address in the cluster to which the destination processor belongs. When the gateway processor receives a message packet in which the cluster address is specified, the gateway processor performs routing by using the local address. By setting and retransmitting the packet, the packet is transferred to the destination processor.

According to a third invention, in the routing method according to the second invention, in each cluster, a plurality of processors in the cluster connected to the outside of the cluster are gateway processors having the same cluster address, and the processors outside the cluster are each a gateway processor. By setting routing information so that the processors can perform routing without crossing each other, a plurality of messages are simultaneously transferred to the processors in the cluster.

[0010]

The principle of the present invention will be described below. In the message packet routing method according to the first invention, the routing table is accessed by using the destination address information added in the message packet to obtain information on the transfer destination. In the routing table, bits for setting whether or not to transfer to all possible transfer destinations (connection links and processors) are assigned, so that transfer to a plurality of links or arithmetic processors is possible.

In a cluster in which an address is uniquely assigned to each processor, a transfer destination for a part of addresses in a routing table of a set of a part of continuous processors in contact with an adjacent cluster is set to be transferred to the adjacent cluster. Thus, the packet specifying the address can be transferred to the processor having the corresponding address in the adjacent cluster without being transferred to the processor of the corresponding address in the cluster to which the sending processor belongs.

According to the above method, it is possible to configure a processor array in which a plurality of clusters limited by the size of the routing table are connected.

In the message packet routing method according to the second invention, a routing table is accessed by using destination address information added in the message packet to obtain transfer destination information. In the routing table, bits for setting whether or not to transfer to all possible transfer destinations (connection links and processors) are assigned, so that transfer to a plurality of links or arithmetic processors is possible. Further, the transfer destination for the cluster address and the intra-cluster local address is specified in the routing table. Here, the cluster address is assigned to some or all processors in the cluster.

When the transmitting processor transfers a message packet to a destination processor belonging to a different cluster, a cluster address and a local address within the cluster are added to the message, and routing is first performed by using the cluster address to thereby execute the processor within the cluster to which the destination processor belongs. (Hereinafter referred to as gateway processor)
Is transferred to. The gateway processor fetches the message packet into the processor, takes out the local address in the cluster in the packet, sets it to perform routing using this, and then retransmits it.
This allows the message to be sent to the destination processor.

According to the above method, by dividing N ² processors into M ² clusters, the size of the routing table required for each processor is calculated from N ² to the number of local addresses in the cluster (N / M). (N / M) ² + M ² obtained by adding ² and the number M ^{2 of} cluster addresses.

In the message packet routing method according to the third invention, when a plurality of processors in contact with the outside of the cluster in each cluster are gateway processors having the same cluster address, the message packet transferred to the cluster is transferred to all gateway processors. Will be done. Therefore, when the number of gateway processors is L, the processors outside the cluster are divided into L gateway processors and L processor sets that are continuous with each other. Routing can be performed. As a result, message transfer into a maximum of L clusters can be performed simultaneously.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the first invention, in which an array processor in which unit processor nodes 10 connected to four links are connected in a two-dimensional lattice is first and second in a two-dimensional lattice. 2 shows a configuration divided into two clusters.

FIG. 2 shows the configuration of the unit processor node 10. The unit processor includes an arithmetic processor 21, a processor port 22, a first communication port 23, a second communication port 24, a third communication port 25, a fourth communication port 26, a control circuit 27, and a routing table 28. Is done.

A first communication port 23, a second communication port 24, a third communication port 25, and a fourth communication port 26
Receives the message packets sent from the other connected unit processor nodes, extracts the destination address information in the message packets, and sends them to the control circuit 27. The processor port 22 extracts the destination address information of the message packet written from the arithmetic processor 21 and sends it to the control circuit 27.

The control circuit 27 determines the first communication port 23, the second communication port 24, the third communication port 25, and the fourth communication port 26 to which the routing table 28 is to be transferred based on the transmitted destination address. Either one or a message transfer control signal is sent to the processor port 22. At this time, the routing table includes the first communication port 23, the second communication port 24, the third communication port 2
5, 4th communication port 26, 5 of processor port 22
It is composed of a readable and writable memory having an address space in which 5 bits assigned to each destination one bit at a time is one address word, and a fixed number of additional numbers is added to the number of processors. The routing table 28 can be set and changed by the arithmetic processor 21.

First communication port 23, second communication port 24, third communication port 25, fourth communication port 26
When a message transfer control signal is received, the transmitted message sends a packet to an adjacent unit processor node connected thereto. The processor port 22 receives and stores the transmitted message upon receiving the message transfer control signal so that the arithmetic processor 21 can read it.

FIG. 3 shows an example of message transfer. FIG.
Denotes an array processor connected in a two-dimensional grid pattern shown in FIG. In FIG. 3, P in each unit processor indicates an arithmetic processor. The first cluster of array processors shown in FIG. 3 includes a first unit processor 31 having a local address 1, a second unit processor 32 having a local address 2, a third unit processor 33 having a local address 3, The second cluster is composed of a fourth unit processor 34 having a local address 3 and a fourth unit processor 34 having an address 4.
5. Sixth unit processor 3 having local address 1
6. Seventh unit processor 3 having local address 2
7, etc. Among them, the third unit processor 33 and the fourth unit processor 34 are nodes that can transfer data to another cluster in the first cluster.

FIG. 4 shows a routing table of each processor. (A) shows the routing tables for the first, third, fourth and sixth unit processors, and (b) shows the second and third unit processor routing tables.
The seventh unit processor routing table is
(C) shows a fifth unit processor routing table. In FIG. 4, the column of P is an arithmetic processor,
The column of N is upward, the column of E is rightward, the column of S is downward, W
Are bits for designating transfer to the left. The message packet sent from the arithmetic processor of the third unit processor 33 is a local address 2 outside the cluster.
And transferred to processors in different clusters.
First, it is sent to the fourth unit processor 34 based on the value E of the address 2 in the routing table (FIG. 4A) of the third unit processor 33, and the fourth unit processor 34 routes the fourth unit processor 34. The value E of the address 2 in the table (FIG. 4A) is sent to the fifth unit processor 35 belonging to the second cluster, and the fifth unit processor 35 sends the routing table of the fifth unit processor 35 (FIG. 4A). 4 (c)) is sent to the sixth unit processor 36 according to the value N of the address 2. The sixth unit processor 36 sends the sixth unit processor 36 to the seventh unit processor 37 according to the value E of the address 2 in the routing table (FIG. 4A). In the seventh unit processor 37, the value is written to the processor port of the seventh unit processor 37 by the value P of the address 2 in the routing table (FIG. 4B) of the seventh unit processor 37.

As described above, the message transfer route is shown in FIG.
Is determined by the setting of the routing table of each unit processor shown in FIG. 3 and the packet transmitted from the third unit processor 33 belonging to the first cluster has the local address 2 in the first cluster despite the fact that the packet has the local address 2. 2nd unit processor 3 having 2
2 is transferred to the seventh unit processor having the local address 2 in the second cluster.

FIG. 5 shows an embodiment of the second invention.
Unit processor nodes 10 connected to two links
A configuration in which an array processor connected in a dimensional lattice is divided into four clusters of a first, second, third and fourth two-dimensional lattice is shown. The configuration of the unit processor node 10 is as follows.
This is the same as the configuration shown in FIG.

FIG. 6 shows an example of message transfer. FIG.
Denotes an array processor connected in a two-dimensional lattice shown in FIG. In FIG. 6, P in each unit processor indicates an arithmetic processor. The first cluster of the array processor shown in FIG. 6 includes a first unit processor 31, a second unit processor 32, a third unit processor 33, and the like, and the second cluster is a fourth unit processor 34,
Fifth unit processor 35, sixth unit processor 3
The third cluster is composed of a seventh unit processor 37, an eighth unit processor 38, and the like. Among them, the fourth unit processor 34 is a gateway node of the second cluster, and the seventh unit processor 37 is a gateway node of the third cluster.

FIG. 7 shows a routing table of each processor. (A) is the first, second, third and fourth unit processor routing tables, and (b) is the fifth
And (c) shows the seventh unit processor routing table, and (d) shows the eighth unit processor routing table. In FIG. 7, the column P indicates an arithmetic processor, the column N indicates an upward direction, the column E indicates a rightward direction, the column S indicates a downward direction, and the column W indicates a bit for specifying a transfer to the left.

The message packet sent from the arithmetic processor of the first unit processor 31 has a cluster address 200 and a local address 2 within the cluster.
Since the message is transferred to a processor in a different cluster, routing is first performed by using the cluster address. First, the first unit processor 31 is sent to the second unit processor 32 based on the value E of the address 200 in the routing table (FIG. 7A). It is sent to the third unit processor 33 according to the value E of the address 200 in the routing table (FIG. 7A), and the third unit processor 33 routes the second unit processor 33 (FIG. 7A). Is sent to the fourth unit processor 37 according to the value E of the address 200 of the third unit. In the fourth unit processor 34, the value E of the address 200 in the routing table (FIG. 7A) of the fourth unit processor 34
Is sent to the fifth unit processor 35.

In the fifth unit processor 35, the routing table of the fifth unit processor 35 (FIG. 7)
It is sent to the sixth unit processor 36 by the value S of the address 200 in (b)). The sixth unit processor 36 sends the sixth unit processor 36 to the seventh unit processor 37 based on the value S of the address 200 in the routing table (FIG. 7B) of the sixth unit processor 36.

In the seventh unit processor 37, the routing table of the seventh unit processor 37 (FIG. 7)
The data is written to the processor port of the seventh unit processor 37 which is the gateway processor of the third cluster by the value P of the address 200 in (c)). The arithmetic processor of the seventh unit processor resets the routing so as to perform the routing based on the intra-cluster local address 2 in the message packet and transmits the message packet. Seventh
The message packet sent from the arithmetic processor of the unit processor 37 is sent to the eighth unit processor 38 according to the value S of the address 2 of the routing table of the seventh unit processor 37, and the eighth unit processor 38
Then, the data is written to the processor port of the eighth unit processor 38 as the destination processor by the value P of the address 2 in the routing table (FIG. 7D) of the eighth unit processor 38.

As described above, the path of the message transfer is determined by the setting of the routing table of each unit processor shown in FIG.

Next, an embodiment of the third invention will be described. The division of the address processor into clusters is the same as in FIG. 5, and the configuration of the unit processor node is the same as the configuration shown in FIG.

FIG. 8 shows an example of the message transfer shown in FIG.
FIG. 8 shows an array processor connected in a two-dimensional grid pattern shown in FIG. In FIG. 8, P in each unit processor
Indicates an arithmetic processor. The first cluster of the array processors shown in FIG. 8 includes a first unit processor 31, a second unit processor 32, a third unit processor 33, and a ninth unit processor.
Unit processor 39, tenth unit processor 40,
The second cluster is composed of a fourth unit processor 34, a fifth unit processor 35, a sixth unit processor 36, a twelfth unit processor 42, and the like. Third cluster seventh
Unit processor 37, eighth unit processor 38, thirteenth unit processor 43, fourteenth unit processor 4
4, etc. Among them, the fourth unit processor 34 and the twelfth unit processor 42 are gateway nodes of the second cluster, and the seventh unit processor 37 and the thirteenth unit processor 43 are gateway nodes of the third cluster.

FIGS. 9 and 10 show a routing table of each processor. FIG. 9A shows the routing tables for the first, second, third, fourth, ninth, tenth, and eleventh unit processors, and FIG. 9B shows the fifth, sixth, and twelfth unit processors. FIG. 9C shows the routing table for the seventh unit processor, FIG. 9D shows the routing table for the eighth unit processor, and FIG. 10E shows the routing table for the thirteenth unit processor. The routine table is shown in FIG.
3 shows a unit processor routing table.

In FIGS. 9 and 10, a column P designates an arithmetic processor, a column N designates an upward direction, a column E designates a rightward direction, a column S designates a downward direction, and a column W designates a transfer direction to the left. It is.

The message packet sent from the arithmetic processor of the first unit processor 31 has a cluster address 200 and an intra-cluster local address 2, and is a message transfer to a processor in a different cluster. . First, the first unit processor 31 is sent to the second unit processor 32 based on the value E of the address 200 in the routing table (FIG. 9A). In the second unit processor 32, the routing of the second unit processor 32 is performed. It is sent to the third unit processor 33 according to the value E of the address 200 of the table (FIG. 9A), and the third unit processor 33 stores the value in the routing table of the third unit processor 33 (FIG. 9A). It is sent to the fourth unit processor 34 by the value E of the address 200. The fourth unit processor 34 sends the fourth unit processor 34 to the fifth unit processor 35 based on the value E of the address 200 in the routing table (FIG. 9A) of the fourth unit processor 34.

In the fifth unit processor 35, the routing table of the fifth unit processor 35 (FIG. 9)
It is sent to the sixth unit processor 36 by the value S of the address 200 in (b)). The sixth unit processor 36 sends the sixth unit processor 36 to the seventh unit processor 37 based on the value S of the address 200 in the routing table (FIG. 9B).

In the seventh unit processor 37, the routing table of the seventh unit processor 37 (FIG. 9)
The value is written to the processor port of the seventh unit processor 37 which is the gateway processor of the third cluster by the value P of the address 200 in (c)). The arithmetic processor of the seventh unit processor resets the routing so as to perform the routing using the intra-cluster local address 2 in the message packet and retransmits the message packet. The message packet sent from the arithmetic processor of the seventh unit processor 37 is
The value S of the address 2 in the routing table of
Of the eighth unit processor 38, which is the destination processor, based on the value P of the address 2 in the routing table (FIG. 9D) of the eighth unit processor 38. Written to the processor port.

On the other hand, a message packet sent from the arithmetic processor of the ninth unit processor 39 has a cluster address 200 and a local address 3 within a cluster, and is a message transfer to a processor in a different cluster. Perform routing. First, the ninth unit processor 39 is sent to the tenth unit processor 40 by the value E of the address 200 in the routing table (FIG. 9A). Address 200 in the routing table (FIG. 9A)
Is transmitted to the eleventh unit processor 41 according to the value E of the twelfth unit processor in the eleventh unit processor 41 by the value E of the address 200 in the routing table (FIG. 9A) of the eleventh unit processor 41. The routing table of the twelfth unit processor 42 is sent to the twelfth unit processor 42 (FIG. 9B).
Is sent to the thirteenth unit processor 43 according to the value S of the address 200 of.

In the thirteenth unit processor 43, the thirteenth
Table of the unit processor 43 of FIG.
The value is written to the processor port of the thirteenth unit processor 43 which is the gateway processor of the third cluster by the value P of the address 200 in (e)). The arithmetic processor of the thirteenth unit processor resets the routing so as to perform the routing using the intra-cluster local address 3 in the message packet, and transmits the message packet.
The message packet sent from the arithmetic processor of the thirteenth unit processor 43 is the thirteenth unit processor 4.
3 is sent to the fourteenth unit processor 44 based on the value S of the address 3 of the routing table, and the fourteenth unit processor 44 transmits the value of the address 3 in the routing table of the fourteenth unit processor 44 (FIG. 10F). The fourteenth unit processor 44 which is the destination processor by P
Is written to the processor port.

As described above, the message transfer path is determined by the setting of the routing table of each unit processor shown in FIGS.

[0043]

As described above, according to the first aspect of the present invention, an array cluster is formed by the size of the routing table in the address processor, and the transfer destination of some processors in the cluster is set to the processor in another cluster. By setting, a plurality of clusters can be combined to configure a large-scale array processor.

According to the second aspect of the present invention, a message packet of an arbitrary route can be sent by rewriting the cluster address and the local address in the routing table in the array processor.

Further, according to the third aspect, it is possible to simultaneously send a message packet from a plurality of unit processors to a plurality of unit processors in one cluster.

[Brief description of the drawings]

FIG. 1 is a diagram showing cluster division in the first invention.

FIG. 2 is a diagram illustrating a configuration of a unit processor.

FIG. 3 is a diagram showing an example of a message transfer according to the first invention.

FIG. 4 is a diagram illustrating a routing table of each unit processor in the example of FIG. 3;

FIG. 5 is a diagram showing cluster division in the second invention.

FIG. 6 is a diagram showing an example of a message transfer according to the second invention.

FIG. 7 is a diagram illustrating a routing table of each unit processor in the example of FIG. 6;

FIG. 8 is a diagram showing an example of a message transfer according to the third invention.

FIG. 9 is a diagram illustrating a routing table of each unit processor in the example of FIG. 8;

FIG. 10 is a diagram showing a routing table of each unit processor in the example of FIG. 8;

[Explanation of symbols]

 Reference Signs List 10 unit processor node 21 arithmetic processor 22 processor port 23 first communication port 24 second communication port 25 third communication port 26 fourth communication port 27 control circuit 28 routing table 31 first unit processor 32 second Unit processor 33 Third unit processor 34 Fourth unit processor 35 Fifth unit processor 36 Sixth unit processor 37 Seventh unit processor 38 Eighth unit processor 39 Ninth unit processor 40 Tenth unit processor 41 11th unit processor 42 12th unit processor 43 13th unit processor 44 14th unit processor

Claims (3)

(57) [Claims] 1. An array processor comprising a plurality of arithmetic processors and a low-dimensional mesh interconnection network for communication between processors, wherein a message packet is routed from a source processor to one or more destination processors. A message packet generated from an arithmetic processor or sent from one of a plurality of connected links for each arithmetic processor in the network. Means for forwarding to one or more destinations designated from among them, and routing rewritable by an arithmetic processor which designates one or more links or arithmetic processors for forwarding the message packet from the address information in the message packet By dividing the array processor having the information storage means into a plurality of clusters and assigning all or some addresses in the routing information storage means of all or some processors in the cluster to processors in another cluster, A method for routing a message packet, wherein the method enables message transfer to a processor. 2. An array processor comprising a plurality of arithmetic processors and a low-dimensional mesh interconnection network for communication between the processors, wherein a message packet is routed from a source processor to one or more destination processors. A message packet generated from an arithmetic processor or sent from one of a plurality of connected links for each arithmetic processor in the network. Means for forwarding to one or more destinations designated from among them, and routing rewritable by an arithmetic processor which designates one or more links or arithmetic processors for forwarding the message packet from the address information in the message packet When the array processor having the information storage means is divided into a plurality of clusters, one address is assigned to each cluster, and the transmitting processor sends a message packet to a destination processor belonging to a different cluster, the packet includes the cluster address and the Is transferred to a gateway processor having a cluster address in the cluster to which the destination processor belongs by performing routing by the cluster address. If the gateway processor receives a message packet in which the cluster address is specified, A method for routing a message packet, wherein the message is transferred to a destination processor by resetting the routing so as to perform routing by an address and retransmitting the packet. 3. A message packet routing method for an array processor according to claim 2, wherein in each cluster, a plurality of processors in the cluster connected to the outside of the cluster are gateway processors having the same cluster address, and the processors outside the cluster are each a processor. A message packet routing method, wherein a plurality of message transfers to processors in a cluster are simultaneously performed by setting routing information so that routing can be performed without intersecting with a gateway processor.