JP2929778B2 - Subtitle super signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subtitle super signal processing circuit of a television receiver or a video projector having a superimpose function, using a dot matrix video display device having a small number of pixels.

[0002]

2. Description of the Related Art In recent years, with the spread of laser disk players and the like, the opportunity to enjoy movie software and the like at home has increased. Among such movie software, there is a movie with a cinemascope size having an aspect ratio of 9:21, and in the foreign movie software, a Japanese translation of a subtitle supermarket is placed above or below the 9:21 movie. There is something. Such software is used for aspect ratio 9:16 or 9: 2.
In case of 1 wide screen image display device, if the image is projected to fill the entire screen, it will not be possible to display the superimposed subtitles.
Some television systems having such a wide screen function have a superimpose function for fitting a superimposed subtitle into a 9:21 video.

Further, with the enlargement of the screen of the television receiver, a light valve image projector using a liquid crystal image display device has already been commercialized. However, in a dot matrix type image display device such as a liquid crystal image display device,
When the superimpose function is installed, there is no problem as long as there is a sufficient number of pixels. For example, in the case of the NTSC system, the video information of the even field and the odd field must be displayed on the same pixel in the vertical direction. 26 pixels
In a popular type dot matrix image display device having 0 pixels or less, image information of even and odd fields is averaged on the screen, and the vertical contour is blurred or flickers, and it is difficult to read kanji having many strokes. become. Even in a television system using such a popular type of dot matrix image display device, there is a problem of improving the quality of superimposed subtitle characters and making kanji easy to read.

Hereinafter, a conventional subtitle super signal processing circuit will be described with reference to the drawings. FIG. 4 shows a block diagram of a conventional subtitle super signal processing circuit. In FIG. 4, reference numeral 21 denotes an A / D converter for converting an analog input Y signal to the subtitle super signal processing circuit into a digital signal. Reference numeral 22 indicates whether the input Y signal is a signal of an even field or a signal of an odd field. Hi is applied to an even field, and Lo is applied to an odd field.
Is output. Reference numeral 23 denotes an even field memory for storing data of a subtitle superimposed portion of the even field of the Y signal digitized by the A / D converter 21. Reference numeral 24 denotes an odd field memory for storing data of a subtitle superimposed portion of an odd field of the Y signal digitized by the A / D converter 21. Reference numeral 25 denotes a write timing control circuit for generating a write pulse for storing the data of the subtitle portion of the digitized Y signal of each field in the even field memory 23 and the odd field memory 24. Reference numeral 26 denotes an AND gate which takes the product of a write pulse output from the write timing control circuit 25 and a field determination signal output from the field determination circuit 22 in order to store only the data of the even field in the even field memory 23. Reference numeral 27 denotes a read timing control circuit that generates a read pulse for reading digitized data of the subtitle superimposed portion of each field stored in the even field memory 23 and the odd field memory 24. Numeral 28 indicates that the data of the even field stored in the even field memory 23 is read only in the even field, so that the product of the read pulse output from the read timing control circuit 27 and the field determination signal output from the field determination circuit 22 is used. AND gate that takes Reference numeral 29 denotes an address control circuit for setting an address of the even field memory 23. An inverter 30 inverts the field discrimination signal output from the field discrimination circuit 22. 31
Since the odd field memory 24 stores only the data of the odd field, the write timing control circuit 2
AND which is the product of the write pulse output from the inverter 5 and the inverted field discrimination signal output from the inverter 30
The gate. Reference numeral 32 denotes the product of the read pulse output from the read timing control circuit 27 and the inverted field discrimination signal output from the inverter 30 because the data of the odd field stored in the odd field memory 24 is read only in the odd field. AND gate. 33 is an address control circuit for setting an address of the odd field memory 24. 34 is a buffer for the output line of the even field memory 23;
Reference numeral 35 denotes a buffer for an output line of the odd-numbered field memory 24, which has a switching function and is closed only when the data of each field is read by the outputs of the AND gates 28 and 32. A D / A 36 converts the subtitle data of each field output from the buffers 34 and 35 into an analog signal.
It is a converter. Reference numeral 37 denotes a primary color signal / subtitle super combining circuit for inserting the subtitle super signal converted into an analog signal by the D / A converter 36 into each of the analog R / G / B primary color signals. 38 is the R / G / B synthesized with the subtitle superimposed by the primary color signal / subtitle superimposition circuit 37
This is a dot matrix image display device that displays each primary color signal as an image.

The operation of the subtitle super signal processing circuit configured as described above will be described below with reference to FIG. FIG. 5 is a timing chart of a conventional subtitle super signal processing circuit. First, the analog Y signal input to the subtitle super signal processing circuit FIG.
The signal is converted into a digital signal by the converter 21. The field determination circuit 22 determines whether the input analog Y signal is an even field or an odd field, and outputs the result as a field determination signal (FIG. 5C).

The Y signal converted to a digital signal by the A / D converter 21 is sent to an even field memory 23 and an odd field memory 24. At this time, in order to store the digital signal of the superimposed subtitle portion in the even field memory 23 and the odd field memory 24, the write timing control circuit 25 changes the write timing pulse diagram (d) adjusted to the subtitle position from the V pulse and the H pulse, to make. The even field write timing pulse (FIG. 5 (f)) obtained by taking the product of the write timing pulse and the field discrimination signal by the AND gate 26 is given to the even field memory 23, so that the digital signal of the subtitle super portion of the even field is obtained. It is stored in the even field memory 23. Similarly, the odd field write timing pulse obtained by taking the product of the write timing pulse and the inverted field discrimination signal inverted by the inverter 30 by the AND gate 31 for the odd field.
By applying (h) to the odd field memory 24, the digital signal of the caption super portion of the odd field is stored in the odd field memory 24.

[0007] The subtitle data stored in the even field memory 23 and the odd field memory 24 must be read at a preset timing in order to be combined with the original video signal. For this reason, the read timing control circuit 27 generates a read timing pulse diagram 5 (e) from the V pulse and the H pulse, and the product of the field discrimination signal and the AND gate 28 obtains the even field read timing pulse diagram 5 (5). g)
And the product of the inverted field discrimination signal and the AND gate 32
Thus, an odd field read timing pulse is formed as shown in FIG. 5 (i). Then, the even field memory 23 and the odd field memory 24
, The subtitle data of the even field is read at a preset timing of the next even field, and the subtitle data of the odd field is read at a preset timing of the next odd field. The read subtitle data is transferred to buffers D and D through buffers 34 and 35, respectively.
The signal is again converted into an analog signal by the / A converter 36, and is combined with the analog R / G / B primary color signal by the primary color signal / subtitle super combining circuit 37. That is, the subtitle super extracted in the 2n field is inserted into the video of the 2n + 2 field, and the subtitle super extracted in the 2n + 1 field is inserted into the video of the 2n + 3 field and superimposed. Then, the superimposed R / G / B primary color signal is sent to the dot matrix image display device 38 and displayed as an image.

[0008]

However, in such a conventional configuration, when used in a dot matrix type image display device such as a liquid crystal image display device, there is no problem if a sufficient number of pixels are provided. The video signal of the field and the odd field must be displayed on the same pixel. For example, in the case of the NTSC system, in a popular type dot matrix video display device in which the number of pixels in the vertical direction is 260 pixels or less, the even field and the Image information with odd fields is averaged on the screen, and gray pixels may appear at the boundary between white and black in the vertical direction, and the outline may be blurred.
Alternatively, there is a problem that flicker appears.

The present invention solves the above-mentioned problem, and the video signals of the even field and the odd field must be displayed on the same pixel. For example, in the case of the NTSC system, the number of pixels in the vertical direction is 260. When using a popular type dot matrix image display device with pixels or less,
It is an object of the present invention to provide a superimposed subtitle signal processing circuit which makes the outline of a superimposed subtitle superimposed character clear and enlarges the character vertically twice so as to make the character easy to read.

[0010]

In order to achieve the above object, a subtitle super signal processing circuit according to the present invention comprises: an A / D converter for converting an analog video signal into a digital signal;
A memory for storing even-field and odd-field subtitle data from the digitized video signal, and even-field and odd-field subtitle data in the memory, and all even and odd fields A memory control circuit for alternately reading the data of the even and odd fields stored in the memory at 1H line intervals, a D / A converter for converting a digital signal read from the memory into an analog signal, And a combining circuit for inserting the processed subtitle character signal into the original video signal.

[0011]

According to the present invention, the video signal of the superimposed subtitle portion is extracted from the video signal, the extracted video signal is divided into an even field and an odd field, stored in the memory, and the extracted character is inserted. In order to read the video signal of the subtitle super portion of the even field and the odd field in all the even and odd fields at a preset timing according to the 1H line alternately and insert it into the original video signal, the inserted character is used. Is doubled in the vertical direction, and the same information is given to each pixel of the dot matrix video display device that displays the characters of superimposed subtitles in the even field and the odd field. Therefore, the information of the even field and the odd field is averaged at each pixel to prevent the outline from being blurred or the character from being difficult to see due to flicker. It can be reflected.

[0012]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 denotes an A / D converter for converting an analog input Y signal to a subtitle super signal processing circuit into a digital signal. Reference numeral 2 denotes a field discrimination circuit that discriminates whether the input Y signal is a signal of an even field or a signal of an odd field, and outputs Hi for an even field and outputs a Lo for an odd field. Reference numeral 3 denotes a memory for storing data of a subtitle superimposed portion of an even field and an odd field of the Y signal digitized by the A / D converter 1. Reference numeral 4 denotes a write timing control circuit for generating a write pulse for storing the data of the subtitle portion of the digitized Y signal in the memory 3. Reference numeral 5 denotes a read timing control circuit for generating a read pulse for reading the digitized data of the superimposed subtitle portion stored in the memory 3. Numeral 6 designates an address for separately storing even-numbered fields and odd-numbered fields when data of a subtitle super-portion is written to the memory 3, and for reading data, the data of the even-numbered fields and the data of the odd-numbered fields are set to 1H. An address control circuit for setting an address so as to alternately read out each line. Reference numeral 7 denotes a memory control circuit including a write timing control circuit 4, a read timing control circuit 5, and an address control circuit 6. Reference numeral 8 denotes a D for converting the data of the superimposed subtitle portion output from the memory 3 into an analog signal.
/ A converter. Reference numeral 9 denotes a primary color signal / subtitle super combining circuit for inserting a subtitle super signal converted into an analog signal by the D / A converter 8 into each of analog R / G / B primary color signals. Reference numeral 10 denotes a dot matrix video display device for displaying, as an image, each of the R / G / B primary color signals obtained by combining the superimposed subtitles in the primary color signal / subtitle superimposing circuit 9.

The operation of the subtitle super signal processing circuit configured as described above will be described with reference to FIG.
First, the analog Y signal input to the subtitle super signal processing circuit FIG. 2A is converted into a digital signal by the A / D converter 1. The field discrimination circuit 2 discriminates whether the input analog Y signal is an even field or an odd field, and determines the result as a field discrimination signal.
Output as (c).

The Y signal converted into a digital signal by the A / D converter 1 is sent to the memory 3. At this time, the write timing control circuit 4 generates a write timing pulse diagram (d) corresponding to the position of the subtitle superimposition from the V pulse and the H pulse in order to store the digital signal of the subtitle superimposition in the memory 3. The write timing pulse is sent to the memory 3 and the address control circuit 6, and the memory 3 is set to the write mode and the address control circuit 6 is operated at the same time. At this time, the address control circuit 6 determines whether the data stored in the memory 3 is the data of the even field or the data of the odd field by the field determination signal, and sets the address so that the respective data do not overlap.
It is stored in the memory 3. It is necessary to read the subtitle data stored in the memory 3 at a timing set in advance in accordance with a position to be inserted into the original video signal. Therefore, the read timing control circuit 5 generates a read timing pulse from FIG. 2 (e) from the V pulse and the H pulse, and supplies the read timing pulse to the memory 3 and the address control circuit 6, thereby setting the memory 3 to the read mode and simultaneously setting the address control circuit. 6 is operated. At this time, the address control circuit 6 uses the H pulse as a reference so that the data of the subtitle super portion of the even field and the data of the subtitle super portion of the odd field stored in the memory 3 are alternately read every 1H line. Is set, and data is read from the memory 3. The read data of the superimposed subtitle portion is converted again into an analog signal by the D / A converter 8, and the primary color signal / superimposed subtitle combining circuit 9
Are combined with an analog R / G / B primary color signal and sent to the dot matrix image display device 10 to be displayed as an image. That is, the subtitle super characters extracted in the 2n field and the 2n + 1 field are synthesized as a character of one frame and inserted into the video of the 2n + 2 field. In the video of the 2n + 3 fields, superimposed subtitles extracted from the 2n + 1 field and the 2n + 2 field are combined as one-frame characters and inserted. Since the character signals of the two fields are alternately inserted into one field for each 1H line, the characters inserted in the video are enlarged twice in the vertical direction. Further, when the character is stationary, among the pixels of the dot matrix video display device 10, in the pixel displaying the inserted character, each pixel has the same value in the even-numbered field and the odd-numbered field. Information will be given. Therefore, the information of the even field and the odd field is averaged at each pixel, so that the outline is not blurred, and the character is not easily seen due to flicker. For this reason, the character is enlarged, and a character with a clear outline can be displayed.

The display result of the superimposed character on the dot matrix video display device when the subtitle super signal processing circuit according to the present embodiment is used, and the superimposition when the conventional subtitle super signal processing circuit is used FIG. 3 shows a comparison result of the displayed characters on the dot matrix image display device.

[0017]

As is apparent from FIG. 3, the superimposed character when the subtitle super signal processing circuit according to the present embodiment is used has no gray pixels at the boundary between white and black, and is sharp. An excellent effect is obtained in that a sharp contour is obtained. Characters are enlarged twice in the vertical direction.

Although the input of the A / D converter 1 is a Y signal in the embodiment, it may be a primary color signal. Further, although the signal of the superimposed subtitle portion is inserted into the primary color signal by the primary color signal / subtitle super combining circuit 9, it goes without saying that it may be inserted into the Y signal.

As described above, according to the present embodiment, the A / D converter 1 converts an analog video signal into a digital signal, and converts the data of the subtitle superimposed part of the even and odd fields from the digitized video signal. A memory 3 for storing the data of the caption super portion of the even field and the odd field in the memory 3 and the data of the even and odd fields stored in the memory 3 in all the even and odd fields , A D / A converter 8 for converting a digital signal read from the memory 3 into an analog signal, and a processed subtitle subtitle character signal as an original video signal. And the superimposition of the primary color signal / subtitle super-synthesizing circuit 9 to be inserted into the It is possible to reflect the easy character.

[0020]

As is clear from the above embodiments, according to the present invention, an A / D converter for converting an analog video signal into a digital signal, and subtitles of even and odd fields from the digitized video signal are provided. A memory for storing the data of the super portion, and the subtitles of the even and odd fields The data of the super portion are stored in the memory, and the even and odd fields stored in the memory in all the even and odd fields 1H
A memory control circuit for alternately reading out lines, a D / A converter for converting a digital signal read from the memory into an analog signal, and a primary color signal for inserting the processed subtitle character signal into the original video signal / Subtitle super combining circuit, for example, NTSC
If the method is used, the video information of the even field and the odd field must be displayed on the same pixel. Even when displaying a video on a dot matrix video display device having a vertical pixel number of 260 pixels or less, the image is enlarged. And
In addition, it is possible to provide a subtitle super signal processing circuit capable of projecting a legible character with a clear character outline. Similarly, the same effect can be obtained in a PAL or SECAM video signal, for example, in a dot matrix video display device having 312 pixels or less in the vertical direction.

[Brief description of the drawings]

FIG. 1 is a block diagram of a subtitle super signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart of a subtitle super signal processing circuit according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing a display result of a subtitle super signal processing circuit in one embodiment of the present invention.

FIG. 4 is a block diagram of a conventional subtitle super signal processing circuit.

FIG. 5 is a timing chart of a conventional subtitle super signal processing circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 A / D converter 2 Field discriminating circuit 3 Memory 4 Write timing control circuit 5 Read timing control circuit 6 Address control circuit 7 Memory control circuit 8 D / A converter 9 Primary color signal / subtitle super combining circuit 10 Dot matrix video display device 21 A / D converter 22 Field discrimination circuit 23 Even field memory 24 Odd field memory 25 Write timing control circuit 26 AND gate 27 Read timing control circuit 28 AND gate 29 Address control circuit 30 Inverter 31 AND gate 32 AND gate 33 Address control circuit 34 Buffer 35 Buffer 36 D / A converter 37 Primary color signal / subtitle super combining circuit 38 Dot matrix video display

Continuation of the front page (56) References JP-A-63-169884 (JP, A) JP-A-2-244986 (JP, A) JP-A 64-15791 (JP, A) JP-A-59-214891 (JP JP-A-3-48584 (JP, A) JP-A-2-179080 (JP, A) JP-A-60-199281 (JP, A) JP-A-2-305190 (JP, A) 63-117175 (JP, U) (58) Field surveyed (Int. Cl. ⁶ , DB name) H04N 5/262-5/28 H04N 5/445

Claims (1)

(57) [Claims] 1. An analog video signal is converted into a digital signal.
A / D converter for conversion and digitized video signal
Subtitles of even and odd fields from issue
Memory for storing partial data and even field
Note the data of the subtitles of the
In all fields, even and odd
Data of even and odd fields stored in memory
Memory control circuit for alternately reading out 1H lines
And the digital signal read from the memory
A D / A converter for converting the signal into a
Subtitle sentence processed by signal output from barta
And a synthesizing circuit for inserting the character signal into the original video signal.
Image of even field and odd field as display device
Dot matrix video table that displays signals on the same pixel
In a television receiver using a display device,
Video data such as NTSC system with superimposed data
Before the number of pixels is smaller than the video signal of the NTSC system etc.
Display on the dot matrix video display device,
Even number field for the subtitle super data part
And odd fields are not displayed on the same pixel,
Subtitle super data of even field and odd file
Read the subtitle super data of the field from the memory
And sequentially display them on the dot matrix video display device.
A subtitle super signal processing circuit characterized in that: