JP2928026B2 - Storage information protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage information protection device and, more particularly, to an erasable programmable read only memory (EP) for preventing stored information from being read by a third party without permission.
ROM).

[0002]

2. Description of the Related Art At present, an ultraviolet erasing PROM (UVEP)
EPROMs such as ROMs and electrically erasable PROMs (EEPROMs) are used for program evaluation and initial mass production. Therefore, information that is generally not desired to be known to an external third party, such as program know-how, is written in the EPROM. However, the above EPROM has P
Since the contents can be easily read by a ROM writer or the like, it is necessary to incorporate a storage information protection device for protecting a third party from reading without permission.

[0003] A conventional EPROM storage information protection device includes:
As shown in FIG. 5, an EPROM 1 to be protected and an EPR
A prohibition flag 11 composed of an EPROM provided separately from the OM1 and a prohibition circuit 12 composed of a two-input AND gate and prohibiting output of the output data D of the EPROM 1 by a prohibition signal N from the prohibition flag 11 are provided. I was

Next, the operation of the conventional storage information protection device will be described.

When the output of the EPROM 1 is prohibited, "L" is first written in the prohibition flag 11 in advance, and the prohibition signal N, which is the output of the prohibition flag 11, is set to "L". Next, when the output data D of the EPROM 1 is input to the prohibition circuit 12, one input of the AND gate of the prohibition circuit 12 becomes "
L ", the output O to the external port TO is also""
L ", and reading of the output data D of the EPROM 1 to the outside is prohibited.

When permitting the output of the EPROM 1, first, the prohibition flag 11 is left at the initial value "H",
The inhibition signal N, which is the output of the inhibition flag 11, is set to "H". Next, the output data D of the EPROM 1 is
, One of the inputs of the AND gate of the inhibition circuit 12 is "H", so that the output O becomes the same as the output data D of the EPROM 1, and the reading of the output data D of the EPROM 1 to the outside is permitted. Met.

[0007]

In the conventional storage information protection device described above, the reading of information stored in the EPROM is prohibited by a prohibition circuit controlled by a prohibition signal from a prohibition flag. When a third party attempts to read the information, it is clear whether the information is prohibited or permitted, and therefore, there is a disadvantage that the EPROM is easily found to be in the read prohibited state. Further, when the EPROM is in the reading prohibited state, a fixed value is output to the external port.
There is a disadvantage that it is difficult to confuse the third party. Further, since the prohibition flag is composed of an EPROM provided separately from the EPROM, there is a disadvantage that the circuit configuration is complicated.

[0008]

SUMMARY OF THE INVENTION A storage information protection apparatus according to the present invention comprises an erasable programmable read-only memory storing first data as predetermined control information and second data as main storage information. A memory (EPROM), a decoder that decodes the first data read by a predetermined control signal and outputs a data selection signal, and a second logical operation based on a predetermined logical operation from the second data. A scramble circuit for generating scramble data having different values, and a data selection circuit for selecting one of the first data and the scramble data by the data selection signal are provided.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the storage information protection device of the present invention.

As shown in FIG. 1, the storage information protection apparatus of this embodiment fetches and decodes the EPROM 1 to be protected and the scramble code DS on the internal bus 6 in synchronization with the rise of the PROM mode setting signal P. Data selection signal Q
, A scramble circuit 3 that scrambles output data D on internal bus 6 and outputs scrambled data S, and selects one of output data D and scrambled data S by data selection signal Q. An output data selector 4 for outputting selection data DO, and an external PR for inputting selection data DO.
It comprises an output buffer 5 for outputting an output signal O to a port TO by an OM control signal, and an internal bus 6 for outputting output data D of the EPROM 1.

Next, the operation of this embodiment will be described.

FIG. 2 is a time chart showing an example of the operation of the storage information protection circuit of the present embodiment.

First, a case where the output data of the EPROM 1 is scrambled and output will be described. First, EP
When writing data to the ROM1, an EPRO
The scramble code DS is written in the scramble code address in M1. When the power is turned on and the PROM mode setting signal P is "L", a scramble code address is given to the EPROM 1 and the scramble code D
S is read. This scramble code address is
PR is forcibly set instead of external address, but PR
Since no external address is input until the OM mode setting signal P becomes "H", no collision occurs between the two addresses. The scramble code DS is taken into the scramble code decoder 2 in synchronization with the rise of the PROM mode setting signal P, decoded, and the data selection signal Q
Is output. Since the level of the PROM mode setting signal P rises from "L" to "H" when the power is turned on, the scrambling code DS is captured only once. When the data selection signal Q of the decoding result of the scramble code DS becomes “H”, the output data selector 4 selects the scramble data S output from the scramble circuit 3. Next, the PROM mode setting signal P
Becomes "H", an external address is applied to the EPROM 1, and the read output data D based on this external address is output.
Is output to the internal bus 6. Output data D on internal bus 6
Is input to the output data selector 4 after being taken into the scramble circuit 3 and subjected to the scramble processing. The output data selector 4 inputs the selected scramble data S to the output buffer 5 as output data DO. When the external PROM control signal C is "
When L ″, the output buffer 5 outputs the output signal O to the port TO.
Is output. By the above operation, the output data of the EPROM 1 is scrambled and output to the outside.

As shown in FIG. 3, the scramble circuit 3 is a circuit for outputting the result of a logical operation between two arbitrary bits of the output data D. As an example, as shown in FIG. There is a two-input exclusive-OR (EXOR) circuit composed of a NOR circuit and a 2AND2NOR circuit.
This circuit is used when two input data match.
L, and outputs “H” if they do not match, and the two-input NAND circuit and 2OR2N shown in FIG.
A two-input EXOR circuit configured with an AND circuit may be used.
This circuit is used when two input data match.
H "is output, and" L "is output if they do not match.

Next, a case where the output data of the EPROM 1 is output as it is will be described. First, EPROM1
When writing data to the scramble code DS in the EPROM 1, the scramble code DS is not written into the scramble code DS but is left at the initial value. When the power is turned on and the PROM mode setting signal P is "L", the EP
The scrambling code address is given to the ROM 1 and the above initial value is read. This initial value is taken into scramble code decoder 2 in synchronization with the rise of PROM mode setting signal P, decoded, and outputs data selection signal Q. When the data selection signal Q becomes "L", the output data selector 4 selects the output data D on the internal bus 6. Next, when the PROM mode setting signal P becomes "H", an address is externally applied to the EPROM 1 and the read output data D based on the external address is output to the internal bus 6. The output data D on the internal bus 6 is input to the output data selector 4. The output data selector 4 inputs the already selected output data D to the output buffer 5 as output data DO. When the external PROM control signal C is "
When L ″, the output buffer 5 outputs the output signal O to the port TO.
Is output. With the above operation, the output data of the EPROM 1 is output to the outside as it is.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

The second embodiment differs from the first embodiment in that a scramble code register 7 for temporarily holding the scramble code DS read from the EPROM 1 is added, and the output data is replaced with the scramble circuit 3. A scramble circuit 8 that inputs both D and the scramble code DS is provided.

The operation of this embodiment is the same as that of the first embodiment until the scramble code DS is output to the internal bus 6. Next, the scramble code DS on the internal bus 6 is stored in the scramble code register 7 and then output to the scramble circuit 8 and the scramble code decoder 2. The scramble code decoder 2 decodes the scramble code DS and outputs a data selection signal Q to the output data selector 4, as in the first embodiment. On the other hand, the scramble circuit 8 performs a scramble process using both the output data D and the scramble code DS, and inputs the scramble data S to the output data selector 4. This can further complicate the scrambling process and make it more and more confusing to third parties who attempt to read the program. Subsequent operations are the same as those of the first embodiment, and the description will be omitted.

[0021]

As described above, the storage information protection apparatus of the present invention stores a scramble code in an EPROM, decodes the scramble code and outputs a data selection signal, and on the other hand, reads out main storage information read data. A scramble circuit which generates scramble data from the EPROM. The output of the EPROM is permitted or prohibited by selecting either the read data or the scramble data by the data selection signal. A prohibition flag composed of an EPROM provided separately from the above is unnecessary, and there is an effect that the circuit configuration is simplified.

Further, the output of the EPROM is scrambled and output, thereby prohibiting the reading of the stored information to the outside. Therefore, it is not easy to determine that the EPROM is in the read-inhibited state. This has the effect of confusing a third party attempting to read.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a storage information protection device according to the present invention.

FIG. 2 is a time chart illustrating an example of an operation of the storage information protection device according to the embodiment.

FIG. 3 is a circuit diagram showing an example of a scramble circuit in the storage information protection device of the present embodiment.

FIG. 4 is a block diagram showing a second embodiment of the storage information protection device of the present invention.

FIG. 5 is a block diagram showing an example of a conventional stored information protection device.

[Explanation of symbols]

 Reference Signs List 1 EPROM 2 scramble code decoder 3, 8 scramble circuit 4 output data selector 5 output buffer 6 internal bus 7 scramble code register 11 prohibition flag 12 prohibition circuit

Claims (2)

(57) [Claims] 1. An erasable programmable read-only memory (EPROM) storing first data as predetermined control information and second data as main storage information, and read-out by a predetermined control signal. A decoder that decodes the first data and outputs a data selection signal, and a scramble circuit that generates scramble data having a value different from the second data by a predetermined logical operation from the second data, A storage information protection device, comprising: a data selection circuit that selects one of the first data and the scramble data according to the data selection signal. 2. A data holding circuit for holding said first data, and a value different from said first and second data by a predetermined logical operation from said second data and an output of said data holding circuit. 2. The storage information protection device according to claim 1, further comprising a second scramble circuit that outputs certain second scramble data.