JP2921930B2 - Field effect transistor, method of manufacturing the same, and semiconductor integrated circuit using the same - Google Patents

Description

The present invention relates to a field-effect transistor, a semiconductor integrated circuit using the same, and a method for manufacturing the same, and more particularly, to a gallium arsenide layer as an operation layer. The present invention relates to a field effect transistor using a III-V compound semiconductor such as GaAs) or silicon (Si).

(Prior art) A Schottky junction gate field effect transistor (MESFET) using a semi-insulating GaAs substrate cannot be obtained with an integrated circuit using a silicon substrate due to the high electron mobility of GaAs. GaAs ICs and LSIs that enable ultra-high-speed operation
Are attracting attention as basic elements.

To improve the performance of such a GaAs field effect transistor, the following four items are required.

By shortening the gate length, the gate capacitance Cg is reduced, and at the same time, the current driving force Gm is improved.

A feedback capacitance Cgd between a gate as an input and a drain as an output is reduced.

Reduce the series resistance Rs between the gate and the source.

Ensure withstand voltage between gate and drain.

Now, as a basic element for a current GaAs IC / LSI, a self-aligned structure as shown in FIG. 8 (a) is very generally used from the viewpoint of simplification of a manufacturing process and improvement of performance. .

That is, as shown in FIG.
An n-type operation layer 2 is formed in an As substrate 1, a gate electrode 3 made of a refractory metal is formed on the n-type operation layer 2, and a high-concentration source
n ⁺ layers 5a and 5b are formed.

In such a structure, since the n ⁺ layers 5a and 5b are formed close to (or in contact with) the gate, Rs is reduced and the current driving capability is increased.

However, conversely, between the gate and the drain, similarly, since the gate and the high-concentration n ⁺ are close to each other, there is a problem that the capacitance Cgd between the gate and the drain is increased and the reverse breakdown voltage of the gate is decreased. Further, when the gate length is shortened in this structure, the interval between the high concentration and deep n ⁺ layers is also reduced at the same time, so that the n ⁺ layers 5a and 5a
A leak current flows between b and a so-called short channel effect occurs.

In order to solve such a problem, a so-called LDD (Lightly Doped Drain) structure as shown in FIG. 8B has been proposed.

This is a self-aligning manner with the gate electrode 3, n-type layer 4a of intermediate concentration, previously formed to 4b, after further forming the sidewall 6 to the gate electrode 3, deep high concentration as a mask n ⁺
The layers 5a and 5b are formed.

In this structure, the short channel effect is suppressed by increasing the distance between the deep high concentration n ⁺ layers 5a and 5b by the side wall width from the gate length, and at the same time, the n-type layers 4a and The presence of 4b can also suppress an increase in source resistance Rs.

However, also in this structure, the n-type layers 4a, 4
Since the concentration of b is as large as 2 to 10 times that of the active layer 2, the gate
The capacitance between the drains increases. Further, if the concentration of the intermediate concentration layers 4a and 4b is increased to further reduce Rs, the capacitance between the gate and the drain increases, and at the same time, the breakdown voltage between the gate and the drain also decreases. In such a case, there is a problem that the degree of freedom in device design is small.

In addition, from the viewpoint of reducing the gate-to-drain capacitance while improving the gate-to-drain withstand voltage while reducing the gate-to-source resistance, the asymmetric recess structure shown in FIG. Is used in a single FET. In this method, an n-type layer is formed thick in advance, a portion serving as an operation layer is etched to form a step, and a gate electrode is formed from the source side. However, the process of adjusting the threshold voltage Vth of the FET by etching the operation layer is poor in uniformity and reproducibility. In particular, tens of thousands or more transistors are formed on one chip like a large-scale LSI. It cannot be used when the Vth uniformity is strictly required.

Thus, an example in which such an asymmetric structure is realized by a self-aligned type has recently been reported (M. Muraguchi et al.
1986 SSDM c-7-1 pp379-382 Solid-State Device
and Materials).

However, in this method, the direction of the source / drain on the wafer is determined because the shadowing effect based on the implantation angle at the time of ion implantation is used. This greatly impairs the degree of freedom of design, and at the same time increases the number of FEs.
In LSIs integrating T, there is a problem that the chip size becomes extremely large, leading to a reduction in yield and a reduction in productivity.

(Problems to be Solved by the Invention) As described above, in the conventional GaAs FET, the factors that determine the performance, that is, the reduction of the gate capacitance Cg due to the shortening of the gate length and the current driving force
Gm improvement.

Reduction of gate-drain feedback capacitance Cgd.

Reduction of gate-source series resistance Rs.

Improved withstand voltage between gate and drain.

It has been extremely difficult to realize an FET structure that satisfies the above four items and has simplicity, uniformity, and reproducibility applicable to large-scale integrated circuits.

Among these, regarding reduction of the gate-drain feedback capacitance Cgd, especially for SLCF (Schottky diode level shiftor)
capasitorc couppled FET logic) circuit and DCFL (Direct
In an integrated circuit in which a first field-effect transistor and a second field-effect transistor are directly connected to each other, such as a couppled FET logic circuit, and the first transistor is used as a switching element of an inverter, it is important to determine an operation speed. It is a factor.

The present invention has been made in view of the above circumstances, and
The objective is to meet the requirements and provide a high-performance MESFET.

[Configuration of the invention]

(Means for Solving the Problems) In the first aspect of the present invention, an n-type layer having an intermediate impurity concentration is formed in the source side region in a self-aligned manner with the gate electrode, and furthermore, from the end of the gate electrode. An n ⁺ layer having a high impurity concentration is formed deeply at predetermined intervals, and a conductive layer having the same impurity concentration and depth as the operating layer is provided between the operating layer and the drain n ⁺ layer immediately below the gate electrode. Connected by layers.

That is, a source / drain region of a high impurity concentration semiconductor is formed at a predetermined interval from the gate electrode, and an impurity concentration between the operation layer and the source region is higher than that of the operation layer and lower than the source region. A concentration layer is formed, while the drain region is formed directly connected to the active layer.

In a second aspect of the present invention, a first field effect transistor and a second power effect transistor, such as an SLCF circuit and a DCFL circuit, are directly connected to each other by using the first transistor of the first aspect of the present invention. These transistors are used as switching elements to form an integrated circuit.

At the time of manufacturing, when ion implantation of the intermediate concentration layer is performed during the process of the conventional LDD structure FET, holes are formed from at least the source region to the operation layer of the region corresponding to the source / drain regions on both sides of the gate electrode. After the formed mask material is formed, ion implantation is performed.

After the mask is formed, the side wall only on the source side of the gate electrode is removed, and after removing the mask material, ion implantation of the intermediate concentration layer is performed.

(Function) In a conventional FET having an LDD structure, the concentration and depth of the intermediate concentration layer formed in the gate in a self-aligned manner conflict with the parasitic resistance between the gate and the source and the reverse breakdown voltage between the gate and the drain. Needed optimization between parameters,
Since the intermediate concentration layer is formed only on the source side, there is no need to consider the drain breakdown voltage when designing the concentration depth, etc., and the degree of freedom in the design is increased, and as a result, the gate-source resistance Rs is reduced. can do.

Further, compared with the conventional LDD structure, since there is no intermediate concentration layer on the drain side, the gate length can be reduced, the gate capacitance Cg can be reduced, and at the same time, the current driving force Gm can be improved.

In addition, this transistor directly connects a first field-effect transistor and a second field-effect transistor, such as an SLCF circuit or a DCFL circuit, in which capacitance between a gate and a drain is a particularly important factor, Is effective in forming an integrated circuit by using the as a switching element of an inverter. That is, the capacitance between the gate and drain is
In the case of the switching FET of the FL circuit, it works as a feedback capacitance between the input and the output. Therefore, reducing this has about twice the contribution to high-speed operability as compared with that between the gate and the source, and the effect is extremely large.

Also, in the manufacturing process, when ion-implanting the intermediate concentration layer during the conventional LDD structure FET process, a step of forming a mask material having a pattern edge on the gate electrode and protecting the drain side from ion implantation is performed. It is only necessary to add, and it can be formed very easily with good controllability.

This also makes it possible to realize an FET having a gate length of about 0.2 μm.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Embodiment 1 FIG. 1 is a cross-sectional structural view of a GaAs MESFET of an embodiment of the present invention.

In this GaAs MESFET, an n-type layer 4 having a depth of 0.2 μm and a concentration of 7 × 10 ¹⁷ cm ^-3 having an intermediate concentration is formed in a source-side region of the gate electrode 3 in a self-aligned manner, and further, a gate electrode end is formed. A high concentration and deep (depth 0.3 μm, concentration 2 × 10 ¹⁸ cm ⁻³ ) n ⁺ layer 5a is formed at a position apart from the portion by a distance d1, while the drain side is d1 from the gate electrode end. distance approximately equal d2 (D1 to d2) n ⁺ -type drain region 5b of the same depth and concentration as n ⁺ source region away only is formed, the active layer 2 Toko immediately below the gate electrode n ⁺ -type drain The n ⁻ -type operation layer is extended and electrically connected between the regions 5b.

Because the FET is a source drain region 5a is a deep n ⁺ layer at a high concentration, between 5b are formed apart added d1 + d2 in the gate length l _g, source drain regions through the semi-insulating substrate
The leakage current flowing between 5a and 5b is reduced. Therefore it is possible to shorten the gate length, a gate capacitance Cg is reduced, thereby improving the current drivability g _m.

Further, since the intermediate density layer 4 is present between the gate electrode 3 and the source region 5a, the source resistance Rs is reduced, thereby improving the current drivability g _m.

Paying attention to the drain end of the gate electrode, the source end is in contact with the intermediate-concentration layer 4 having a higher concentration than the operating layer 2, whereas the drain end does not have the intermediate-concentration layer 4 and has a relatively low concentration. It is only in contact with the operation layer 2. For this reason,
As compared with the case where the intermediate concentration layer 4 exists, the impurity concentration at the drain end of the gate electrode is significantly reduced, and as a result, the junction capacitance between the gate and the drain is greatly reduced. In the case of the switching FET of this DCFL circuit, this gate-drain capacitance acts as a feedback capacitance between the input and the output, so reducing it is about twice as fast as that between the gate and the source for high-speed operation. There is a contribution and the effect is great.

Further, as a result of the drastic reduction of the impurity concentration at the drain end of the gate electrode, there is an effect that the Schottky reverse characteristics between the gate and the drain, particularly the breakdown voltage, are greatly improved.

Further, in the conventional LDD structure, the depth and concentration of the intermediate concentration layer had to be determined in consideration of both the source-side series resistance Rs and the drain-side gate reverse pressure, so that the degree of freedom was small. On the other hand, the structure of the present invention does not need to consider the gate breakdown voltage on the drain side, and has an advantage that the degree of freedom in design is large. That is, in this example, the intermediate concentration layer 4 can be set deeply and at a high concentration within a range where the short channel effect is not increased, and as a result, the source resistance can be reduced.

 Next, a manufacturing process of the GaAs FET will be described.

First, as shown in FIG. 2 (a), an n ⁻ -type layer 2 serving as an FET operation layer is formed on the surface of a semi-insulating GaAs substrate 1 by a selective ion implantation method, and then tungsten nitride (W) is used.
A gate metal made of N) is deposited so as to have a film thickness of 5000 °, and the gate electrode 3 is formed by etching. At this time, the ion implantation conditions for the n ⁻ -type layer are, for example, a normally-off type F having a threshold voltage (Vth) of about 0 to +0.1 V.
To obtain ET, Si ⁺ ions are set at an acceleration voltage of 50 keV and a dose of about 1.3 × 10 ¹² / cm ² .

For example, when it is desired to obtain an FET having a Vth of about −0.6 V, the dose is set to about 2.5 × 10 ¹² / cm ² . In addition,
Here, the gate length was 0.8 μm.

Subsequently, as shown in FIG. 2B, a resist pattern 8 having an opening only in a portion corresponding to the source region is formed, and the resist pattern 8 is used as a mask under conditions of, for example, 50 KeV and 1 × 10 ¹³ cm ^{−2. The} intermediate concentration layer 4 is formed by ion implantation of ⁺ ions. Here, ion implantation is performed by masking the region serving as the drain of the FET with a photoresist. It is sufficient that the edge of the resist pattern 8 is formed above the gate electrode 3 and care must be taken of process variations. Can be applied without. In addition, the positioning accuracy of the currently used reduction projection exposure apparatus is ± 0.
Since it is about 2 μm, it can be formed with high accuracy up to a gate length of about 0.4 to 0.5 μm.

Next, as shown in FIG. 2 (c), the resist pattern 8 is removed, and a silicon oxide film having a thickness of about 0.4 μm is deposited by a method having excellent step coverage such as a plasma CVD method. The silicon oxide film 7 is left only on the side wall of the gate electrode by performing etching by an amount equivalent to the film thickness in the vertical direction by anisotropic etching such as (RIE). At this time, the width of the silicon oxide film 7 remaining on the side wall is determined by the deposited film thickness, but is about 0.3 μm here.

Subsequently, as shown in FIG. 2 (d), a resist pattern 9 is formed, and using this as a mask, for example, 120 KeV, 3 × 10
^The source region 5a and the drain region 5b are formed by implanting Si ⁺ ions under the condition of ¹³ cm ⁻² .

Then, after removing the resist pattern 9 as shown in FIG. 2 (e), annealing for activating the ion implantation layer is performed (800-900 ° C.), and finally, the source electrode 6a and the drain electrode 6 made of AuGe alloy. 6b to form an embodiment of the present invention.
FET is completed.

According to this method, the source region having the intermediate concentration layer 4 and the drain region having no intermediate concentration layer 4 can be determined only by the mask pattern when forming the intermediate concentration layer. There is no inconvenience that the direction of the source / drain that occurs when it is determined is uniquely determined.

Therefore, the present invention can be easily applied even when, for example, the direction of the source and the drain or the angle of the gate exists at random, and does not limit the degree of freedom of design or increase the chip size. It becomes easy.

Further, it is possible only by adding a single step of forming a photoresist pattern to a step for realizing a conventional LDD structure, and it is possible to avoid an increase in manufacturing cost.

In addition, this method uses a conventional self-aligned FET.
Or, like the LDD type FET, it can be formed only by ion implantation and annealing, for example, and does not require a step of etching the operation layer, so that uniformity and reproducibility of FET characteristics can be easily obtained, and high integration Conversion is easy.

Embodiment 2 Next, another method of manufacturing a GaAs MESFET will be described as a second embodiment of the present invention.

After forming an n ⁻ -type layer 2 serving as an FET operation layer on the surface of a semi-insulating GaAs substrate 1 by a selective ion implantation method, a gate metal made of tungsten nitride (WN) is formed to a thickness of 5000Å.
The steps up to the step of forming the gate electrode 3 by depositing and etching to be as follows are the same as the steps shown in FIG. 2A in the first embodiment (FIG. 3A).

Subsequently, as shown in FIG. 3 (b), the silicon oxide film 7 is formed by a method excellent in step coverage such as a plasma CVD method.
After depositing about 0.6 μm, a resist pattern 8 having an opening whose outer edge corresponds to the outer end of the source / drain region is formed.

Thereafter, as shown in FIG. 3 (c), the film is etched by a thickness corresponding to the film thickness in the vertical direction by anisotropic etching such as reactive ion etching (RIE), thereby forming the resist pattern 8 and the side wall of the gate electrode. Only, the silicon oxide film 9 is removed from the portion corresponding to the source / drain region, and using this as a mask, Si ⁺ ions are ion-implanted under the conditions of, for example, 100 KeV and 5 × 10 ¹³ cm ^−2. As a result, a high concentration source region 5a and drain region 5b are formed.

Then, as shown in FIG. 3D, the resist pattern 8 is removed, a resist pattern 9 having an opening only on the source side is formed, and the side wall insulating film 7 on the source side is removed by etching using this as a mask. For example, 50 KeV, 1 × 1
The intermediate concentration layer 4 is formed by implanting Si ⁺ ions under the condition of ¹³ cm ⁻² . Here, the ion implantation is performed by masking the drain region of the FET with a photoresist. The edge of the resist pattern 9 may be applied to the gate electrode 3, and the resist pattern formed on the source side may be the source region. Silicon oxide film 7 outside
Is desirably formed so as to cover. On the other hand, if the silicon oxide film 7 outside the source region is exposed, the silicon oxide film in this portion is also etched when the sidewall insulating film is etched, and the source region is expanded when the ion implantation of the intermediate concentration layer is performed. This is because there is a possibility that the isolation characteristics from the adjacent element may be adversely affected.

Then, as shown in FIG. 3E, after removing the resist pattern 9, annealing for activating the ion implantation layer is performed (800 to 900 ° C.), and finally, the source electrode 6a and the drain electrode made of AuGe alloy. 6b to form an embodiment of the present invention.
FET is completed.

In this example, a similar transistor can be formed even when the edge of the pattern covering the drain side is not necessarily formed on the gate electrode 3 during ion implantation for forming the intermediate concentration layer 4.

That is, when the resist pattern 9 having an opening only on the source side shown in FIG. 3D is formed, as shown in FIG. 4A, the edge of the resist pattern 9 covering the drain side becomes the gate electrode. Let's consider a case where it is formed on the side wall insulating film 7 on the source side instead of the above.

In this case, as shown in FIG. 4 (b), after using the resist pattern 9 as a mask, the side wall insulating film 7 on the source side is removed by isotropic etching, and subsequently, the resist pattern 9 is removed. As shown in FIG. 4C, the silicon oxide film 7 and the gate electrode 3 are used as masks to implant the Si ⁺ ions under the conditions of, for example, 50 KeV and 1 × 10 ¹³ cm ⁻² , thereby forming the intermediate concentration layer 4. Thus, an FET similar to that of the second embodiment can be obtained.

At this time, in a region other than the FET, the silicon oxide film 7 serves as a mask at the time of ion implantation. However, since the ion implantation depth of the intermediate concentration layer 4 is about 0.1 to 0.3 μm, the thickness of the silicon oxide film 7 is 0.4 μm. When the thickness is about 0.5 μm, the implanted ions can be sufficiently prevented.

When the FET is manufactured in such a process, the pattern edge of the resist pattern 9 covering the drain side may be located anywhere on the source-side sidewall insulating film 7 and the gate electrode 3. Therefore, for example, when the side wall width is 0.3 μm and the overlay accuracy of the exposure apparatus used for pattern formation is 0.25 μm, the region where the resist pattern edge is allowed is 0.5 μm, and the extremely fine area of about 0.2 μm It is also applicable to FETs having various gate lengths.

 For comparison, a conventional LDD structure FET was created.

At this time, the ion implantation condition of the intermediate concentration layer 4 was 50 KeV and 5 × 10 ¹² cm ^{−2 in} the LDD structure, and Si ⁺ ions were implanted. As described above, the concentration is about half that of the present invention. This is because in the LDD structure, the concentration of the intermediate concentration layer cannot be increased so much due to the problem of the gate-drain breakdown voltage, but the present invention has no limitation. Therefore, the gate-source resistance Rs
This is because the condition can be set so as to sufficiently reduce.

As a result, the resistance Rs between the gate and the source was 0.35 Ωmm in the conventional LDD structure, whereas the resistance Rs in the present invention was 0.35 Ωmm.
25 [Omega] · mm and has become approximately 30% lower, as a result, g _m in the pentode region whereas those of LDD structure was 300 ms / mm, was improved to 350 ms / mm. Further, in the FET of the present invention, the resistance between the gate and the drain is slightly increased, so there is a concern that the characteristics may deteriorate in the triode region. However, the on-resistance (resistance between the source and the drain) at Vd = 0.02V and Vg = 0V is reduced. Measurement results, gate width
In the FET of W _g = 20 μm, the FET of the LDD structure, the FET of the present invention
Both were 250Ω, almost the same (Vth = −0.6V
FET). This is because, in the FET of the present invention, the concentration of the intermediate concentration layer on the source side is increased by the amount corresponding to the increase in the resistance on the drain side.
This is because they were offset by the reduced resistance.

Further, regarding the reverse breakdown voltage between the gate and the drain, LD
In the present invention, while the voltage of the D structure was about 6 V, 8.5
V is greatly improved, and the applicable drain voltage is greatly improved. This is because the concentration of the portion where the drain end of the gate is in contact with the LDD is formed by both the intermediate concentration layer and the active layer in the LDD, but is reduced to about 1 / 2.5 in the present invention only in the active layer. It is.

Embodiment 3 Next, as a third embodiment of the present invention, an example in which a GaAs MESFET of the present invention is used as a switching FET of a DCFL circuit as shown in an equivalent circuit diagram in FIG. 5 will be described.

In other words, this example constitutes an inverter, and uses a conventional LDD structure FET as a depletion type FET Tr1 serving as a constant current source of a load, and uses the FET of the present invention as an enhancement type FET Tr2 for switching. Things.

The structure of the FET Tr2 was exactly the same as that shown in FIG.

As described at the end of the second embodiment, the on-resistance of this FET is almost the same as that of the conventional LDD structure FET, so that the noise margin of the inverter is almost equal to that of the conventional LDD structure transistor. It was 190 mV.

However, regarding the operating speed, under the condition of power consumption per inverter of 1.0 mW / gate (Vdd = 2.0 V), L
The DD type FET is 26 ps / gate, whereas the inverter of FIG. 5 using the FET of the present invention as a switching FET is 19 ps / gate.
The gate has improved by about 27%.

This is because the gate-drain capacitance acting as the feedback capacitance of the inverter was reduced as a result of the reduced impurity concentration at the drain end of the gate electrode.

Embodiment 4 In the above embodiment, an operation layer is formed on a substrate surface,
An example in which the source / drain layer is formed in the substrate by ion implantation has been described. However, the present invention is not limited to this structure. As shown in FIGS. 6 (a) to 6 (e), the manufacturing process is shown in FIG. The intermediate concentration layer may be formed only in the operation layer on the source side, and the source / drain region may be constituted by a high concentration region selectively grown on the substrate surface by the epitaxial growth method.

 This example will be described as a fourth embodiment of the present invention.

Also in this case, as shown in FIG.
After forming an n ⁻ -type layer 2 serving as an FET operation layer on the surface of a GaAs substrate 1 by selective ion implantation, a gate metal made of tungsten nitride (WN) is deposited to a thickness of 5000 ° and etched. The gate electrode 3 is formed by processing, and then, as shown in FIG.
Silicon oxide film 7 with excellent step coverage such as CVD
Is deposited to a thickness of about 0.6 μm, and then a resist pattern 8 having an opening whose outer edge corresponds to the outer end of the source / drain region is formed. The steps up to this step are exactly the same as in the second embodiment.

Thereafter, as shown in FIG. 6 (c), by etching in the vertical direction by anisotropic etching such as reactive ion etching (RIE) by an amount corresponding to the film thickness, the resist pattern 8 and the side wall of the gate electrode are etched. The silicon oxide film 7 is left only on the silicon oxide film 7 and a portion corresponding to the source / drain region is removed. Using this as a mask, a silicon layer is selectively grown by selective MOCVD. Then, with the mask still in place, 100 KeV, 5 × 10 ¹³ cm
By implanting Si ⁺ ions under the condition of ⁻² , the source region 5a and the drain region 5b with high concentration are formed.

Then, as shown in FIG. 6D, the resist pattern 8 is removed, a resist pattern 9 having an opening only on the source side is formed, and the side wall insulating film 7 on the source side is removed by etching using this as a mask. For example, 50 KeV, 1 × 1
The intermediate concentration layer 4 is formed by implanting Si ⁺ ions under the condition of ¹³ cm ⁻² . In this case as well, ion implantation is performed by masking the drain region of the FET with a photoresist. However, the edge of the resist pattern 9 may be applied to the gate electrode 3, and the resist pattern formed on the source side may be a source pattern. It is desirable to form so as to cover the silicon oxide film 7 outside the region.

Then, after removing the resist pattern 9 as shown in FIG. 6E, annealing for activating the ion-implanted layer is performed (800 to 900 ° C.) to form a silicon oxide film 10 as an interlayer insulating film. After forming the contact hole H,
Finally, a source electrode 6a and a drain electrode 6b made of AuGe alloy are formed to complete the FET according to the embodiment of the present invention. At this time, the cavity formed by removing the sidewall insulating film when forming the intermediate concentration layer is filled with the silicon oxide film 10.

As a modification, as shown in FIGS. 7A to 7D, a method of forming an intermediate concentration layer prior to selective CVD is also effective.

That is, similarly to the case shown in FIG. 6A, after forming the n ⁻ -type layer 2 serving as an operation layer, tungsten nitride (W
N) is formed on the gate metal 3 (FIG. 7A).

Thereafter, as shown in FIG. 7B, a resist pattern 9 having an opening only on the source side is formed, and using this as a mask, for example, Si ⁺ ions are ionized under the conditions of 50 KeV and 1 × 10 ¹³ cm ^−2. Implant and anneal for activation (800-9
00 ° C). An intermediate concentration layer 4 is formed.

Thereafter, the resist pattern 9 is removed, a silicon oxide film 7 is deposited to a thickness of about 0.6 μm, and a resist pattern 8 having an opening whose outer edge corresponds to the outer end of the source / drain region is formed. Etching by a thickness equivalent to the film thickness in the vertical direction by reactive ion etching,
The silicon oxide film 7 is left only under the resist pattern 8 and on the side wall of the gate electrode.

Then, as shown in FIG. 7 (c), using this silicon oxide film 7 as a mask, an impurity concentration of 3
By selectively growing an n ⁺ -type GaAs layer of about × 10 ¹⁸ cm ⁻³ , a source region 5a and a drain region 5b with high concentration are formed.

Finally, as shown in FIG.
The source electrode 6a and the drain electrode 6b made of an alloy are formed to complete the FET of the embodiment of the present invention.

Although the GaAs MESFET has been described in the above embodiment, the present invention is not limited to GaAs, but can be applied to other compound semiconductors, and further to FETs using silicon.

In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

〔effect〕

As described above, in the conventional LDD structure FET,
The concentration and depth of the intermediate concentration layer formed in a self-aligned manner on the gate required optimization between the contradictory parameters of the parasitic resistance between the gate and the source and the reverse breakdown voltage between the gate and the drain. On the other hand, according to the present invention, since the intermediate concentration layer is formed only on the source side, it is not necessary to consider the drain breakdown voltage when designing the concentration depth or the like, and the degree of freedom in the design is increased, and the gate capacitance Cg is increased. , And at the same time, the current driving force Gm can be improved, the operation can be speeded up, and the manufacture is extremely easy.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of a GaAs MESFET according to a first embodiment of the present invention, and FIGS. 2 (a) to 2 (e) show the same GaAs MESFET.
FIGS. 3 (a) to 3 (e) are views showing a manufacturing process of an ESFET, and FIGS. 4 (a) to 4 (c) are views showing a manufacturing process of a GaAs MESFET according to a second embodiment of the present invention. FIG. 5 is a diagram showing a modification of the second embodiment, FIG. 5 is an equivalent circuit diagram of the inverter according to the third embodiment of the present invention, and FIGS. 6 (a) to 6 (e) are diagrams of the inverter of the present invention. FIGS. 7 (a) to 7 (d) are views showing a modified example of the fourth embodiment, and FIGS. 8 (a) to 8 ( c) is a conventional GaAs M
FIG. 3 is a diagram showing an ESFET. 1 ... a semi-insulating GaAs substrate, 2 ... operating layer (n-layer), 3
... gate electrode, 4 ... intermediate concentration layer, 5a ... source region, 5b ... drain region, 6a ... source electrode, 6b ... drain region, 7 ... silicon oxide film, 8 ... resist pattern, 9 ... resist pattern, 10 ... silicon oxide film, Tr1 ... constant current FET, Tr2 ... switching transistor.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 H01L 27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (3)

(57) [Claims] A semiconductor operating layer formed on a substrate surface;
In a field effect transistor including a gate electrode formed on a surface of the operation layer and source and drain regions formed on both sides of the operation layer, an impurity concentration between the operation layer and the source region is An intermediate concentration layer higher than the operation layer and lower than the source region is formed, and the drain region is directly connected to the operation layer, and is formed at a predetermined distance from the gate electrode. Characteristic field effect transistor. 2. An integrated circuit in which a first field-effect transistor and a second field-effect transistor are connected in series, and the first transistor is used as a switching element. Using the formed semiconductor as an operation layer, a source region and a drain region are formed on both sides of the operation layer, and an impurity concentration between the operation layer and the source region is higher than that of the operation layer, and is higher than that of the source region. A semiconductor integrated circuit, wherein a low intermediate concentration layer is formed, and the drain region is directly connected to the operation layer and is formed at a predetermined distance from the gate electrode. 3. An operation layer forming step of forming a semiconductor operation layer on a substrate surface; a gate electrode formation step of forming a gate electrode on the operation layer; and forming source and drain regions on both sides of the gate electrode. Performing ion implantation from above the aperture mask over at least the source region to the operation layer in the region to be formed, forming an intermediate concentration layer only on the source side, and leaving an insulating film on a side wall of the gate electrode; Forming a source / drain region of a high impurity concentration semiconductor by performing ion implantation using the gate electrode and the sidewall insulating film as a mask.