JP2916533B2 - Digital multi-track recorder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital multi-track recorder capable of digitally recording, reproducing, and further editing a multi-track audio signal.

[Background] Conventionally, as a method of recording (recording), reproducing, and editing an audio signal, an analog audio signal is magnetically recorded on a magnetic tape, and the analog signal is reproduced and edited. However, in such a conventional technique, since analog recording and reproduction are performed, deterioration of sound quality cannot be avoided. Particularly, once recorded audio is dubbed, the deterioration becomes remarkable.

In addition, since the magnetic tape is used as the recording medium, the editing operation takes a long time to reach the target editing point, and during the editing operation, the recording portion of the magnetic tape is physically cut and pasted. However, there is also a problem that it cannot be performed unless it is copied once to another location.

Although the problem of sound quality deterioration can be dealt with by digitizing the recording method on the magnetic tape, the disadvantages related to the cueing and the degree of freedom of editing caused by using a sequential access recording medium are the same.

Therefore, in recent years, proposals have been made to solve the conventional problems by performing disk recording using a Winchester-type hard disk as a recording medium (for example, JAS Journal '89 April, pages 16 to 16). (See p.22, "Digital Audio Workstation (DAW) Trends-From AES Japan January Meeting)."

By the way, an external storage device such as a hard disk generally has a lower data transfer speed than that of a RAM and takes a long time to access, and this is a particular problem when recording and reproducing a plurality of tracks in one external storage device in real time. Come.

[Object of the Invention] The present invention solves the above-mentioned problems, prevents the hardware from increasing in size, and furthermore, a central processing unit (CPU)
It is an object of the present invention to provide a digital multi-track recorder that does not burden the user.

[Configuration and Function of the Invention] In the present invention, audio input / output means for inputting / outputting audio data independently for each of a plurality of tracks, and audio data for each track input / output from the audio input / output means, Buffer means for temporarily storing data for each corresponding track; external storage means for individually reading and writing the audio data for each of the tracks; and one for priority between the audio input / output means and the buffer means. While the audio data for the sample is single-transferred for each track, the audio data for a plurality of samples is blocked for each track between the buffer means and the external storage means during a period in which the single transfer is not performed. Data transfer means for transferring.

According to such a configuration, the voice input / output unit /
While the single transfer (one sample data transfer) is preferentially performed between the buffer means, the block transfer (multiple sample data transfer) is performed between the buffer means / external storage means during the period in which the single transfer is not performed. It is possible to record (voice input) or reproduce (voice output) real time independently for each of a plurality of tracks, even though an external storage device which has a low data transfer speed and cannot respond at high speed is used. According to the present invention, various configuration examples, modifications, and application examples can be taken. Those skilled in the art will be clear from the description of the following embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of one embodiment, in which recording and playback operations for up to three tracks can be performed simultaneously. The whole is divided into a CPU unit and a DMA unit (audio recording / reproducing processing device) as shown in the figure.

The CPU section includes a CPU 1, a program ROM 2 storing a program (described later in detail) that defines the operation of the CPU 1, an RAM 3 including an area for storing various data, a three-track disk access pointer, a work area, and the like. I / O
It has a keyboard 4 including various function keys, data input keys, and the like, which are peripheral devices connected to the port, and a display device 5 including a CRT or LCD and its driver and performing various displays. As will be described later, the CPU 1 controls each component of the DMA unit as needed during an idle time of the address bus and the data bus of the DMA unit during a real-time operation (recording / playback, etc.), and during editing,
It performs rearrangement of data blocks, operation of a disk access pointer, and the like. As will be described later, the recording / playback mode setting for each track (hereinafter referred to as Tr), start, stop, locate, and edit point designation can be performed from the keyboard 4.

Address signals are sent from the CPU 1 to the address terminals of the program ROM 2 and the RAM 3 via the address bus, and their output terminals are connected to the CPU 1 or the transceiver 7 via the data bus.

That is, in order to connect the CPU unit and the DMA unit,
A buffer 6 and a transceiver 7 are provided in the DMA unit. The buffer 6 is connected to the CPU 1 via an address bus, and further connected to an address bus in the DMA unit. The transceiver 7 is connected to the CPU 1 via a data bus, and further connected to a data bus in the DMA unit.

In the DMA unit, an audio input / output device for Tr1 8-
1. An audio input / output device 8-2 for Tr2 and an audio input / output device 8-3 for Tr3 are provided, and analog audio signals can be input and output independently of each other.

Inside each of the audio input / output devices 8-1 to 8-3, in addition to a converter for selectively performing A / D conversion and D / A conversion, a low-pass filter for removing sampling noise, and a sampling period. A clock circuit for generating a clock is included. In these audio input / output devices 8-1 to 8-3, if the track is set to a record state, an external analog audio signal is appropriately filtered at each sampling period, and then A / D converted to digital audio. Get the data. Conversely, if the track is set to the play state, the digital audio data read out in advance is D / A-converted at each sampling period, filtered appropriately, and output as an analog audio signal.

Each of the audio input / output devices 8-1 to 8-3 of Tr1 to Tr3 is connected to a buffer 9-1 (BUF1) and a buffer 9- via a data bus.
2 (BUF2) and a buffer 9-3 (BUF3) for transmitting and receiving digital audio data.

The buffers 9-1 to 9-3 correspond to Tr1 to Tr3, respectively, and data transfer between the audio input / output devices 8-1 to 8-3 is performed by the DMA controller 10 by a direct memory access method. Will be

Each of the audio input / output devices 8-1 to 8-3 transmits data to the DMA controller 10 from the audio input / output devices 8-1 to 8-3 at a sampling period during recording.
Requests (requests) DMA transfer (single transfer) of digital data related to one sampling in the 1-9-3 directions (transmits a DRQ signal (DRQ1 for Tr1, DRQ1 for Tr2)
2, Tr3 gives DRQ3 to DMA controller 10)), answer from DMA controller 10 (Acknowledge, DAK1 for Tr1, DAK2 for Tr2, DAK3 for Tr3 as DAK3
The actual data transfer is executed by the MA controller 10). At the time of playing, the audio input / output device 8-
A request for DMA transfer (single transfer) of digital data relating to one sampling in the directions 1 to 8-3 is made from the audio input / output devices 8-1 to 8-3, and data transfer is performed by the DMA controller 10 in the same manner as described above. Is executed.

Each of the buffers 9-1 to 9-3 has a capacity capable of storing digital audio data a plurality of times or a large number of times. For example, the RAM is divided into three parts Tr1 to Tr3, and a ring buffer (the last address and the start address are virtually It is configured to function as a FIFO buffer by using it as a buffer that is connected to the memory.

The addresses for the buffers 9-1 to 9-3 are specified by the DMA controller 10 or the like via an address bus. That is, when a DMA transfer is being performed, the address bus, data bus, and control signal lines in the DMA unit are
The DMA controller 10 will occupy it.

The buffers 9-1 to 9-3 are connected via a data bus.
Further, it exchanges data with the hard disk 12 under the control of a hard disk controller (hereinafter, referred to as an HD controller) 11. The hard disk 12 and the HD controller 11 are connected via a data bus and a control signal line, and all the read / write access to the hard disk 12 is performed by the HD controller 11. The hard disk 12 has a storage area divided into three tracks of Tr1 to Tr3, and data transfer with the buffers 9-1 to 9-3 is performed by the DMA controller 10. This is done by the HD controller 11 issuing an interrupt (INT) to the CPU 1 when the transfer of one data block is completed, and instructing the CPU 1 to transfer the next data block. CPU1 is
When the interrupt signal INT arrives from the HD controller 11, the DMA controller 10 and the HD controller are set to desired states or programmed, and then the DMA transfer is performed. Details of this operation will be described later.

At the time of play, the DMA controller 10 reads digital audio data of a predetermined amount (for a plurality of sampling periods) from the hard disk 12 and then transfers the read digital audio data to the designated buffer among the buffers 9-1 to 9-3. It operates to perform DMA transfer (block transfer). At the time of recording, it reads out digital audio data of a specified amount (for a plurality of sampling cycles) from a specified buffer and transfers it to a specified position on the hard disk 12 by DMA transfer (Block transfer).

When data is transferred between the hard disk 12 and the buffers 9-1 to 9-3, a request signal DREQ is output from the HD controller 11 to the DMA controller 10 (the DMA controller 10 receives the request signal DREQ), and the data can be transferred. Then, the answer signal DACK is received in reverse.
(AK4 output), the actual transfer state is established.

As described above, the DMA controller 10 performs data transfer of three channels (CH1 to CH3 described later) between the audio input / output devices 8-1 to 8-3 of Tr1 to Tr3 and the buffers 9-1 to 9-3. , Any of the buffers 9-1 to 9- selected in order.
One channel between the hard disk 3 and the hard disk 12 (described later)
Performs time-division data transfer operation for a total of four channels with the data transfer of CH4).

The CPU 1 supplies an address signal to the buffer 6 via an address bus and supplies a designation signal of each component to the decoder 13 via the buffer 6 in order to manage the function and operation of each component in the DMA unit. , Each designated signal CS
To each of the audio input / output devices 8-1 to 8-3, the buffer 9-1.
9-3, the DMA controller 10 and the HD controller 11. At the same time, various data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Further, the CPU 1 sends the IO signals of the audio input / output devices 8-1 to 8-3.
The WR terminal has a designation signal WR that designates whether to enter a record state (write state) or a play state (read state).
Is provided via the buffer 6.

Each of the buffers 9-1 to 9-3 and the DMA controller 1
0, this designation signal (write signal) WR and another designation signal (read signal) RD are also supplied from the CPU 1 via the buffer 6 to the HD controller 11 so that data can be read from or read from each component. Or to write data to. The DMA controller 10 also outputs these designation signals RD and WR in the DMA transfer state. The relationship between these signals and the function and operation of each component will be described later.

The DMA controller 10 sets the DMA enable (enabling) signal DMAENB to “1” and outputs it when the DMA transfer is being performed between the components. As a result, the output of the AND gate 14 to which the signal DMAENB is given via the inverter 16 becomes "0", and the enabling signal E is given to the buffer 6 and the transceiver 7 as "0". Data and addresses cannot be exchanged. At this time, if a "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1".
A wait signal WAIT is supplied to CPU1.

That is, when the CPU 1 supplies a predetermined signal to the decoder 13 to listen to the buffer 6 and the transceiver 7 in order to manage the DMA unit, that is, the “1” signal from the decoder 13 is supplied to the − input terminal of the AND gate 14. Is supplied (the CPU 1 has buffers 9-1 to 9-3, the DMA controller 1
0, HD controller 11, audio input / output devices 8-1 to 8-3
Is output, the output of the decoder 13 becomes active, and the output to the-input terminal of each of the AND gates 14 and 15 becomes "1". ),
When the DMA transfer is started, a wait (WAIT) is applied to the CPU 1, and after the DMA transfer is executed with priority, the operation of the CPU 1 is restarted with the release of the wait.

Conversely, even if the CPU 1 attempts to access the DMA controller 10, for example, while the DMA controller 10 is executing a DMA transfer, the wait signal from the AND gate 15 is output from the AND gate 15.
When WAIT is given, the execution cycle of the CPU 1 is extended halfway, and the buffer 6 and the transceiver 7 are closed during that time.

In the end, the reason why the CPU 1 can access each component of the DMA unit is that the CPU 1 issues an address for accessing each component of the DMA unit.

The signal DMAENB is inactive (“0”), that is, the data bus of the DMA section is free.

When these two conditions are satisfied, the CPU 1 can proceed with the processing without considering when to access the DMA unit by the operation of the gates 14, 15, and 16 as described above.

Further, when the CPU 1 wants to immediately change the operation state of the DMA unit in response to a key input or a trigger of control data, the CPU 1 issues a DMA transfer to the DMA controller 10 regardless of the state of the DMA controller 10. An interrupt command DMAEND can be output (this is given to the DMA controller 10 as an END signal).

<Main Configuration of DMA Controller 10> Next, a configuration example of the DMA controller 10 will be described. DMA
The controller 10 has a transfer capability in which one bus cycle is several hundred nanoseconds. Therefore, the time for transferring the sampling data for three tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, the interval of one sampling time is about 21 microseconds, and most of the sampling time interval is between the buffers 9-1 to 9-3 and the HD.
It is possible to dedicate data transfer between the controller 11 and the hard disk 12 and programming time of each component from the CPU 1.

Now, the main configuration of the specific example is shown in FIG. The DMA controller 10 has an input (IN) address buffer 101 connected to an address bus and an output (O)
UT). The contents specified by the register selector 103 change according to the address signal given to the input-side address buffer 101, and the desired registers existing in the address register 104 and the control register 105 are specified.

The address register 104 and the control register 105 have four channels CH1 to CH4.
CH1 to CH3 are registers for performing DMA transfer between the buffers 9-1 to 9-3 and the audio input / output devices 8-1 to 8-3, and the channel CH4 is for buffers 9-1 to 9-. DM between the designated buffer of 3 and the hard disk 12
This is a register for performing A transfer.

The registers of the channels CH1 to CH4 in the address register 104 have corresponding buffers 9-1 to 9-3 and an area for storing at least the current address and start address of the designated buffer. In the areas of the channels CH1 to CH4, for example, control data for designating the direction of the DMA transfer is stored.

This address register 104, control register 105
Can be input / output to / from the data bus via the data buffer 106. These components are controlled by the timing control logic 107, the service controller 108, and the channel selector 109.

The service controller 108 is controlled by a hard logic or a microprogram, and receives a signal from the timing control logic 107 and the audio input / output device 8.
-1 to 8-3, DMA request signal DRQ from HD controller 11
In addition to receiving DMA interrupt commands END (DMAEND) from the CPU 1 to DRQ4 and the CPU 1, it outputs answer (acknowledge) signals DAK1 to DAK4 to the above-described components, a DMA enable (enabling) signal DMAENB indicating that DMA transfer is in progress, and a DMAENB signal. It issues various commands to the timing control logic 107 and outputs a channel select signal to the channel selector 109. The channel selector 109 selectively designates a register corresponding to each of the channels CH1 to CH4 in the address register 104 and the control register 105.

The timing control logic 107 includes a decoder 1
3, the control signal from the control register 105, the control signal from the service controller 108, and the address buffer 102, the data buffer 1
06 I / O control and address increment 11
By operating 0, the current address register of the specified channel in the address register 104 is incremented.

<Overall Operation of CPU 1> The operation of the present embodiment will be described below. A flowchart showing the operation of the CPU 1 is shown in FIG. 3 and FIG. This is based on a program (software) stored in the program ROM 2. FIG. 3 shows a main routine, and FIG. 4 shows an interrupt routine executed in response to an interrupt signal INT from the HD controller 11. I have.

First, in FIG. 3, it is judged whether the mode set by the keyboard 4 is the play / record mode or the edit (edit) mode (see FIG. 3).
1). If you are in edit mode,
The CPU 1 determines the track or point to be edited, and what kind of editing is to be performed (for example, shifting the timing of the sound recorded at the designated point for a certain time back, forth, correcting, or deleting), For this purpose, control data is generated and stored in the RAM 3 (3-3), and after performing various editing operations, the process returns to 3-1 again.

Although this editing operation is not described in detail, the hard disk drive 12 for the HD controller 11 and the DMA controller 10 is not described.
Read access point program from RAM and RAM3
Transfer to the RAM, various edits using the RAM 3, and the work of restoring the edited digital audio data to the hard disk 12,
An access point is specified under the control of the CPU 1.

When the CPU 1 judges that the current mode is the play / record mode, the process proceeds from 3-1 to 3-4, and the operation mode of each of the three tracks is set according to the input instruction of the keyboard 4. Whether each of the audio input / output devices 8-1 to 8-3 performs the operation of / D conversion or D / A conversion is determined by giving IOWR while sequentially transmitting the designated signal CS via the buffer 6 and the decoder 13. Set. Now
For example, Tr1 is in the play state (according to the D / A conversion operation state), and Tr2 and Tr3 are each in the record state (according to the A / D conversion state).
Conversion operation state). FIG. 8 shows a conceptual diagram of a schematic operation when such a mode is set.

Then, in 3-5, each T
The addresses of buffers 9-1 to 9-3 for r1 to Tr3 are initialized. That is, the address buffer 10 shown in FIG.
1. While specifying registers (address register 104, control register 105) of channels CH1 to CH3 by register selector 103, channel selector 109, etc.,
Initial setting data is input and set via the data buffer 106.

Here, the buffers 9-1 to 9-3 are used cyclically as ring buffers, and the initial address and the current address of each of the buffers 9-1 to 9-3 are initially set. (FIG. 8 schematically shows a state in which the start address and the current address of each of the buffers 9-1 to 9-3 are stored and controlled in the address registers 104 of CH1 to CH3. It is.).

Subsequently, the CPU 1 executes the processing of 3-6, and initializes the disk access pointers corresponding to the respective tracks Tr1 to Tr3 of the hard disk 12 existing in the work (work) memory area in the RAM 3 (see FIG. Shows the relationship between the storage area and the disk access pointer.)

Next, the CPU 1 controls the A / D of each of the audio input / output devices 8-1 to 8-3.
A conversion operation or a D / A conversion operation is started (3-7). Subsequently, in 3-8, a software interrupt is issued,
The HD controller 11 has a hard disk 12 and a buffer 9-
1 to 9-3, a program request for data transfer (the HD controller 11 interrupts the CPU 1
T) is performed (the same process as that described later) is performed.

Specifically, the operation according to the flowchart shown in FIG. 4 is executed in 3-8. For example, in this case, for the Tr1, the channel CH1 corresponding to the Tr1 is determined as the channel of the DMA controller 10 in order to DMA-transfer the digital audio data from the bird disk 12 to the buffer 9-1 (4-1).

Subsequently, the start address of CH1 (initial assumption of 3-5 as described above) is copied as the start address of CH4 (4-2). The operation of the DMA controller 10 at this time will be described later. Then, in this case CH1
The number of data transfers is calculated from the start address and the current address (4-3). Now that it is in the initial state,
No data has been transferred to the buffer 9-1 with respect to Tr1, so that data can be transferred from the hard disk 12 to the entire memory area of the buffer 9-1. Of course, if there are a plurality of tracks at the time of play, the digital audio data stored in advance in the plurality of buffers from the hard disk 12 must be transferred from the hard disk 12 at an early stage. DMA transfer can be performed for each track one after another. Alternatively, the play / record operation may be started synchronously after the data is completely transferred from the hard disk 12 to the necessary buffers 9-1 to 9-3 in advance.

Next, at 4-4, the contents of the current address of CH1 are copied to the start address in this case. In this case, the initial address is eventually the start address.

As described above, the CPU 1 performs DMA transfer in 4-1 to 4-4.
After performing each setting / control on the controller 10,
Next, proceeding to 4-5, the disk access pointer of Tr1 is taken out from the working memory of RAM3, and further, in 4-6, the CH of the control register 105 of the DMA controller 10 is
According to the operation mode (now play mode) of Tr1 obtained according to the contents of the area 1, the disk access pointer for this Tr1, and the number of data transfers from the hard disk 12 to the buffer 9-1 determined in 4-3, the HD Program the controller 11. The operation of the HD controller 11 at this time will be described later in detail.

As a result, the HD controller 11 performs DMA transfer in the direction from the hard disk 12 to the buffer 9-1 in this case.
A request (outputs DREQ) to the controller 10 and the DMA controller 10 executes the corresponding DMA transfer. This operation will be described later in detail.

Subsequently, in 4-7, the CPU 1 updates the disk access pointer of Tr1 in the working memory of the RAM 3 to a value that the disk access pointer will take as a result of executing the above-described transfer processing. That is, as can be understood from the above description, the data transfer between the hard disk 12 and the buffer 9-1 is thereafter performed by the DMA controller 10, and the CPU 1 accesses the hard disk 12 when the DMA transfer is completed. The value taken by the pointer is set at 4-7. Then, the main routine (FIG. 3) returns.

As will be apparent from the following description, once the first interrupt routine (FIG. 4) is activated and the HD controller 11 is operated once, the HD is executed every time the transfer of the data block specified by the CPU 1 is completed. Since an interrupt is issued from the controller 11 (INT signal is given to CPU1),
PU1 performs the recording / playback operation,
It only determines whether a key input has been made or a trigger specified in the control data has been activated.

That is, the CPU 1 refers to the disk access pointer (RAM3) in 3-9 to judge whether or not the memory area is over, that is, whether or not to end (3-10). -1 to 8-3 A / D conversion, D / A
The conversion operation is stopped (3-11). If NO, the control data and the key input state are referred to (3-12). If there is no change, the process proceeds to 3-9 to check the disk access pointer. Return and repeat 3-9 to 3-13 below.

And if there is any change in 3-12,
From 13 to 3-14, the CPU 1 temporarily suspends the DMA transfer and sends a D
Output MA stop command (DMAEND). Subsequently, the DMA controller 10 and the audio input / output devices 8-1 to 8-3 are programmed according to a new input instruction or the like (3-15), and the process proceeds to 3-16 to restart the DMA operation again. After executing the routine of FIG. 4 in the same manner as -8, the process returns to 3-9.

As described above, the CPU 1 performs the initial setting of 3-4 to 3-8 at the time of play / recording,
9, 3-10, 3-12, 3-13 and 3-14 to 3-16 are repeatedly executed, and a change instruction on the keyboard 4 (for example, pause (A / D, D / A interruption) for a certain track) or In response to punch-in / out (switching between A / D and D / A operations) and changes in control data obtained during editing, DMA transfer control is immediately interrupted and the program is changed.
It operates to execute the same processing again.

<Operations of Audio Input / Output Devices 8-1 to 8-3> Next, referring to FIG.
3 will be described. This flowchart may be based on microprogram control or hard logic control, and various means for implementing functions can be selected.

By the way, in 5-1 the designation signal CS of the audio input / output device has arrived from the CPU 1 (it is active).
Judgment is made as to whether or not, and if YES, the operation state (record, play, stop, etc.) is set by the CPU 1 in 5-2. This corresponds to 3- in the main routine of CPU1 in FIG.
This is done in response to 5, 3-15.

Then, if a determination of NO is made in 5-1, 5-3
It is determined whether the audio input / output devices 8-1 to 8-3 are in a record state or a play state. Then, when it is determined that the game is in the play state, the process proceeds to 5-10 to 5-15.

First, the operation of the audio input / output devices set to the record state (the audio input / output devices 8-2 and 8-3 in this case) will be described. At 5-4, it is determined whether or not the sampling time has come, and this 5-4 is repeated until the sampling time comes. The determination of the sampling time may be performed by using a hard timer in each of the audio input / output devices 8-1 to 8-3 and outputting the same, or a common hard timer may be provided and each audio input / output device may operate in accordance with the output. It may be operated. As will be understood from the following description, it is also possible to make the sampling frequency of each of the audio input / output devices 8-1 to 8-3 different.

When the determination of YES is made in 5-4, the given analog audio signal is sampled and held (S /
H) Then, perform A / D conversion. Subsequently, in 5-6, the DMA transfer request DRQ is activated and output to the DMA controller 10.

The DMA controller 10 receives the request signal DRQ,
The response signal DAK is output to perform the DMA transfer (the detailed operation in this case will be described later). Therefore, the voice input / output devices 8-1 to 8-3 (the voice input / output devices 8-2 or 8-3 in the record state in this case) determine YES in 5-7.
In step 5-8, the digital audio data obtained by the A / D conversion is output to the data bus, and the corresponding buffer 9-
1 to 9-3 (in this case, the buffer 9-2 or 9-3). Then, at 5-9, the DMA transfer request DRQ is made inactive. Therefore, in this case, the audio input / output device 8
-2 and 8-3, an analog audio signal supplied from the outside is converted into a digital audio signal at each sampling period, and the buffers 9-2 and 9 designated by the DMA controller 10 as described later. -3 (see FIG. 8).

If it is determined in 5-3 that the player is in the play state, 5
Proceeds to -10, and the DMA transfer request DRQ is sent to the DMA controller 10.
Is activated and the answer signal DAK is sent from the DMA controller 10.
(5-11), digital audio data on the data bus is fetched (5-12), and the request DRQ is made inactive (5-13). DMA controller 1 at this time
Although the operation of 0 will be described later, in this case, as shown in FIG. 8, the contents of the current address of the buffer 9-1 corresponding to Tr1 (this is the contents of the area of Tr1 of the hard disk 12 already transferred and recorded) .) Is input to the voice input / output device 8-1 by the above operation. Then, it is determined whether or not the sampling time has come (5-1).
Four). The detection of the arrival of the sampling time is the same as that described in 5-4.

If the answer is YES in 5-14, the process proceeds to 5-15, where D / A conversion and low-pass filtering are performed, and then an analog audio signal is output to the outside.

As described above, 1 in the case of the record state and the case of the play state
The operation at one sampling time has been described.
After the end of each of the processes 9 and 5-15, the process returns to 5-1 to execute the processes for the sampling times one after another in the same manner.

FIG. 9 shows an operation time chart of the audio input / output devices 8-1 to 8-3. In this case, the audio input / output device 8-1 of Tr1 is in the play mode, and the sampling time t and the sampling time During t + 1, a sampling request (DRQ) occurs and the channel in the DMA controller 10 is
Under the control of CH1, DMA transfer from the buffer 9-1 to the audio input / output device 8-1 is performed, and a D / A conversion operation is performed in synchronization with the sampling time t + 1.

Conversely, in this case, the audio input / output device 8-2 of Tr2 and Tr3,
8-3, a record mode is set, A / D conversion is performed in synchronization with the sampling time t or t + 1, and then a DMA transfer instruction is output to the DMA controller 10 to perform DMA transfer. Tr2, Tr3 in order (simultaneously DMA
This is due to the relationship that the priority when requested is CH1>CH2>CH3> CH4. ) Is executed, and data is transferred from the audio input / output devices 8-2 and 8-3 to the buffers 9-2 and 9-3.

<Operation of DMA Controller 10> Next, the operation of the DMA controller 10 will be described with reference to FIG. The flowchart of FIG. 6 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the function of the DMA controller 10 may be realized by hard logic.

First, in 6-1 it is determined whether or not the designated signal CS from the CPU 1 has arrived (it is active).
If S, either read signal RD or write signal WR is CPU1
From the read signal RD.
Proceed to 3 to output the contents of the registers 104 and 105 specified by the address signal given via the address bus via the data bus so that the CPU 1 can read them. Then, desired data is input and set to the designated register via the data bus. The processing of 6-3 and 6-4 corresponds to the processing of 3-5, 3-15 and the like of the main routine of the CPU 1. Therefore, 6
The desired data is set in each of the registers 104 and 105 in FIG. 2 by the process of -4.

When the CPU 1 accesses the DMA controller 10 or completes the program, the designation signal CS becomes inactive, and the process proceeds from 6-1 to 6-5.

In 6-5, the audio input / output devices 8-1 to 8-3 send DM
A Check whether transfer requests DRQ1 to DRQ3 are
From the DMA transfer request DREQ (DRQ4), if there is a request from any of them, proceed to 6-6,
Set enable signal DMAENB to “1” (active) and set the address bus and data bus in the DMA unit to DMA controller 1
0 is occupied and access from CPU 1 is not accepted.

Subsequently, for a plurality of requests, channels CH1 to CH4
The channels are selected according to the priority order of (6).
7). For example, in the example of FIG.
2. Data transfer requests from the voice input / output devices 8-2 and 8-3 of Tr3 are made at the same time, but since Tr2 has a higher priority,
First, the DMA transfer of CH2 is performed. Also, as will be understood in the following description, since the priority order of CH4 is the lowest, when data is transferred between the hard disk 12 and one of the buffers 9-1 to 9-3, any audio input is performed. When a request for data transfer is made from the output device 8-1 to 8-3, the latter data transfer is preferentially performed first.

Subsequently, the current address (the content of the current address register of CH2 of the address register 104) of the selected channel (now, for example, CH2) is output to the address bus (6-8). And the selected channel (for example,
CH2) by referring to the contents of control register 105
It decides in which direction the transfer is to be performed (6-9), and if the transfer is from buffer 9-1 to 9-3 to another element (I / O), it proceeds from 6-10 to 6-11, 9-1 to 9-3
The read signal RD is supplied to the buffer selected from among the buffers 9-1 to 9-3 from the other elements (I / O).
If it is transferred to the buffer, the process proceeds to 6-12, and the write signal WR is given to the buffer.

Thereafter, the answer signal DAK is activated (6-1).
3). As a result, in this case, the Tr2 audio input / output device 8-
2 is to transmit the sampled audio data to the data bus by the processing of 5-7 and 5-8 (FIG. 5), and to write the data to the area of the current address of the buffer 9-2 by the DMA controller 10. (See FIG. 8).

At 6-14, since the data transfer has been completed, the read signal RD or write signal WR and the answer signal DAK are made inactive. At 6-15, the current address (the address register 104 in FIG. 2) of the channel (now CH2) is set. +1 is added to the contents of (in). The operation of 6-15 causes the buffer 9-1 to operate.
The count is incremented each time new sampled audio data is written or new audio data is read out for .about.9-3. Then, after the process of 6-15, the process returns to 6-1.

In the previous state (see FIG. 9), a data transfer request has been made to the DMA controller 10 from the audio input / output devices 8-2 and 8-3 of Tr2 and Tr3, and data transfer has been performed only for Tr2 so far. 6-
At 5, a YES determination is made. Below, regarding Tr3,
Data transfer in the direction from the audio input / output device 8-3 to the buffer 9-3 is performed in the same manner as described above by executing 6-7 to 6-10 and 6-12 to 6-15.

When such data transfer is completed, 6-5 to 6-15
Then, the DMA enable signal is set to "0" (inactive) to stop the DMA controller 10 from occupying the data bus and the address bus in the DMA unit, so that the access from the CPU 1 can be accepted.

As described above, regarding the Tr2 and Tr3, the audio input / output devices 8-2 and 8-3
The data transfer from the buffer 9-1 to the audio input / output device 8-1 has been described for the Tr1.
Made by the A controller 10.

As shown in FIG. 9, the sampling times t and t
The audio input / output device 8-1 corresponding to Tr1 in the middle of +1
Outputs a request signal DRQ to the DMA controller 10 (fifth
(Fig. 5-10).

In response, the DMA controller 10 responds to the
-5 to 6-7 are executed, and in 6-8, the buffer 9-
Address data indicating an address to be read is given via an address bus. By executing 6-9 and 6-10, the process proceeds to 6-11. This time, the read signal RD is given to the buffer 9-1, and the answer signal DAK is set to "1" at 6-13.

As a result, the digital audio data of the designated address of the buffer 9-1 is transferred to the audio input / output device 8-1 of Tr1 via the data bus and is taken in. Thereafter, the process returns to 6-1 through the processes of 6-14 and 6-15.

The DMA controller 10 also performs data transfer between the hard disk 12 and the buffers 9-1 to 9-3. In this case, the address register 104 and the control register 105 of the channel CH4 are used. This operation is performed by executing the interrupt routine (FIG. 4) of CPU1.
Setting / control operation 4-1 to 4- for controller 10
4. Programming operation 4 for HD controller 11
Executed after 5, 4-6.

In response to the setting / control operations 4-1 to 4-4 of the CPU 1 for the DMA controller 10, the DMA controller 10
6-3 and 6-4 are performed. That is, the CPU 1 determines a track to which data is transferred by the channel CH4 this time,
The start address of the buffer corresponding to the track (that is, the address next to the block data previously used for data transfer between the buffer and the hard disk 12) is set to CH4.
In the start address register (in the address register 104 in FIG. 2), and the current data transfer number for this track is set to the start address and the current address (after the previous data transfer was performed between the hard disk 12 and the previous step). Address), CPU1 gets
Copy the current address for this track to the start address.

The CPU 1 controls the buffer 9-1 corresponding to the track being operated.
9-3 and the hard disk 12 are sequentially performed for each track, and the data transfer following the previous data transfer (block transfer) is performed for each track. In the example of FIG. 8, for example, for Tr1, the data amount corresponding to the hatched portion between the illustrated start address (CH1) and the current address (CH1) is transferred from the hard disk 12 (other tracks). , The data transfer direction is reversed, but it is clear that similar control is performed.) Note that, in the buffer in the play mode (corresponding to 9-1), the hatched portion corresponds to the data portion that has already been voice-output, and in the buffer in the record mode (corresponding to 9-2 and 9-3), the hatched portion is voice-inputted. Corresponding to the data portion.

Then, after performing programming on the HD controller 11 by 4-5 and 4-6, the CPU 1 generates an actual transfer request from the HD controller 11 and starts DMA transfer.

When the DMA controller 10 detects that there is a transfer request from the HD controller 11 in 6-5, it executes 6-6 to 6-9 in the same manner as described above, and then executes
6-10, a request for data transfer from the hard disk 12 to the hard disk 12 or a request for data transfer from the hard disk 12 to the buffer 9-1 to 9-3. Then go to 6-12, 6-13 ~
6-15 are executed. At this time, for example, digital audio data for one sample is transferred by one transfer operation, so that the operations 6-5 to 6-15 are repeated a plurality of times to perform block transfer. The data transfer between the hard disk 12 and the buffers 9-1 to 9-3 will be further described later because the operation of the HD controller 11 is also greatly related.

When the DMA transfer is completed, the request signals DRQ1 to DRQ4 do not arrive, and the process proceeds from 6-5 to 6-16, where the DMA enable signal DQ
MAENB is set to “0” (inactive).

<Operation of HD Controller 11> Next, the operation of the HD controller 11 will be described with reference to FIG. The HD controller 11 may be based on hardware logic or microprogram control, and in any case, realizes the operation flow of FIG.

First, it is determined whether the designation signal CS is given from the CPU 1 (7-1). This is given by the interrupt routine of the CPU 1 (4-5, 4-6 in FIG. 4). In the case of NO, the process returns to the original. In the case of YES, the process proceeds to step 7-2 to determine whether the read signal RD or the write signal WR is supplied from the CPU 1.
Outputs the internal designated data (contents of the address register, etc.) to the CPU 1 via the data bus.

When the write signal WR is given, the process proceeds from 7-2 to 7-4, and the channel C of the DMA controller 10 is
The data transfer direction between the buffer for DMA transfer and the hard disk 12 is set at H4, and the access point of the hard disk 12 to be accessed is set at 7-5. this is,
Based on the access pointer of the track obtained by the CPU 1 from the RAM 3 (FIG. 4, 4-5).

Subsequently, in 7-6, the number of transfer data (the number of digital audio data) is set in an internal counter of the HD controller 11. This transfer data number is obtained in 4-6 in the interrupt routine of the CPU 1.

Thus, by executing 7-4 to 7-6,
The HD controller 11 is programmed under the control of the CPU 1, and thereafter, the HD controller requests the DMA controller 10 for data transfer (7-7). As can be understood from this, when receiving the interrupt signal INT from the HD controller 11, the CPU 1 corresponds to the next track (that is, if Tr1 to Tr3 are all operating now, Tr1, T2
r2, Tr3, Tr1, ... in order) DMA transfer setting and control
Execute for MA controller 10 to program HD controller 11. After that, the CPU 1
Apart from the controller 10, the actual DMA transfer is executed by mutual interaction.

The HD controller 11 proceeds to 7-8 after 7-7,
7-8 are repeated until the answer signal DACK (DAK4) is received from the A controller 10 (see 6-13 in FIG. 6).

If the judgment in step 7-8 is YES, the process proceeds to step 7-9, where the digital audio data of one sample is transferred by the operation of CH4 of the DMA controller 10, and the transfer counter set in step 7-6 is counted down by one. (7-10). Follow 7
At -11, judgment is made in accordance with the contents of the transfer counter as to whether the data transfer for the preset number of transfer data is completed, and if NO, the process returns to 7-8 again. Therefore, DMA
In the controller 10, the transfer (block transfer) of the number of data set from the HD controller 11 is completed.
The transfer request DRQ4 is continuously received, and the processing of FIGS. 6-5 to 6-15 (FIG. 6) is executed in accordance with the transfer request.
In response to this, the HD controller 11 has 7-8 to 7
Execute the process of -11.

When the end of the transfer is determined in 7-11, 7-12
The request DREQ (DRQ4) for data transfer from the HD controller 11 to the DMA controller 10 is set to “0” (inactive). Then, the HD controller 11 supplies an interrupt signal INT to the CPU 1 to cause the data transfer between the hard disk 12 and any of the buffers 9-1 to 9-3 for the next track (7-13). In response to this, the CPU 1 executes the interrupt routine (FIG. 4) as described above.

<Data Transfer Operation Between Hard Disk 12 and Buffers 9-1 to 9-3> In the above description, the hard disk 12 and the buffer 9-
The data transfer between 1 and 9-3 has also been understood, but with reference to FIGS. 8 and 10, how the DMA request is made to the DMA controller 10, The following describes whether or not the DMA controller 10 supports time division.

As described above, in the setting state shown in FIG. 8, Tr1 is in the play state, and Tr2 and Tr3 are in the record state.
8-3, a data transfer request to the buffers 9-1 to 9-3 is made to the DMA controller 10 at each sampling time (fs in FIG. 10).

This occurs while the CPU 1 is programming the HD controller 11 (4-5, 4-6 in FIG. 4, 7-4 to 7-4 in FIG. 7).
7-7) also occurs. When there is a data transfer request from the audio input / output devices 8-1 to 8-3, the DMA controller 10 outputs the DMA enable signal DMAENB as described above (6 in FIG. 6).
-6), the programming of the HD controller 11 by the CPU 1 is interrupted (WAIT), and DMA by each channel CH1 to CH3 is performed.
After the transfer is completed, it is restarted (see FIG. 10).

Also, when the data transfer between the hard disk 12 and the buffers 9-1 to 9-3 is sequentially performed by the DMA transfer by CH4, each of the audio input / output devices 8-1 to 8-3 is also used.
Thereafter, a data transfer request is made for each sampling time (fs in FIG. 10).

At this time, in the DMA controller 10, 6-7 in FIG.
As a result, the data transfer of the higher priority channels (CH1 to CH3) is performed first. During this period, the data transfer request DRQ4 is continuously output from the HD controller 11 to the DMA controller 10 (see FIG. 7, 7-7).
Since the answer signal DAK4 does not return from the A controller 10, it waits for the next data transfer (it repeats 7-8).

Therefore, macroscopically, the DMA controller 10 has the Tr1, Tr2, Tr3 hard disk 12 as shown in FIG.
The DMA transfer (block transfer) between the buffer 9-1 and the buffers 9-1 to 9-3 is repeated. Microscopically, during programming to the HD controller 11, during actual DMA transfer (by CH4), or Even during a pause (idle), the buffers 9-1 to 9
Transfer (single transfer) between the audio input / output device 8-1 and the audio input / output devices 8-1 to 8-3 is performed by each of the channels CH1 to CH3.
Conversion and D / A conversion can be dealt with sufficiently fast.

<Other Embodiments> One embodiment of the present invention has been described above in detail, but the present invention can be variously modified and applied. Example 11
Shown in the figure.

FIG. 11 shows two sets of the DMA units of the above-described embodiment, a three-track DMA unit of Tr1 to Tr3, and Tr4 to Tr6.
This is an example in which a three-track DMA unit and a six-track digital multi-track recorder are configured. In other words, the number of multi-tracks can be increased by adding DMA units.

In FIG. 11, a CPU 1 'is connected to each unit via a control bus, an address bus, and a data bus to control and manage six tracks. Also, each DMA
Interrupt signals INT0 and INT1 indicating completion of data transfer with the hard disk are supplied from the unit to the CPU 1 '.

ROM 2 ′ and RAM 3 ′ store programs and data modified in response to the doubling of the number of tracks as in the previous embodiment.

CPU1 'wait (WAIT) signals are Tr1 to Tr3.
The signal from the DMA unit and the signals from the DMA units Tr4 to Tr6 are given via the OR gate 200.

Other configurations and operations are the same as those of the above-described embodiment, so that further description will not be required.

The present invention may further include a digital multi-track recorder of a type capable of changing a sampling frequency of each audio input / output device, in addition to a device having an audio input / output device for inputting / outputting an audio signal at a fixed sampling rate. If the sampling frequency of each audio input / output device is changed depending on the scale frequency (a sampling clock will be generated by a VCO or digital oscillator, etc.)
The entire device becomes a polyphonic sampler (sampling electronic musical instrument). In this case, the sampling clock of each audio input / output device at the time of reproduction (at the time of play) depends on the performance operation.

In addition, by setting different sampling frequencies for each track, a track or the like that does not require high frequencies can be assigned a low sampling frequency, and track control with a high degree of freedom, such as a reduction in data capacity, can be performed.

According to the present invention, while the single transfer (one-sample data transfer) is preferentially performed between the audio input / output unit / buffer unit, the buffer unit / external unit is not used during the single transfer period. Since block transfer (transfer of a plurality of samples) is performed between storage means, multi-track recording in which recording (voice input) or playback (voice output) is independently performed in real time for each of a plurality of tracks has a low data transfer speed. There is an effect that can be realized using an external storage device that cannot respond at high speed.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention, FIG. 1 is an overall configuration diagram of one embodiment, FIG. 2 is a detailed view of a main part of a DMA controller 10 in FIG. 1, and FIG. FIG. 4 is a diagram showing an interrupt routine of the CPU 1 of FIG. 1, and FIG. 5 is a diagram showing the voice input / output devices 8-1 to 8-3 of FIG.
FIG. 6 shows the operation of the DMA controller 10 shown in FIG.
FIG. 7 is a diagram showing the operation of the HD controller 11 of FIG. 1, FIG. 8 is a conceptual diagram showing the overall operation,
FIG. 9 is a time chart showing D / A and A / D conversion operations and DMA transfer for each track, and FIG.
And FIG. 11 is a circuit block diagram of another configuration example of the present invention. 1, 1 'CPU, 2, 2' ROM, 3, 3 'RA
M, 8-1 to 8-3 ... voice input / output device, 9-1 to 9-
3 ... buffer, 10 ... DMA controller, 11 ... HD controller, 12 ... hard disk, 13 ... decoder,
14, 15 ... AND gate, 16 ... inverter.

Claims (1)

(57) [Claims] An audio input / output means for inputting / outputting audio data independently for each of a plurality of tracks, and audio data for each track input / output from the audio input / output means are temporarily stored for each corresponding track. Buffering means, external storage means capable of independently reading and writing the audio data of each track, and between the audio input / output means and the buffer means, the audio data of one sample is preferentially stored. A data transfer unit for performing a single transfer for each track, and a block for transferring a plurality of samples of audio data for each track between the buffer unit and the external storage unit during a period in which the single transfer is not performed; A digital multi-track recorder characterized by comprising: