JP2911133B2 - Time compression device for HDTV receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time compression device for a high-definition television receiver, and more particularly to a method for displaying a NTSC television signal converted into progressive scan on a high-vision display. Further, the present invention relates to a device for performing time compression so that the linearity of a reproduced image is not changed by digital processing.

[Conventional technology]

A reproduced image of an NTSC television signal (hereinafter, referred to as an NTSC signal) converted into a progressive scan has a frame frequency of 59.94 (Hz) and a horizontal frequency of 31.47 (KHz). On the other hand, the HDTV signal has a field frequency of 60 (H
z), the horizontal frequency is 33.75 (KHz). Therefore, NTSC
Since the vertical frequency and the horizontal frequency of the signal and the HDTV signal are very close values, the NTSC signal can be displayed on the HDTV display. At this time, the ratio of the vertical blanking period to one frame period in the NTSC display and the high-vision display is defined by exactly the same value, so that there is no problem in the vertical display. However, while the aspect ratio of the NTSC signal is 4: 3,
The aspect ratio of the HDTV signal is 16: 9. Also NT
The ratio of the horizontal blanking period to one horizontal scanning period in the SC display and the HDTV display is approximately
5: 4. Therefore, when the ratio in the vertical direction is kept constant and the ratio of the number of unit pixels in one horizontal scanning period between the NTSC signal and the Hi-Vision signal is obtained from these numerical values, the ratio is approximately 4: 5. That is, in order to display the NTSC signal on a high-vision display while maintaining the linearity, it must be compressed about 4/5 times in the horizontal direction. A method using a line memory is conceivable for compressing the image by 4/5 in the horizontal direction. Thus, FIG. 4 shows a general configuration of a time compression device of this high-vision receiver.

In the figure, 1 is an NTSC signal input terminal, 2 is an A / D converter which receives a signal arriving at the NTSC signal input terminal 1 and 3 is A
Synchronization / timing pulse generation circuit with the output of the / D converter 2 as input, 4 an IDTV decoder with the output of the A / D converter 2 and the synchronization / timing pulse generation circuit 3 as input, 5 synchronization / timing pulse generation A horizontal synchronizing circuit having an output of the circuit 3 as an input, 6 to 8 are line memories having an output of the IDTV decoder 4 and an output of the horizontal synchronizing circuit 5 as an input, and 15 is a D / A converter having an output of the line memory 6 as an input. 16 is a D / A converter which receives the output of the line memory 7 as an input, and 17 is a line memory 8
A D / A converter having the output of the D / A converter 15, an R signal output terminal having the output of the D / A converter 15 as an input, a G signal output terminal having the output of the D / A converter 16 as an input, Reference numeral 20 denotes a B signal output terminal to which the output of the D / A converter 17 is input, and reference numeral 21 denotes a synchronization signal output terminal to which the output of the synchronization / timing pulse generation circuit 3 is input.

 Next, the operation will be described.

The analog signal arriving at NTSC signal input terminal 1 is A /
The signal is input to the D converter 2 and converted into a digital signal. The output of the A / D converter 2 is input to the synchronization / timing pulse generation circuit 3 and the IDTV decoder 4. The synchronization / timing pulse generation circuit 3 generates a clock synchronized with the output signal of the A / D converter 2 and outputs a clock and various timing pulses to the IDTV decoder 4 and the horizontal synchronization circuit 5. Further, it outputs a synchronization signal to the synchronization signal output terminal 21. The IDTV decoder 4 digitally processes the output of the A / D converter 2 to perform luminance signal chrominance signal separation and sequential scan conversion. The frame frequency is 59.94 (Hz), the number of scan lines is 525, and the progressive scan RGB signal is stored in a line memory. Output to 6,7,8. Digital processing of the IDTV decoder 4 is controlled by the output of the synchronization / timing pulse generation circuit 3. The RGB outputs of the IDTV decoder 4 are time-compressed by the line memories 6, 7, and 8, respectively. At this time, the control of the line memories 6, 7, 8 is performed by the output of the horizontal synchronization circuit 5.

 Next, the configuration of the horizontal synchronization circuit 5 is shown in FIG.

The clock (WCK) output from the synchronization / timing pulse generation circuit 3 is horizontally synchronized at the same frequency as the transmission rate of the output data of the IDTV decoder 4. Horizontal counter 22
Counts WCK. The horizontal counter 26 counts the clock (RCK) output from the voltage control generator (VCO) 25. The number of samples in one horizontal scanning period is set in the horizontal counters 22 and 26 in advance, and the set value of the horizontal counter 22 is 4/5 times the set value of the horizontal counter 26. The outputs of the horizontal counters 22 and 26 are input to a phase comparator 23,
The phase is compared every horizontal scanning period. The output of the phase comparator 23 is integrated by the loop filter 24 and becomes the control voltage of the voltage controlled oscillator 25. When the loop of the horizontal synchronization circuit 5 becomes stable,
A clock whose frequency is 5/4 times that of the clock of the horizontal counter 22 is obtained by a clock horizontally synchronized with the output of the voltage controlled oscillator 25. Therefore, WCK is used as a write clock for the line memories 6, 7, and 8, and a reset pulse (WRT) obtained from the horizontal counter 22 is used for resetting. Similarly, RCK is used as a read clock for the line memories 6, 7, and 8, and a reset pulse (RRT) obtained from the horizontal counter 26 is used for resetting. In addition, in order to determine the horizontal position when the power is turned on, the horizontal counter 22 is reset by the horizontal timing pulse (HD) output from the synchronization / timing pulse generation circuit 3. Accordingly, the read clock RCK of the line memories 6, 7, 8 is horizontally synchronized with the write clock WCK, and since the RCK is 5/4 times the frequency of WCK, the output of the IDTV decoder 4 is 4/5 in the horizontal direction.
Time compressed twice. The outputs of the line memories 6, 7, 8 are input to the D / A converters 15 to 18 and converted into analog signals. The output of the D / A converter 15 is input to an R signal output terminal 18, the output of the D / A converter 16 is input to a G signal output terminal 19, and the output of the D / A converter 17 is a B signal output terminal 20. Is input to

[Problems to be solved by the invention]

Since the conventional time compression device of the HDTV receiver is configured as described above, there is a problem that a portion where a signal is missing occurs on the screen of the HDTV display and burning of a CRT occurs.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-described problems, and has as its object to provide a time compression device for a high-definition receiver capable of eliminating a missing portion of a signal and preventing burning of a CRT. .

[Means for solving the problem]

A time compression device for a high-definition television receiver according to the present invention includes an A / D conversion unit that converts an NTSC composite television signal into a digital signal, and a clock or timing pulse from an output signal of the A / D conversion unit. A synchronous / timing pulse generating means, an IDTV decoder for outputting a signal of a digital amount of sequential scanning from the output signal of the A / D converting means and the output signal of the synchronous / timing pulse generating means, and a digital signal of the IDTV decoder. Time compression means for time-compressing the amount of output signal in the horizontal direction, and a character decoder for reproducing and outputting text information of text multiplex broadcasting from the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generation means Switching between a signal obtained by time-compressing the digital output signal of the IDTV decoder in the horizontal direction and the output signal of the character decoder. Output.

The time compression device for a high-definition receiver according to the present invention is the time compression device for a high-definition receiver described above, wherein the line memory having the output signal of the IDTV decoder as an input signal, and the output signal of the character decoder being an input signal. A buffer memory, a memory control means for controlling the buffer memory, a selector for switching output signals of the line memory and the buffer memory, and an output of the synchronization / timing pulse generating means as inputs, and A control signal for horizontally compressing the output signal of the IDTV decoder in the horizontal direction, and controlling the selector and the memory control means to output the output signal of the buffer memory when the output of the line memory is not performed. Horizontal synchronizing means for outputting a signal. .

Further, in the time compression device for a high-vision receiver according to the present invention, in the time compression device for a high-vision receiver described above, the time synchronization unit may be configured to count the output signal of the synchronization / timing pulse generation unit for one horizontal scanning period. 1 horizontal counter and the output of the first horizontal counter,
A phase comparison means for receiving an output of a second horizontal counter described later as an input, a loop filter for integrating an output of the phase comparison means, a voltage control oscillating means for receiving an output of the loop filter as an input, And a second horizontal counter for counting the output signal of the oscillating means for one horizontal scanning period.

[Action]

According to the present invention, when the output of the line memory is blanking, based on the control signal of the horizontal synchronizing circuit, switching from the line memory to the buffer memory is performed, and a character missing portion caused by time-compressing the video signal includes a character. Since the information signal is inserted, burning of the CRT is prevented.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a time compression device of a high-definition television receiver according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an NTSC signal input terminal, and 2 denotes a signal arriving at an NTSC signal input terminal 1. An A / D converter as an input, 3 is a synchronization / timing pulse generation circuit having an output of the A / D converter 2 as an input, and 4 is an output of the A / D converter 2 and a synchronization / timing pulse generation circuit 3. An IDTV decoder as an input, 5 is a horizontal synchronizing circuit having an output of a synchronization / timing pulse generation circuit 3 as an input, 6 to 8 are line memories having an output of an IDTV decoder 4 and an output of a horizontal synchronizing circuit 5 as inputs, and 9 is A A character decoder which receives the output of the / D converter 2 and the output of the synchronization / timing pulse generation circuit 3 as input, 10 is a memory control circuit which receives the output of the horizontal synchronization circuit 5 as input, and 11 is a character decoder 9 and a memory control circuit 10 Buffer input with the output of Memory 12, a selector which receives the outputs of the horizontal synchronization circuit 5, the line memory 6 and the buffer memory 11 as input, 13 a selector which receives the outputs of the horizontal synchronization circuit 5, the line memory 7 and the buffer memory 11, and 14.
Is a horizontal synchronous circuit 5, a line memory 8, and a buffer memory 11.
Selector, the input of which is the output of the selector 13, 15 is a D / A converter that receives the output of the selector 12, 16 is the D / A converter that receives the output of the selector 13, and 17 is the output of the selector 14. D / A
Converter, 18 is an R signal input terminal to which the output of the D / A converter 15 is input, 19 is a G signal input terminal to which the output of the D / A converter 16 is input, and 20 is an input of the D / A converter 17. A B signal input terminal to which the output is input, and 21 is a SYNC signal output terminal to which the output of the synchronization / timing pulse generation circuit 3 is input.

 Next, the operation will be described.

The analog signal arriving at NTSC signal input terminal 1 is
The signal is input to the A / D converter 2 and converted into a digital signal. The output of the A / D converter 2 is input to a synchronization / timing pulse generation circuit 3, an IDTV decoder 4, and a character decoder 9. The synchronization / timing pulse generation circuit 3 generates a clock synchronized with the output signal of the A / D converter 2, and outputs a clock and various timing pulses to the IDTV decoder 4 to the character decoder 9 and the horizontal synchronization circuit 5. Further, it outputs a synchronization signal to a SYNC signal output terminal 21. The IDTV decoder 4 digitally processes the output of the A / D converter 2 to separate the luminance signal and the chrominance signal and perform sequential scan conversion, and obtains a frame frequency of 59.94 (H
z) Outputs 525 scanning lines and sequentially scanned RGB signals to the line memories 6, 7, and 8. Digital processing of the IDTV decoder 4 is controlled by the output of the synchronization / timing pulse generation circuit 3. The line memories 6, 7, 8 compress the RGB signals output from the IDTV decoder 4 by 4/5 times in the horizontal direction by digital processing. At this time, the control of the line memories 6, 7, 8 is performed by the output of the horizontal synchronization circuit 5. The configuration of the horizontal synchronizing circuit 5
Shown in the figure. The control of the line memories 6, 7, 8 is the same as in the conventional example. The output of the A / D converter 2 is input to the character decoder 9, and the character information of the teletext is reproduced. The digital processing of the character decoder 9 is controlled by the output of the synchronization / timing pulse generation circuit 3. The output of the character decoder 9 is input to the buffer memory 11. Selector 12, 13, 14
Switches between the outputs of the line memories 6, 7, 8 and the output of the buffer memory 11. At this time, the buffer memory 11 is controlled by the output of the memory control circuit 10, and the memory control circuit 10, and the selectors 12, 13, and 14 are controlled by the output (SEL) of the horizontal synchronization circuit 5. The outputs of the selectors 12 to 14 are switched so that the output of the buffer memory 11 is output only when the output of the line memories 6 to 8 is at the blanking level, and the display screen is changed as shown in FIGS. 3 (a) and 3 (b). Or, the display is controlled as shown in (c). In FIG. 5, the hatched portion indicates a display portion of the character information. In addition, the memory control circuit 10
Controls the contents of the character information. selector
The outputs 12 to 14 are converted into analog quantities by D / A converters 15 to 17. The R signal output from the selector 12 is output to an R signal output terminal 18. The G signal output from the selector 13 is output to a G signal output terminal 19. The B signal output from the selector 14 is output to a B signal output terminal 20.

According to the above embodiment, the output of the buffer memory to which the character information is input is output only when the output of the line memory is at the blanking level, and the lack of a signal caused by time-compressing the video signal Since the signal of the character information is inserted into the portion where the CRT is inserted, the burn-in of the CRT can be prevented.

〔The invention's effect〕

As described above, according to the time compression device for a high definition receiver according to the present invention, A / D conversion means for converting a composite television signal of the NTSC system into a digital signal,
A synchronization / timing pulse generating means for generating a clock or a timing pulse from the output signal of the / D conversion means;
An IDTV decoder for outputting a digital signal of progressive scanning from the output signal of the D conversion means and the output signal of the synchronization / timing pulse generating means, and time compression for time-compressing the digital output signal of the IDTV decoder in the horizontal direction Means, and a character decoder for reproducing and outputting character information of text multiplex broadcasting from an output signal of the A / D conversion means and an output signal of the synchronization / timing pulse generating means, and a digital amount output signal of the IDTV decoder. Is output by switching between a signal obtained by time-compressing the horizontal direction and an output signal of the character decoder, so that a signal of character information is inserted into a missing portion of a signal generated by time-compressing a video signal. With such a configuration, there is an effect that seizure of the CRT can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a time compression device of a high-definition receiver according to an embodiment of the present invention. FIG. 2 is a diagram showing a configuration of a horizontal synchronization circuit of the time compression device of the high-definition receiver of FIG. FIG. 4 is a diagram showing a display on a high-vision display, FIG. 4 is a block diagram of a conventional time compression device of a high-vision receiver, and FIG. 5 is a diagram showing a configuration of a conventional horizontal synchronization circuit. In the figure, 1 is an NTSC signal input terminal, 2 is an A / D converter,
3 is a synchronization / timing pulse generation circuit, 4 is an IDTV decoder, 5 is a horizontal synchronization circuit, 6, 7, and 8 are line memories, 9 is a character decoder, 10 is a memory control circuit, 11 is a buffer memory, 12, 13, and 14. Is a selector, 15, 16 and 17 are D / A converters, 18 is an R signal output terminal, 19 is a G signal output terminal, 20 is a B signal output terminal, 21 is a SYNC signal output terminal, 22 is a horizontal counter, and 23 is A phase comparator, 24 is a loop filter, 25 is a voltage controlled oscillator, and 26 is a horizontal counter. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

(57) [Claims] A / D conversion means for converting a composite television signal of the NTSC system into a digital signal, and synchronization / timing pulse generation means for generating a clock or a timing pulse from an output signal of the A / D conversion means. An IDTV decoder for outputting a signal of a digital amount of sequential scanning from the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generating means; and outputting the digital amount output signal of the IDTV decoder in the horizontal direction. Time compression means for performing time compression, and a character decoder for reproducing and outputting text information of text multiplex broadcasting from the output signal of the A / D conversion means and the output signal of the synchronization / timing pulse generation means, A high-visibility signal characterized by switching between a signal obtained by temporally compressing an output signal of a digital amount in the horizontal direction and an output signal of the character decoder. Time compression device for the receiver. 2. A time compression device for a high-definition television receiver according to claim 1, wherein: a line memory having an output signal of said IDTV decoder as an input signal; a buffer memory having an output signal of said character decoder as an input signal; A memory control means for controlling a buffer memory; a selector for switching the output signals of the line memory and the buffer memory; an output of the synchronization / timing pulse generating means as an input; and an output signal of the IDTV decoder to the line memory. Horizontal synchronizing means for outputting a control signal for horizontally compressing time and outputting a control signal to the selector and the memory control means for outputting an output signal of the buffer memory when the output of the line memory is not performed. A time compression device for a high-definition receiver, comprising: 3. The time compression device for a high-definition receiver according to claim 2, wherein said horizontal synchronization means comprises: a first horizontal counter for counting an output signal of said synchronization / timing pulse generation means for one horizontal scanning period; Phase comparison means for receiving an output of a first horizontal counter and an output of a second horizontal counter described later, a loop filter for integrating an output of the phase comparison means, and a voltage for receiving an output of the loop filter as an input A time compression device for a high-definition television receiver, comprising: a control oscillation means; and a second horizontal counter for counting an output signal of the voltage control oscillation means for one horizontal scanning period.