JP2909653B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field of the Present Invention> The present invention relates to a PLL circuit.

<Prior art> A PLL circuit that controls the oscillation frequency of the oscillator so that the phase difference between the output component signal of the oscillator and the reference signal always becomes a predetermined value, and stabilizes the oscillation frequency, improves the S / M, or adjusts the FM signal It has been widely used for demodulation and the like.

FIG. 4 is a block diagram showing a basic configuration of a PLL circuit. A voltage-controlled oscillator (hereinafter, referred to as VCO) whose oscillation frequency is varied according to the magnitude of a control voltage signal Vc, and a VCO
Phase comparator 2 for detecting the phase difference between the output of 1 and the reference signal
And a loop filter 3 which receives a detection signal from the phase comparator 2 and inputs a control voltage signal to the VCO 1 so that the phase difference between the output of the VCO 1 and the reference signal becomes a constant value.

As the phase comparator 2, a digital type phase frequency comparator is frequently used instead of an analog type phase comparator due to a wide capture range.

This type of phase frequency comparator, which is composed of logic circuits such as gate circuits and flip-flops, has a frequency comparison function of outputting a signal corresponding to the level of the frequency of one input signal with respect to the frequency of the other input signal. Therefore, even when the frequency Fr of the reference signal and the output frequency Fv of the output signal of the VCO1 are far apart, a detection signal can be obtained and the frequency of the VCO1
Fv can be pulled in the Fr direction.

<Problem to be Solved> However, in the digital type phase frequency comparator as described above, a dead zone due to the delay of the digital circuit is generated near the phase difference of 0 degree, and the loop gain near the lock is significantly reduced. is there.

In order to prevent this, there has been a PLL circuit in which the charging voltage of the loop filter 3 is constantly leaked so that the phase difference between the two signals is adjusted to a value away from the dead zone near 0 °. In the output of VCO1, the reference signal frequency
Fr sideband noise is strongly generated.

For this reason, at present, the width of the dead zone is narrowed by using an expensive phase frequency comparator composed of high-speed logic elements.

An object of the present invention is to provide a PLL circuit that solves this problem.

<Means for Solving the Problems> In order to solve the above problems, a PLL circuit according to the present invention includes: an oscillator having an oscillation frequency variable according to the magnitude of a control signal; and an output component signal of the oscillator and a reference signal. A first phase comparator of a phase comparison type for digitally detecting a frequency difference and a phase difference; and a second analog mixer type of a beat for detecting a frequency difference and a phase difference between the output component signal of the oscillator and the reference signal.
A phase comparator which receives a beat output of the second phase comparator and determines whether or not the beat frequency is greater than a predetermined frequency; and wherein the first phase comparator or the second phase A loop filter for receiving the detection output of the comparator and generating the control signal; and the first circuit when the determination circuit determines that the beat output of the second phase comparator is higher than the predetermined frequency.
A switching circuit for inputting the detection output of the phase comparator to the loop filter, and when the beat output is determined to be smaller than the predetermined frequency, inputting the detection output of the second phase comparator to the loop filter. It has.

<Operation> Therefore, when the frequency difference between the reference signal and the output component signal of the oscillator is equal to or higher than the predetermined frequency, the detection output of the first phase comparator causes the frequency of the output component signal of the oscillator to approach the reference signal. When the frequency difference between the reference signal and the output component signal of the oscillator becomes equal to or less than a predetermined frequency, the output signal of the oscillator is locked to the reference signal by the detection signal of the second phase comparator.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a PLL circuit according to one embodiment of the present invention.

The PLL circuit is a circuit for generating a local signal for the microwave receiver, 1K range of 3G _Hz to 5 g _Hz
It is configured to be variable in steps.

In FIG. 1, reference numeral 10 denotes a microwave oscillator,
Two control terminals 11a of the oscillator 11, by varying the current supplied to 11b, it is possible to continuously vary the oscillation frequency between the 3G _Hz ~5G _Hz.

One control terminal 11a is a terminal for sweeping the YIG oscillator 11 and can be varied over the entire oscillation frequency range, and the other control terminal 11b is a modulation terminal and can have a lower frequency range in a narrow range. .

Reference numerals 12 and 13 denote voltages for driving the YIG oscillator 11 with current.
The current converter 14 converts the control voltage Vd corresponding to the coarse adjustment data Fa from the frequency setting unit 55 described later into a voltage-current converter 13.
This is a DA converter that outputs to

The output of the YIG oscillator 11 is input to the frequency converter 15.

Frequency converter 15, an input signal, a mixer 16 and a low pass filter (hereinafter, referred to as LPF) in converting the frequency band of 30 to 40 m _Hz.

18, a local oscillation signal of a frequency corresponding to the first frequency data Fb from the frequency setting device 55, a local oscillation signal generator for outputting to the mixer 16, the input signal of 3 to 5 g _Hz, 2.9
The local oscillation signal of 7～4.97G _Hz is configured to be output at 10M _Hz steps (lower heterodyne).

20 is a reference signal generator for outputting a second reference signal of 30 to 40 m _Hz corresponding to the frequency data Fc from frequency setter 55 in 1K _Hz steps.

The output signal from the frequency converter 15 (the output component signal of the YIG oscillator 11) and the reference signal from the reference signal generator 20 are both passed through the 1/8 frequency dividers 21 and 22 to perform the first phase comparison. Input to the container 23.

The first phase comparator 23 is a phase frequency comparison type digital phase comparator typified by Motorola's MC4044 type integrated circuit. The first phase comparator 23 is inputted to a V terminal with respect to the phase of a pulse inputted to an R terminal. When the phase of the pulse is advanced, an "L" level pulse having a width corresponding to the phase difference is output from the D output terminal, and when the pulse is delayed, an "L" level pulse having a width corresponding to the phase difference is output. "A level pulse is output from the U output terminal. When the frequency of the pulse input to the V terminal is higher than the frequency of the pulse input to the R terminal, the D output terminal is fixed at “L” level until the phase comparison state is reached, and conversely. When low, the U output terminal is fixed at "L" level.

Reference numeral 24 denotes an analog mixer-type second phase comparator that detects a frequency difference and a phase difference between the reference signal and the output signal from the frequency converter 15.

This second phase comparator 24 is a double balanced mixer (DRM)
And outputs only the sum and difference components of the two input signals. The average output is zero when the input signal is input with a phase difference of 90 degrees, and the average output of the phase difference of 0 degrees. Is + maximum, and the average output of the -180 degree phase difference is -maximum.

Reference numeral 25 denotes an LPF for removing a high-frequency component from the output of the second phase comparator 24 and passing a signal component having a frequency equal to or lower than the frequency Fp.

A frequency comparator 27 determines whether or not the frequency of the signal component (beat component) of the difference passed from the output of the second phase comparator 24 by the LPF 28 is higher than a predetermined frequency Fm (Fm <Fp).
This is a judgment circuit for judging by 29.

The frequency comparator 29 is configured, for example, as shown in FIG.

That is, the beat signal is amplified by the amplifier 30 and the waveform shaping circuit is used.
Re-trigger one-shot multi-circuit 32
Trigger.

The pulse width of the one-shot multi-circuit 32 is set to a period Tm of a predetermined frequency Fm, and its output is input to the D terminal of a flip-flop 33 that uses the output of the waveform shaping circuit 31 as a clock.

Therefore, if the cycle of the input beat signal is shorter than Tm, that is, if the frequency of the beat signal is higher than Fm,
The output of the flip-flop 33 remains at “H” level,
Conversely, when the period of the beat signal is longer than Tm, that is, when the frequency of the beat signal is lower than Fm, the output of the flip-flop 33 remains at the “L” level.

The output of the frequency comparator 29 is slightly delayed by a delay circuit 35 as shown in FIG.

When the output of the determination circuit 27 is at the “H” level, the switching circuit 40 outputs the output of the first phase comparator 23 inverted by the inverters 41 and 42 via the AND circuits 43 and 44 to a loop filter 50 described later. When the output of the decision circuit 27 is at the "L" level, the switch 46 is turned on with the "H" level output obtained by inverting the decision output by the inverter 45, and the output of the amplifier 26 (the second phase comparison The phase difference signal from the filter 24 is connected to the loop filter 50.

The loop filter 50 is connected to the AND circuits 43 and 44 of the switching circuit 40.
The switches 51, 52 and 46 for the charge pump which are turned on by the "H" level output from the resistor R1, R2, R3 each having one end connected thereto, and the resistor R4 and the capacitor C connected in series, This is a luxury type filter.

Positive and negative power supplies (± B) are supplied to the other ends of the charge pump switches 51 and 52, and while the output of the AND circuit 43 is at the “H” level, capacitors are supplied from the power supply + B via R1 and R4. C is charged, and while the output of the AND circuit 44 is at the "H" level, the capacitor C is connected to the power supply -B via the resistors R2 and R4.
(Usually R1 = R2).

While the switch 46 is on, the output of the amplifier 26 charges and discharges the capacitor C via the resistors R3 and R4.

The output of the loop filter 50 is input to the microwave oscillating unit 10 as the control voltage Vc.

Note that the frequency setting unit 55 is configured to input 10M of the input frequency data Fs.
A first frequency data Fb obtained by subtracting 3 from the _Hz of positions above the upper data, the second frequency data Fc obtained by adding 30000 to the lower data from 1K _Hz to 10M _Hz, respectively local oscillator signal generator 18 and sends to the reference signal generator 20, the free-running frequency of the YIG oscillator 11 for switching the frequency data Fb, Fb × 10M _Hz
The coarse adjustment data Fa for slightly higher output is output to the DA converter 14 of the microwave oscillating unit 10 to shorten the time until locking and prevent the control direction of the loop from being reversed.

 Next, the operation of the PLL circuit will be described.

As frequency data Fs for frequency setting device 55, for example, when 3456.789M _Hz is set, the first frequency data F
"342" (= 345-3) is set as b in the local oscillator signal generator 18, and "36789" (30000 + 6789) is set as the second frequency Fc.
Is set in the reference signal generator 20, and the coarse adjustment data Fa in which the free-running frequency of the YIG oscillator 11 is close to, for example, 3500 MHz higher than the set frequency is set for the DA converter 14 of the microwave oscillation unit 10. Is done.

With this setting, the output frequency of the YIG oscillator 11 becomes the third frequency.
Almost 3500M _Hz next to the switching time (set time)-to as shown in the figure, from the frequency conversion unit 15, is output signal of approximately 80M _Hz.

Therefore, in the 1/8 frequency divider 21, 22 and the second phase comparator 24, so that the reference signal 36.789M _Hz, the signal of approximately 80M _Hz is input.

For this reason, the D output of the first phase comparator 23 that has received the frequency-divided output having a frequency distant from the 1/8 frequency dividers 21 and 22 becomes "L" level.

Further, the determination circuit 27 receives a beat component (approximately 40 MHz) having a frequency higher than the predetermined frequency Fm from the second phase comparator 24.
Is at the “H” level, the “H” level of the AND circuit 44
The switch 52 of the loop filter 50 is turned on by the level output.

For this reason, the charging voltage of the loop filter 50, that is, the control voltage Vc decreases, and the oscillation frequency of the YIG oscillator 11 decreases as shown in FIG.

As the oscillation frequency decreases, the output frequency from the frequency conversion unit 15 also decreases, and when the frequency difference from the reference signal becomes equal to or less than the predetermined frequency Fm, the output of the determination circuit 27 becomes "L" level with a slight delay. At (t ₁ ), the output of the second phase comparator 24 is connected to the loop filter 50.

As a result, the retraction is performed by the phase comparison output of the second phase comparator 24, t ₂ times the oscillation frequency is locked to 3456.678M _Hz.

This locked state is maintained by the loop control based on the output of the second phase comparator 24 until the frequency data is switched. However, since there is no dead zone in the analog mixer type phase comparator, the loop in the locked state is maintained. There is no decrease in gain, and the signal purity of the oscillation output is extremely high.

The switching delay in the determination circuit 27 is a delay for preventing the oscillation frequency from jumping out of the pull-in range (± Fm) of the oscillation frequency caused by the loop response not catching up with the switching of the phase comparator. The switching of the phase comparator is performed after the frequency completely enters or exits the pull-in range (± Fm).

From this state, t ₃ at the time of frequency data Fs is 4000.000M _Hz
, The first frequency data Fb becomes “397” and the second
Is "30000", and the coarse adjustment data Fa is
Switched to the value for the free-running frequency of the YIG oscillator 11 is substantially 4100M _Hz.

This switching, the oscillation frequency of the YIG oscillator 11 is raised to the vicinity of 4100M _Hz as shown in FIG. 3, the retraction by the same output of the first phase comparator 23, the second phase comparator 24 It switched to pull by the output, to lock the frequency equal 4000.000M _Hz to frequency data Fs.

The switching of the phase comparator is performed by a second phase comparator.
This is performed when there is a frequency deviation larger than the loop pull-in range (± Fm) by 24, and the same switching operation is performed even when only the frequency of the reference signal is changed by Fm or more.

<Another embodiment of the present invention> In the above embodiment, the reference signal and the output from the frequency converter 15 (the output component signal of the YIG oscillator 11) are divided by a 1/8 frequency divider.
21 and 22 had been entered by dividing the first phase comparator 23, the frequency of the reference signal is low (several M _Hz stand) or, in the case of using a high-speed phase comparator, a frequency divider Can be omitted and entered directly.

Further, in the above embodiment, the YI
Although the output of the G oscillator 11 is frequency-converted (heterodyne-converted), the output of the oscillator may be directly input to the first and second phase comparators, or may be input via a frequency divider. You may do so.

In the above embodiment, the MC40 is used as the first phase comparator.
Although the 44 type phase comparator is used, a comparator of another configuration, for example, a MOS type phase frequency comparator with a charge pump may be used as long as it is a digital type phase frequency comparator.

<Effect of the Present Invention> As described above, the PLL circuit of the present invention is a first phase comparator of a phase frequency comparator capable of digitally detecting a wide range of frequency difference and phase difference, and sets the oscillation frequency of the oscillator to a predetermined value. After the signal is pulled into the frequency band, the oscillation signal is locked to the reference signal by loop control using the output of the analog mixer-type second phase comparator, so that a wide pull-in range and a loop gain without a dead band are provided. And a high-purity oscillation output can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing a main part of one embodiment, and FIG. 3 is a diagram showing a change in oscillation frequency in one embodiment. FIG. 4 is a diagram showing a basic configuration of a PLL circuit. 10 microwave oscillator, 11 YIG oscillator, 15 frequency converter, 18 local signal generator, 20 reference signal generator, 21, 22 1/8 frequency divider, 23 ... First phase comparator, 24... Second phase comparator, 27... Decision circuit, 40.
Switching circuit, 50: Loop filter, 55: Frequency setting device.

Claims (1)

(57) [Claims] An oscillator whose oscillation frequency is varied in accordance with the magnitude of a control signal; and a phase comparison type first phase comparison for digitally detecting a frequency difference and a phase difference between an output component signal of the oscillator and a reference signal. A second phase comparator of an analog mixer type for beat-detecting a frequency difference and a phase difference between an output component signal of the oscillator and the reference signal, and receiving a beat output of the second phase comparator; A determining circuit for determining whether or not the frequency is higher than a predetermined frequency; a loop filter for receiving the detection output of the first phase comparator or the second phase comparator and generating the control signal; When it is determined that the beat output of the second phase comparator is higher than the predetermined frequency, the detection output of the first phase comparator is input to the loop filter, and the beat output is There when it is determined to be smaller than the predetermined frequency, PLL circuit, characterized in that the detection output of said second phase comparator and a switching circuit for input to said loop filter.