JP2907284B1 - Spread spectrum signal demodulation circuit - Google Patents

Abstract

Kind Code: A1 The present invention relates to a spread spectrum signal demodulation circuit used in spread spectrum communication, and realizes high-speed spread code synchronization and carrier synchronization at low S / N and in the presence of a carrier frequency error. . SOLUTION: Among output signals of passive correlation means 3, 4,
First cyclic integration means 5 and 6 for cyclically integrating an unmodulated signal in an L symbol section for establishing initial synchronization, envelope detection means 7 for detecting an envelope of an output signal of the first cyclic integration means, and an envelope Second cyclic integration means 8 for cyclically integrating the output signal of the detection means, position detection means 9 for detecting a position at which the output signal of the second cyclic integration means indicates a predetermined value, and first cyclic integration in the L symbol section. Means are M where L> M
Times, and the second cyclic integration means outputs (L /
A control means 15 for performing M) integration operations and performing an intermittent operation at M symbol periods.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal demodulation circuit used in spread spectrum communication, and more particularly to a synchronization control method for establishing initial synchronization in an L (L is an integer) symbol section of a received signal.

[0002]

2. Description of the Related Art Spread spectrum communication is a communication system in which a frequency band of an information signal is spread by a high-speed spreading code and transmitted. The spread spectrum communication has features such as high confidentiality, hardly causing interference and hardly receiving interference. Have. The spread spectrum signal demodulation circuit is a circuit that detects (despreads) a correlation value between a received signal and a spread code synchronized with the received signal and reproduces (demodulates) an information signal. Among them, a spread spectrum signal demodulation circuit using a passive correlator such as a matched filter as a despreading circuit is known to realize high-speed synchronization establishment (for example,
Reference "Spread Spectrum Communication Equipment for Satellite Communication Performing Data Demodulation Directly with Matched Filter", Hamamoto et al .: IEICE Transactions B, Vol.J69-B, No.11, pp.1540-1547).

[0003] When demodulating a spread spectrum signal, the transmitting side transmits a signal for initial synchronization establishment in which a known signal is spread spectrum in an L symbol section for establishing initial synchronization, thereby realizing faster initial synchronization establishment. You. The signal for establishing initial synchronization includes a method using a non-modulated signal and a method using a signal modulated by a predetermined modulation pattern.

FIG. 6 shows a configuration example (conventional example 1) of a conventional spread spectrum signal demodulation circuit using a matched filter as a passive correlator. This spread spectrum signal demodulation circuit is a circuit that can be applied to both cases where the signal for establishing initial synchronization is a non-modulated signal and a modulated signal. 6, this spread spectrum signal demodulation circuit includes a quadrature detector 1, a complex multiplier 2, matched filters 3, 4
, An envelope detector 7, a cyclic integrator 8, a peak position detection circuit 9, samplers 10 and 11, and a carrier regenerator 14.
And a control circuit 20.

[0005] In the received signal input to the quadrature detector 1, the signal for establishing initial synchronization is either a non-modulated signal or a modulated signal. This received signal is converted into a complex baseband signal composed of an in-phase component and a quadrature component in the quadrature detector 1 and applied to one input of the complex multiplier 2. The complex multiplier 2 receives the reproduced carrier from the carrier regenerator 14 at the other input, and outputs complex baseband signals synchronized with the reproduced carrier to the matched filters 3 and 4.

[0006] The matched filters 3 and 4 are linear filters that use the time waveform of the spread code as an impulse response, and the output of the filter provides a correlation value between the received signal and the spread code every moment. Output signals of the matched filters 3 and 4 are applied to an envelope detector 7 and samplers 10 and 11. The envelope detector 7 detects the envelope by taking the sum of squares of the output signals of both the matched filters 3 and 4, and outputs the detected envelope to the cyclic integrator 8.

The cyclic integrator 8 includes an adder 25, a delay circuit 26, and a multiplier 27, for example, as shown in FIG. One input of the adder 25 is the output of the envelope detector 7, the other input is the output of the delay circuit 26, the output is the input of the delay circuit 26 via the multiplier 27, and The signal is sent to the detection circuit 9. Sampler 1
0 and 11 sample the outputs of the matched filters 3 and 4 at the timing of the peak position detected by the peak position detection circuit 9. Output signals from the samplers 10 and 11 become demodulated outputs and are output to the carrier regenerator 14.
The carrier regenerator 14 performs carrier regeneration from the output signals of the samplers 10 and 11 and applies the regenerated carrier to the other input of the complex multiplier 2.

[0008] The control circuit 20 controls the cyclic integrator 7, the peak position detection circuit 9, and the carrier regenerator 14, and establishes the synchronization of the spreading code and the carrier in the L symbol initial synchronization establishment section. A maintenance follow-up operation is performed.
Next, the operation of establishing synchronization will be described with reference to FIG. FIG.
As shown in (1), a conventional initial synchronization establishment section is composed of a period in which synchronization of spreading codes is established and a period in which carrier synchronization is established. FIG. 8 is an operation timing chart when the first 60 symbol sections of the received signal are used as the initial synchronization establishment section, of which 50 symbol sections are used to establish spreading code synchronization and 10 symbol sections thereafter are used to establish carrier synchronization.

Referring to FIG. 8, first, the operation in the section for establishing 50-symbol spread code synchronization will be described. Control circuit 2
0 is the leading position of the 50-symbol spread code synchronization establishment section, resets the delay circuit 26 and initializes the cyclic integrator 8. The multiplication constant A of the multiplier 27 of the cyclic integrator 8
Is A = 1.

[0010] Since the carrier of the received signal is unknown during the 50-symbol spread code synchronization establishment section, the carrier regenerator 14 converts the carrier signal having a fixed frequency and phase into a complex multiplier according to the instruction of the control circuit 20. 2 to the other input. The fixed carrier is naturally set to match the frequency and phase of the carrier on the transmitting side, but it is difficult to match exactly because it depends on the accuracy of the oscillator. Therefore, in the spread code synchronization establishment section, a frequency error and a phase error often exist between the reproduced carrier output from the carrier regenerator 14 and the transmitting carrier. For this reason, the output amplitude of the complex multiplier 2 is biased to either in-phase / quadrature components or fluctuates between in-phase / quadrature.

The matched filters 3 and 4 output a signal having a peak when the spread code of the matched filter and the received signal (output signal of the complex multiplier 2) are synchronized. In this spread code synchronization establishment section, the peak positions of the output amplitudes of the matched filters 3 and 4 are detected, and spread code synchronization is established. However, like the output amplitude of the complex multiplier 2, the output amplitudes of the matched filters 3 and 4 are biased or fluctuated to either in-phase or quadrature components. The speed of this deviation or fluctuation is not so large when the received signal is a non-modulated signal, but when the received signal is a modulated signal,
Since it changes at a high speed for each symbol, smoothing by the subsequent cyclic integrator 8 becomes difficult.

Therefore, in order to prevent such influences, the signal is output once to the envelope detector 7 to detect the envelope waveform. Since the envelope waveform is a constant waveform irrelevant to the frequency error and the phase error, the envelope waveform is applied to the cyclic integrator 8 to remove noise components, and then the peak position detection circuit 9 detects the peak position. . The cyclic integrator 8
As shown in FIG. 7, the input waveform (envelope waveform) and the output waveform of the delay circuit 26 are added by the adder 25, and the added waveform is added to the delay circuit 2 via the multiplier 27 where the multiplication constant A is 1.
6, and is fed back to the input side (adder 25). For this reason, waveforms that repeatedly appear at the input side of the adder 25 with a period equal to the delay time of the delay circuit 26 are gradually increased, and the other waveforms are smoothed.

Since the peak position of the output amplitude of the matched filters 3 and 4 repeats at the modulation symbol period, the output of the matched filters 3 and 4 is set by equalizing the delay time of the cyclic integrator 8 and the modulation symbol period. Noise components can be removed from the amplitude envelope waveform. As shown in FIG. 8, under the control of the control circuit 20, the cyclic integrator 8
Integration is performed continuously 0 times.

The peak position detecting circuit 9 detects the peak position of the output signal of the cyclic integrator 8 after integrating 50 times under the instruction of the control circuit 20, and outputs the detected signal to the samplers 10 and 11. The samplers 10 and 11 start sampling the output signals of the matched filters 3 and 4 at the detected peak positions. Thereby, the samplers 10, 11
, The peak value of the output (despread output) of the matched filters 3 and 4 is obtained.

The control circuit 20 sends samplers 10 and 11 to the carrier regenerator 14 at the end of the spread code synchronization establishment section.
The instruction to reproduce the carrier wave from the output signal is issued. As a result, the carrier regenerator 14 starts controlling the output carrier so as to cancel the carrier frequency error and the phase error included in the output signals of the samplers 10 and 11. The section required to cancel the carrier frequency error and the phase error is the carrier synchronization establishment section, and FIG. 8 uses a 10 symbol section. Thereafter, a tracking operation is performed using the output signals of the samplers 10 and 11 to maintain the synchronization of the established spreading code and carrier.

Next, FIG. 9 shows a configuration example (conventional example 2) of a conventional spread spectrum signal demodulation circuit using a matched filter as a passive correlator. This spread spectrum signal demodulation circuit is a circuit applied when the signal for establishing initial synchronization is a non-modulated signal. 9, this spread spectrum signal demodulation circuit is different from the circuit shown in FIG. 6 in that cyclic integrators 5 and 6 are provided between matched filters 3 and 4 and envelope detector 7, and cyclic integrators are provided. 8, the output of the envelope detector 7 is directly connected to the peak position detection circuit 9. The cyclic integrators 5 and 6 have the same configuration as that shown in FIG.

In the section where spread code synchronization is established, the output amplitude of the complex multiplier 2 has a bias or a fluctuation, but at least the speed of the fluctuation depends on the degree of frequency error since the received signal is an unmodulated signal. However, it does not become so large, and the matched filters 3 and 4 periodically output signals having similar peaks. The cyclic integrators 5 and 6 are matched filters 3 and
Cyclic integration is performed on each of the output signals having a peak of 4, that is, the noise component is removed, and the output is output to the envelope detector 7. The peak position detection circuit 9 detects a peak position from the envelope waveform detected by the envelope detector 7 and outputs the peak position to the samplers 10 and 11. Therefore, the circuit shown in FIG. 9 can perform the same operation in the time chart shown in FIG.

[0018]

A received signal in wireless communication is a signal in which a desired signal and uncorrelated thermal noise are superimposed thereon. If such a superimposed signal is smoothed by cyclic integration, Every time the number of integrations doubles, S /
N is known to be improved by 3 dB. But,
In the circuit shown in FIG. 6, since a non-linear operation (square operation) is performed when detecting the envelope waveform, the noise component is no longer uncorrelated with the desired signal. For this reason, the S / N improvement amount per integration number decreases, and it is necessary to increase the integration number in order to obtain a sufficient S / N improvement amount. Therefore, there is no significant problem in use in a communication line having a relatively good S / N, but an extremely long integration time is required under low S / N conditions such as a satellite communication line, and it is difficult to establish high-speed synchronization of spread codes. It is.

In the circuit shown in FIG. 6, if the number of integrations is reduced for high-speed synchronization, it becomes difficult to distinguish between the peak position of the output amplitude of the matched filter and noise, and the probability of erroneous synchronization increases. . In this regard, the configuration shown in FIG. 9 is a case where the received signal is an unmodulated signal and the frequency error is small. However, as shown in FIG. 9, the cyclic integration is performed on each of the in-phase side and the quadrature side before the envelope detection. If the peak position is detected from the envelope waveform of the signal after the cyclic integration, the ideal S / N
As a result, the peak position of the output amplitude of the matched filter can be easily distinguished from noise.

However, in the configuration shown in FIG. 9, since the amplitude of each of the in-phase and quadrature components fluctuates in a sinusoidal manner within the integration time due to the presence of the carrier frequency error, the peak amplitude after integration is attenuated by the cyclic integration. The peak amplitude is not significantly affected and the attenuation is small if “carrier frequency error × integration time” is small, but the attenuation increases as the value increases.

Since the carrier frequency error depends on the accuracy of the oscillators on the transmitting and receiving sides, it is practically difficult to set the carrier frequency error to zero during the spread code synchronization establishment period. Therefore, in the configuration shown in FIG. 9, if the integration time is increased to enhance the S / N improvement effect in the presence of a certain carrier frequency error, the probability of erroneous synchronization is greatly deteriorated due to the attenuation of the peak amplitude.

In the conventional configuration shown in FIGS. 6 and 9,
Since the peak value of the despread signal cannot be obtained until the spread code synchronization is established, it is impossible to perform carrier wave synchronization during that time. Therefore, a spreading code synchronization establishing section and a carrier wave synchronization establishing section are each required as the initial synchronization establishing section, and the time required for the initial synchronization is further increased. SUMMARY OF THE INVENTION An object of the present invention is to provide a spread spectrum signal demodulation circuit capable of realizing high-speed spread code synchronization and carrier wave synchronization in a situation where a low S / N and a carrier frequency error exist.

[0023]

According to a first aspect of the present invention, there is provided a spread spectrum signal demodulation circuit for converting a received signal, which has been spread spectrum by a spread code, with a reference carrier signal, Passive correlation means for despreading an output signal; first cyclic integration means for cyclically integrating a non-modulated signal in an L (L is an integer) symbol section for establishing initial synchronization among output signals of the passive correlation means; Envelope detection means for detecting an envelope of an output signal of the first cyclic integration means, second cyclic integration means for cyclically integrating the output signal of the envelope detection means, and a maximum of the output signal of the second cyclic integration means. A position detecting means for detecting a position indicating a value or a predetermined value, and sampling an output signal of the passive correlation means at a position detected by the position detecting means, and outputting a demodulated signal. In one symbol unit and an L symbol section for establishing the initial synchronization of the reception signal, the first cyclic integration unit performs M integration operations where L> M (M is an integer), or Is set, and the second cyclic integration means is caused to perform (L / M) integration operations, or (L / M).
And a control means for setting a time constant for performing an operation corresponding to M) times of integration operations and performing an intermittent operation at M symbol periods.

According to a second aspect of the present invention, there is provided a spread spectrum signal demodulation circuit for converting a received signal, which is spread by a spread code, into a frequency using a reference carrier signal, and despreading an output signal of the conversion means. Passive correlation means, modulation signal removal means for removing a modulation signal included in a received signal in an L (L is an integer) symbol section for establishing initial synchronization among output signals of the passive correlation means, and modulation signal removal means First cyclic integration means for cyclically integrating the output signal of the above, envelope detection means for detecting the envelope of the output signal of the first cyclic integration means, and second cyclic integration for cyclically integrating the output signal of the envelope detection means. Integrating means, position detecting means for detecting the position of the maximum value or a predetermined value of the output signal of the second cyclic integration means, and detecting the position of the output signal of the passive correlation means. The first sampling means for sampling at the position detected by the means and outputting the demodulated signal, and the first cyclic integration means in the L symbol section for establishing the initial synchronization of the received signal, L> M (M is an integer) Is performed or a time constant corresponding to the M times of the integration operation is performed, and the second integration means (L
/ M) times or a time constant for performing an operation equivalent to (L / M) times of integration is set, and M
Control means for performing an intermittent operation at a symbol cycle.

According to a third aspect of the present invention, in the spread spectrum signal demodulation circuit according to the first or second aspect, the carrier is reproduced from the output signal of the first sampling means. A carrier recovery unit that outputs the reference carrier signal; and a second sampling unit that samples an output signal of the first cyclic integration unit at a position of a predetermined value detected by the position detection unit and outputs the signal to the carrier recovery unit. The control unit is characterized in that the control unit causes the carrier recovery unit to take in the output signal of the second sampling unit as an initial value of the carrier recovery in response to the end of the L symbol section for establishing the initial synchronization.

(Operation) According to the first aspect of the present invention, the signal that is spread and transmitted in the initial synchronization establishment section of the L symbol is an unmodulated signal. In this initial synchronization establishment section, since the transmission carrier is unknown, a reference carrier having a fixed frequency and phase is used.
Therefore, in the initial synchronization establishment section, a carrier frequency error exists, and the passive correlation means outputs a signal whose peak value amplitude gradually changes according to the degree of the frequency error.
However, since the received signal is an unmodulated signal, the output signal of the passive correlation means can be subjected to cyclic integration before envelope detection. This frequency error can be assumed in advance as an amount depending on the accuracy of the oscillator on the transmitting side and the oscillator on the receiving side.

Therefore, the control means determines the number of times that the first cyclic integration means cyclically integrates the L-symbol unmodulated received signal before detecting the envelope, so that the attenuation of the peak amplitude due to the carrier frequency error is suppressed. L is set to a relatively small value M equal to or less than L such that L> M, and the ratio of the integration time to the reciprocal of the assumed carrier frequency error is set short. Thus, in the first cyclic integration means, an ideal S / N improvement effect can be obtained while suppressing the attenuation of the peak amplitude due to the carrier frequency error.

From the output signal of the first cyclic integration means, the envelope waveform is detected by the envelope detection means and input to the second cyclic integration means. Since the second cyclic integration means is provided after the envelope detection, the cyclic integration can be performed without being affected by the carrier frequency error. Further, the second cyclic integration means has a small S / N improvement amount per integration number, but the input signal is a signal whose S / N has already been improved by the first cyclic integration means.

Therefore, the control means sets the number of integrations in the second cyclic integration means to be as small as (L / M) times, and sets an M symbol period so that only signals after the completion of the M integrations are input. Intermittent operation is performed. Thereby, the S / N improvement effect is maximized. In short, according to the first aspect of the present invention, the S / N is efficiently improved in a short time while suppressing the attenuation of the peak amplitude by the first cyclic integration means in a situation where a frequency error exists, and the S / N is improved. By detecting the envelope of the obtained signal and performing intermittent cyclic integration by the second cyclic integration means, a large S / N improvement can be obtained in a short time as a whole.

Therefore, according to the first aspect of the present invention, in a situation where a frequency error exists, high-speed spread code synchronization and a low false synchronization probability of a spread spectrum signal received at a low S / N are simultaneously realized. Is done. Specifically, if the period of spread code synchronization establishment is the same as in the past, the probability of false synchronization can be reduced, and if the probability of false synchronization is approximately the same as in the past, the period of spread code synchronization establishment can be shortened. it can.

According to the second aspect of the present invention, since the signal that is spread and transmitted in the initial synchronization establishment section of the L symbol is a modulated signal, the output signal of the passive correlation means cannot be cyclically integrated as it is. . Therefore, the output signal of the passive correlation unit is provided to the modulation signal removal unit, and the modulation signal included in the received signal in the L symbol section for establishing the initial synchronization is removed to obtain a non-modulated signal, which is input to the first cyclic integration unit.

In short, the invention according to claim 2 is different from the invention according to claim 1 in that the signal in the initial synchronization establishment section is a modulation signal, but is a non-modulated signal. The modulation signal is removed from the signal to give a non-modulated signal to the first cyclic integration means. Thereafter, the configuration is the same as that of the first aspect.

Therefore, as in the case of the first aspect of the present invention, a large S / N improvement can be obtained in a short time as a whole in a situation where a frequency error exists.
High-speed spread code synchronization and a low false synchronization probability for a spread spectrum signal received at a low S / N are simultaneously realized.
Specifically, if the period of spread code synchronization establishment is the same as in the past, the probability of false synchronization can be reduced, and if the probability of false synchronization is approximately the same as in the past, the period of spread code synchronization establishment can be shortened. it can.

According to a third aspect of the present invention, in the first or second aspect of the invention, the input signal of the first cyclic integration means in the initial synchronization establishment section is a signal after despreading. It is an unmodulated signal. Therefore, at the end of the L symbol section, the first cyclic integration means has the result of smoothing the unmodulated signal for the immediately preceding M symbols, that is, the carrier. Therefore, the control means causes the carrier recovery means to take in the output signal of the second sampling means as the initial value of the carrier recovery in response to the end of the L symbol section for establishing the initial synchronization.

Thus, the carrier recovery means can perform carrier recovery using the integration result of the first cyclic integration means as an initial value,
Since the reproduced carrier, which is the reference carrier signal, is generated immediately after the spread code synchronization is established, the carrier synchronization can be quickly established without requiring the conventional carrier synchronization establishment section.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration example of the first embodiment (an embodiment corresponding to the first and third aspects of the present invention). The spread spectrum signal demodulation circuit of this embodiment is configured to convert a received signal into a complex baseband and process it, as in the conventional example (FIGS. 6 and 9). The same components as in the conventional example (FIGS. 6 and 9) are denoted by the same reference numerals and names. Hereinafter, the portion according to this embodiment will be mainly described.

The spread spectrum signal demodulating circuit according to the first embodiment is applied to a spread spectrum communication system in which an unmodulated signal is spread and transmitted in an initial synchronization establishment section of L (L is an integer) symbols. It is. In the first embodiment, as shown in FIG. 1, the cyclic integrator 8 is provided between the envelope detector 7 and the peak detection circuit 9 in the configuration shown in FIG. 6 which sample the output signal of the sampler 12, 1
3, samplers 10 to 13 are both operated by the output signal of the peak position detection circuit 9 and output to the carrier recovery circuit 14.

Each of the cyclic integrators 5, 6, and 8 has the same configuration as that shown in the conventional example (FIG. 7), but in this embodiment, the control circuit 15 uses the control circuit 15 shown in FIG. It is set to operate in the mode shown in b). FIG. 3A shows a case where the cyclic integrators 5, 6, and 8 operate with a predetermined number of integrations, and FIG. 3B shows a case where they operate with a predetermined time constant.

Specifically, the cyclic integrators 5, 6, and 8 are set as follows. First, when the cyclic integrators 5 and 6 operate with a predetermined number of integrations, the control circuit 15 sets the multiplication constant A of the multiplier 27 to a value of 1 (FIG. 3A), and sets the initial synchronization. In the L symbol section to be established, the delay circuit 26 is reset at a cycle of a value M where L> M (M is an integer), and the cyclic integrators 5 and 6 perform M integration operations in each cycle of M symbols.

When the cyclic integrators 5 and 6 operate with a predetermined time constant, the control circuit 15 sets the cyclic integrators 5 and 6 to perform an operation corresponding to M integration operations in the L symbol section. Multiplier 2 so that it has a time constant (1 / (1−a))
The multiplication constant A of 7 is set to a constant a smaller than the value 1 (FIG. 3B). In this case, since the whole operates as a kind of filter, an integration operation corresponding to a predetermined number of integrations is performed without resetting the delay circuit 26.

Next, when the cyclic integrator 8 performs the integration operation (L / M) times in the L symbol section, the control circuit 15 sets the multiplication constant A of the multiplier 27 to a value 1 and (FIG. 3A), the delay circuit 26 is reset at the beginning of the L symbol section, and one (L / M) integration operation is performed within the M symbol period, and during the remaining period, The operation is stopped and the total operation (L / M) is performed.

When the cyclic integrator 8 performs an operation corresponding to (L / M) integration operations with a predetermined time constant in the L symbol section, the control circuit 15 determines that the cyclic integrator 8 , The multiplier 2 so as to have a time constant (1 / (1−a)).
The multiplication constant A of 7 is set to a constant a smaller than the value 1 (FIG. 3B). Then, the control circuit 15 operates such that the cyclic integrator 8 performs an operation corresponding to one (L / M) integration operation within the period of M symbols and stops during the remaining period.

The correspondence between the above configuration and the first and third aspects is as follows. The whole of the quadrature detector 1 and the complex multiplier 2 corresponds to the conversion means. Matched filters 3 and 4 correspond to the passive correlation means. The cyclic integrators 5 and 6 correspond to the first cyclic integration means. The envelope detector 7 corresponds to the envelope detector. The cyclic integrator 8 corresponds to the second cyclic integration means. The peak position detecting circuit 9 corresponds to the position detecting means. Samplers 10 and 11 correspond to the first sampling means. Samplers 12 and 13 correspond to the second sampling means. The carrier regeneration unit 14 corresponds to the carrier regeneration unit. The control means corresponds to the control means. The reproduced carrier signal reproduced by the carrier regenerator 14 corresponds to the reference carrier signal.

Next, the operation of the portion according to the first embodiment will be mainly described with reference to FIGS. FIG.
6 is an operation timing chart of the embodiment. In FIG. 2, the initial synchronization establishment section of L symbols is 50 symbols. In the cyclic integrators 5, 6, the number of integrations M is 10, and is initialized every 10 symbols. In addition, the cyclic integrator 8 has an integration count (L / M) of five, is initialized at the beginning of the L symbol section, and performs one integration operation in each cycle of every ten symbols. Intermittently to stop during the period.

That is, the operation shown in FIG. 2 shows a case where the cyclic integrators 5, 6, and 8 are controlled in the manner shown in FIG. It should be noted that this initial synchronization establishment section corresponds to a conventional spread code synchronization establishment section, and there is no conventional section for establishing carrier synchronization. The received signal in the initial synchronization establishment section is a signal in which an unmodulated signal is spread and transmitted. As described above, the frequency of the transmission carrier is unknown, and the carrier regenerator 14 supplies a carrier signal having a fixed frequency and phase to the complex multiplier 2 according to an instruction from the control circuit 15. Therefore, in the initial synchronization establishment section, a carrier frequency error exists, and the matched filters 3 and 4 generate signals whose peak value amplitude fluctuates according to the degree of the frequency error by the samplers 10 and 11 and the cyclic integrators 5 and 5. 6 and output.

In the cyclic integrators 5 and 6, as shown in FIG. 2, the integration operation is performed ten times during the period of 10 symbols, and the integration result is represented by the envelope detector 7 and the samplers 12, 13.
And is initialized just before the next integration starts. As described above, the cyclic integrators 5 and 6 repeatedly perform integration every 10 symbols in the initial synchronization establishment section of 50 symbols.

In the initial synchronization establishment section, a carrier frequency error exists, but the number of cyclic integrations is set to a relatively small value of 50 symbols or less so that the ratio of the integration time to the reciprocal of the assumed carrier frequency error is set short. Value "10
, The cyclic integrators 5 and 6 can effectively perform noise removal while suppressing attenuation of peak amplitude due to carrier frequency error, and obtain an ideal S / N improvement effect. Can be

The envelope detector 7 detects the envelope of each integration cycle from the sum of squares of the integration results on the in-phase side and the quadrature side, respectively.
Each is output to the cyclic integrator 8. The cyclic integrator 8 includes:
Only the signal after the completion of the ten integrations is input. Therefore, as shown in FIG. 2, the cyclic integrator 8 performs the integration operation once at the end of the ten integrations in each of ten symbol sections and outputs the integration result to the peak position detection circuit 9, and the remaining period is An intermittent operation of stopping the operation is performed. In the cyclic integrator 8, the signal having already improved S / N is cyclically integrated a small number of times without being affected by the carrier frequency error, so that a desired S / N improvement amount can be easily obtained.

The peak position detection circuit 9 receives the integration operation timing signal of the cyclic integrator 8 from the control circuit 15, detects the peak position of each integration result of the cyclic integrator 8, and converts the peak position timing signal into the sampler 10 signal. To 13 are output. The samplers 10 and 11 sample the output signals of the matched filters 3 and 4 at the timing of the detected peak position and output the signals to the carrier regenerator 14. Also,
The samplers 12 and 13 sample the output signals of the cyclic integrators 5 and 6 at the timing of the detected peak position and output to the carrier regenerator 14.

In the initial synchronization establishing section, the carrier regenerator 14 samples the samplers 10 to 13 under the instruction of the control circuit 15.
Is ignored, and a carrier signal having a fixed frequency and phase is output. Here, the integration results of the cyclic integrators 5 and 6 sampled by the samplers 12 and 13 immediately after the end of the initial synchronization establishment section correspond to signals obtained by smoothing the transmission carrier in the last 10 symbol sections of the initial synchronization establishment section.

Therefore, when the carrier regenerator 14 receives the end notification of the initial synchronization establishment section from the control circuit 15, it takes in the output signals of the samplers 12 and 13 immediately after the end of the initial synchronization establishment section and uses it for the carrier reproduction. It is set as an initial value, and a carrier signal reproduced based on the initial value is output to the complex multiplier 2. Thereafter, the operation of reproducing and following the carrier in accordance with the output signals of the samplers 10 and 11 is performed without performing the operation of establishing carrier synchronization.

Next, FIG. 4 shows a simulation result of the S / N vs. false synchronization probability characteristic. In this simulation, a spreading code having a code length of 19 is used, and the speed of the spreading code is assumed to be 200 kHz. FIG. 4 also shows the characteristics of the conventional circuit shown in FIG. 7 (conventional 1) and the circuit shown in FIG. 9 for performing cyclic integration before envelope detection (conventional 2). It should be noted that the carrier frequency error 0 is practically impossible, but exists because it is a computer simulation.

The number of symbols L in the section required for establishing synchronization (however, in the prior art example, the spread code synchronization establishment section) is set to 50 symbols, which is the same as in this embodiment and the conventional example. As described above, in the conventional example 1, the probability of false synchronization is largely inferior to the others as a whole, and in the conventional example 2, the deterioration is large when there is a carrier frequency error. On the other hand, the circuit of the first embodiment has a required S / N of about 3.
It is excellent by 5 dB, and the deterioration due to the carrier frequency error can be almost ignored.

That is, in the circuit of the first embodiment, if the period of spread code synchronization establishment is the same as that of the related art under the condition that a carrier frequency error exists, the probability of false synchronization can be reduced, and It has been shown that if the probability is the same as the conventional one, the period of establishing the spread code synchronization can be shortened. next,
FIG. 5 is a configuration example of the second embodiment (an embodiment corresponding to claims 2 and 3). The spread spectrum signal demodulation circuit according to the second embodiment is applied to a spread spectrum communication system in which a modulated signal is spread and transmitted in an initial synchronization establishment section of L (L is an integer) symbols. This modulation signal is a signal modulated by a predetermined modulation pattern.

In the second embodiment, as shown in FIG. 5, a complex multiplier 16 is provided between the matched filters 3 and 4 and the cyclic integrators 5 and 6 in FIG. 16 is configured to multiply the output of the matched filters 3 and 4 by the modulation pattern input from the outside. Other configurations are the same as those of the first embodiment shown in FIG. This complex multiplier 16 corresponds to the modulated signal removing means in claim 2. Other correspondences are the same as in the first embodiment.

In the second embodiment, the received signal in the section for establishing the initial synchronization of L symbols is a signal obtained by spreading the spectrum of the modulated signal. Therefore, since the output signals of the matched filters 3 and 4 cannot be directly cyclically integrated, the complex multiplier 16 multiplies the output signals of the matched filters 3 and 4 by the complex conjugate number of the modulation pattern and removes the modulation component. That is, the signals are supplied to the cyclic integrators 5 and 6 as unmodulated signals.

Thereafter, similarly to the first embodiment, the operation is performed according to the operation time chart shown in FIG. 2, and the characteristics shown in FIG. 4 are obtained. In the two embodiments described above, a matched filter is used as a passive correlator, but a convolver or the like can be used instead. That is,
In the two embodiments, the example of the circuit that performs the demodulation operation in the baseband is shown.

In the detection of the position of the envelope, the actual peak position is detected. Alternatively, a predetermined position exceeding a predetermined threshold may be set as the peak position.

[0060]

As described above, according to the first and second aspects of the present invention, the signals spread and transmitted in the initial synchronization establishment section of L symbols are an unmodulated signal and a modulated signal, In a situation where an error exists, a high S / N improvement amount can be obtained in a short time as a whole,
A spread-spectrum signal demodulation circuit that enables high-speed spread code synchronization and a low probability of false synchronization of a spread-spectrum signal received at a low S / N is realized.

According to the third aspect of the present invention, the first and second aspects are provided.
Since the carrier synchronization can be established without requiring a special section for carrier synchronization, the time required for initial synchronization establishment is further reduced.

[Brief description of the drawings]

FIG. 1 is a configuration example of a first embodiment (an embodiment corresponding to claims 1 and 3).

FIG. 2 is an operation timing chart of the embodiment.

FIG. 3 is a configuration example of a cyclic integrator of the embodiment. (A)
Is a configuration in the case of operating at a predetermined integration number. (B)
Is a configuration in the case of operating with a predetermined time constant.

FIG. 4 is a diagram showing simulation results of S / N versus false synchronization probability characteristics (comparison of the present invention with Conventional 1 and Conventional 2).

FIG. 5 is a configuration example of a second embodiment (an embodiment corresponding to claims 2 and 3).

FIG. 6 is a configuration example of a conventional spread spectrum signal demodulation circuit (conventional 1).

FIG. 7 is a configuration example of a cyclic integrator.

FIG. 8 is an operation timing chart of a conventional example.

FIG. 9 is a configuration example of a conventional spread spectrum signal demodulation circuit (conventional 2).

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Quadrature detector 2 Complex multiplier 3, 4 Matched filter 5, 6, 8 Cyclic integrator 7 Envelope detector 9 Peak position detection circuit 10, 11, 12, 13 Sampler 14 Carrier regenerator 15 Control circuit 16 Complex multiplication vessel

Claims (3)

(57) [Claims] 1. A conversion unit for frequency-converting a received signal, which is spread by a spreading code, by a reference carrier signal, a passive correlation unit for despreading an output signal of the conversion unit, and an output signal of the passive correlation unit A first cyclic integration means for cyclically integrating an unmodulated signal in an L (L is an integer) symbol section for establishing initial synchronization; an envelope detection means for detecting an envelope of an output signal of the first cyclic integration means; A second cyclic integration means for cyclically integrating the output signal of the envelope detection means; a position detection means for detecting a position indicating a maximum value or a predetermined value of the output signal of the second cyclic integration means; First sampling means for sampling an output signal at a position detected by the position detection means and outputting a demodulated signal; and L symbols for establishing initial synchronization of the reception signal In the meantime, a time constant is set to cause the first cyclic integration means to perform M integration operations where L> M (M is an integer) or to perform an operation equivalent to the M integration operations; A time constant for causing the second cyclic integration means to perform (L / M) integration operations or to perform an operation corresponding to (L / M) integration operations is set, and at the M symbol period. A spread spectrum signal demodulation circuit, comprising: a control unit that operates intermittently. 2. A conversion means for frequency-converting a received signal spectrally spread by a spreading code with a reference carrier signal, a passive correlation means for despreading an output signal of the conversion means, and an output signal of the passive correlation means. Modulation signal removal means for removing a modulation signal included in a received signal in an L (L is an integer) symbol section for establishing initial synchronization; first cyclic integration means for cyclically integrating an output signal of the modulation signal removal means; An envelope detection means for detecting an envelope of an output signal of the first cyclic integration means; a second cyclic integration means for cyclically integrating the output signal of the envelope detection means; and an output signal of the second cyclic integration means. Position detecting means for detecting a position indicating a maximum value or a predetermined value, and sampling an output signal of the passive correlation means at a position of the predetermined value detected by the position detecting means, A first sampling means for outputting a tuning signal; and an M symbol operation where L> M (M is an integer) is performed by the first cyclic integration means in an L symbol section for establishing initial synchronization of the received signal. Or a time constant for performing an operation corresponding to the M integration operations is set, and the second cyclic integration means performs the (L / M) integration operations, or (L / M) A spread-spectrum signal demodulation circuit, comprising: a time constant for performing an operation corresponding to a single integration operation; and control means for performing an intermittent operation at a period of M symbols. 3. The spread spectrum signal demodulation circuit according to claim 1 or 2, wherein a carrier recovery unit that recovers a carrier from an output signal of the first sampling unit and outputs the reference carrier signal; Second sampling means for sampling an output signal of one cyclic integration means at a position detected by the position detection means and outputting the sampled signal to the carrier recovery means, wherein the control means terminates an L symbol section for establishing initial synchronization. A spread spectrum signal demodulation circuit characterized in that an output signal of the second sampling means is taken into the carrier recovery means as an initial value of carrier recovery in response to the signal.