JP2903175B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus used for image equipment such as an image scanner, a printer, and a copying machine, and more particularly, to an image processing apparatus that handles a color image.

[Conventional technology]

2. Description of the Related Art Conventionally, in an image processing apparatus that handles two-dimensional color image data, line-sequential data is frequently used in an image scanner, and plane-sequential data is frequently used in a printer or a copier as a data format to be handled. For example, R (red),
Taking as an example input data separated into three primary colors of G (green) and B (blue), FIG. 28 shows dot-sequential data, FIG. 29 shows line-sequential data, and FIG. 30 shows plane-sequential data. In the main scanning direction, all pixels have the same color data in the line-sequential data and plane-sequential data, and in the sub-scanning direction, dot-sequential data and plane-sequential data. Then, all lines become the same color data every two lines in line sequential data. As described above, the arrangement of data differs depending on the data format, and therefore, a specific image processing circuit is configured according to each data format.

[Problems to be solved by the invention]

In the conventional techniques as described above, the versatility of the image processing apparatus is poor, and it is difficult to connect to another apparatus having a different data format. For example, an image processing device used in an image scanner that uses line-sequential data as a data format cannot be used in a printer or copier that uses a lot of line-sequential data. I had to.

Therefore, an object of the present invention is to provide an image processing apparatus that can handle a plurality of data formats.

[Means for solving the problem]

In order to solve the above problems, in the present invention,
It has the following configuration.

2. Description of the Related Art In an image processing apparatus that performs arithmetic processing by focusing on a pixel area (area is N × M; N, M ≧ 1) of two-dimensional color image data, image processing is performed by focusing on input image data. When this is performed (hereinafter referred to as N + M = 2), the image processing apparatus of the present invention has the following configuration. That is, data storage means for storing either image data or coefficient data related to input pixel data, and a data format indicating whether the input pixel data is dot-sequential, line-sequential, or plane-sequential A control unit for generating an address signal corresponding to the data format of the input pixel data to the data storage unit based on a signal, a line signal indicating a data range of one line, and a clock signal synchronized with the input pixel data And subjecting the data of at least one color of the input pixel data to desired operation processing using data corresponding to the one color of the image data or coefficient data read from the data storage means, and outputting as output data. Together with one of the read data according to the desired arithmetic processing. The that data consisting of an arithmetic processing means for outputting as a memory data in the data storage device.

Even in the case of N + M = 2, in image processing that uses data or the like stored in advance in the data storage means for image processing and does not need to update the data, the image processing apparatus of the present invention uses Data storage means for storing previously inputted coefficient data; a data format signal indicating whether the input pixel data is dot-sequential, line-sequential, or plane-sequential; and a line signal indicating a data range of one line. Control means for generating an address signal corresponding to the data format of the input pixel data to the data storage means based on a clock signal synchronized with the input pixel data; and at least one color data of the input pixel data. Then, a desired arithmetic process is performed using the data corresponding to the one color of the coefficient data read from the data storage unit, and the result is output. Composed of a processing means.

On the other hand, when the arithmetic processing is performed using the data of the target pixel and the peripheral pixels of the target pixel in the pixel region of the two-dimensional color image data (hereinafter, referred to as N + M> 2), the present invention The configuration of the image processing device is as follows.

That is, data storage means for storing any one of image data or coefficient data related to the input pixel data, and the input pixel data is dot-sequential, line-sequential,
Alternatively, the input pixel data of the input pixel data is transmitted to the data storage unit based on a data format signal indicating which of the line-sequential mode, a line signal indicating a data range of one line, and a clock signal synchronized with the input pixel data. A control unit for generating an address signal corresponding to a data format; holding the image data or coefficient data and the input pixel data read from the data storage unit; And outputting data corresponding to at least one color of the input pixel data as operation data according to the type of operation processing, and corresponding to one of the data stored in the data storage means according to the operation processing. Circuit means for outputting data to be stored as memory data to the data storage means, and the sequential circuit Comprising a processing unit for the processing corresponding to the type of the operation processing in the operation data outputted from the stage.

[Action]

According to the configuration described above, the data to be read from the data storage unit is selected based on the data format based on the control unit, or the data is written to the data storage unit as needed, and the image data is further processed by the sequential circuit. By rearranging, arithmetic processing can be performed regardless of the data format.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

 FIG. 1 is a configuration block diagram of an embodiment of the present invention.

The control means 1 is provided for eliminating the influence on the calculation due to the difference in the data arrangement between the data formats, for example, the adverse effect of using data of another color at the time of the calculation between the same color data. , A counter, etc.
The format of the input image data is dot-sequential data, line-sequential data,
By inputting a data format signal 6 indicating any of the frame sequential data, a line signal 5 indicating an effective range of the data, and a clock 8 synchronized with the input data, a method of generating an address 9 according to the data arrangement of each color And outputs it to the data storage means 4. When the data storage means 4 is composed of a plurality of table data and a plurality of storage elements, a selection signal for selecting the table data and the storage element is output as necessary.

The control means 1 will be described with reference to FIG. 3. The control means 1 has a line counter 40 for counting line signals for three lines, an A input and a B input, and outputs one of the signals based on a signal input to a select terminal. It comprises a selector 41 for outputting, and an address counter 42 for counting addresses in synchronization with a clock.
A line signal 5 is input to an A input of the address counter 42 and an enable terminal E of the address counter 42, a Q output 43 of the line counter 40 is input to a B input of the selector 41, and a data format signal 6 is input to a select terminal S. Is entered.
The reset terminal R of the address counter 42 has a selector
The Y output 44 of 41 is connected, and the clock 8 is input to the clock terminal. With these configurations, the data format signal 6 selects which of the line signal 5 and the three-line signal 43, which is a line signal for three lines, is used as the reset signal 44 of the address counter 42, and the address of the data storage means 4 is selected. 9 is generated.

In the dot-sequential data and the frame-sequential data, the address 9 is incremented in synchronism with the clock input during the assertion of the line signal as shown in FIG. 4 using the line signal 5 as the reset signal 44 of the address counter 42, and the line signal is negated. Reset every time In the line-sequential data, the 3-line signal 43 is used as a reset signal 44 of the address counter 42, and is incremented in synchronization with the clock input during the assertion of the line signal as shown in FIG. 5, and is reset every time the 3-line signal becomes negated. Is done. In FIG. 3, the address counter 42 can be constituted by a counter, and the line counter 40 can be constituted by a counter and a gate.

In this example, the output from the address counter is used as it is as the address of the data storage means. However, when the data storage means 4 is composed of a plurality of table data and a plurality of storage elements, the upper bit of the address 9 is used. Can be used to select table data and storage elements.

The sequential circuit 2 transfers necessary pixel data to the arithmetic processing circuit in addition to the input data 7 when two or more pieces of pixel data are required for the operation, and also transfers the coefficients required for the operation when necessary. Is going. The sequential circuit is composed of a plurality of flip-flops (hereinafter referred to as FFs) and known ones such as selectors, selects an output of a specific FF according to the data format signal 6, and performs an arithmetic processing on the input data 7 or the memory data 10. Output to the circuit 3. The detailed configuration varies depending on the processing performed on the data, and will be described later in detail.

The arithmetic processing circuit 3 is composed of an adder, a divider and the like, and is a circuit that performs a desired operation on the operation data 11 from the sequential circuit 2 and outputs the result. Various types are used according to the operation to be performed.

The data storage means 4 can be composed of a storage element such as a RAM or a ROM, and stores image data or coefficients used for the operation.
Is output to the sequential circuit 2, and new data such as input data and operation results are stored as the memory data 10.

The arithmetic processing circuit 3 _{replaces the target} pixel Z _{i, j} with the Z
_Assuming that the operation is performed using _{i, j−1} and Z _{i−1, j} , the sequential circuit 2 receives the data 45 of the previous line from the storage means 4 as shown in FIG. And a shift register including four stages of FFs to which the input data 7 is input,
The output of the last stage FF49 and the second stage FF of the shift register
A selector 50 which receives the output of 48 as an input and outputs one based on a data format signal, and outputs the output of FF 46 to the pixel Z
_{i−1, j} , the output of the selector 50 is the pixel Z _{i, j−1} , and the output of the first stage FF47 of the shift register is the same color data of the pixel Z _{i, j} , for example, R _{i−1, j} , R _{i, j−1} and R _{i, j} are output to the arithmetic processing circuit. Further, the output of FF47 is stored in the storage means as data one line before. By inputting the data format signal 6 to the control means 1 and the sequential circuit 2, the control means 1 outputs the line signal 5 for dot-sequential data and plane-sequential data, and the three-line signal 43 for line-sequential data. Control means 1
Address 9 is output from the data storage means 4 and the memory data 10 corresponding to the pixel is stored as the data 45 one line before.
Written to FF46. In the sequential circuit 2, the data is sequentially shifted by the clock 8, and the data corresponding to Ri, j-1 is selected by the selector 50 as the data of FF49 for the dot sequential data and the data of FF48 for the line sequential data and the plane sequential data.

As a result, the data necessary for the operation are prepared. By inputting the data to the operation processing circuit 3, a desired operation is performed and output.

FIG. 7 is a block diagram showing the configuration of an embodiment of the present invention, which is an outline emphasizing circuit for performing a second derivative using a target pixel and peripheral pixel data.

The control means 1 outputs the address of the line memory according to the data format signal 6 as described above.

The sequential circuit 21 outputs the surrounding four pixels as data in addition to the input pixel data as described in detail later. As shown in FIG.
, A first shift register composed of four stages of FFs, a second shift register composed of seven stages of FFs receiving one line previous data 52 from the line memory 23, and input data 7 And a third shift register composed of four stages of FFs and an output of the first stage FF54 or the output of the third stage FF56 of the second shift register based on the data format signal. A selector 57 and a second selector 61 for selecting, based on the data format signal, the output of the fifth stage FF59 of the second shift register or the output of the last stage FF60. The output of the stage FF is Z _{i−1, j} , the output of the first selector 57 is pixel Z _{i, j + 1} , and the output of the fourth stage FF58 of the second shift register is the pixel Z _{i, j} . The output of the selector 61 of the pixel Z
The output of the FF at the final stage of the third shift register of _{i, j-1} is converted to data of the same color of the pixel Z _{i + 1, j} , for example, R
_{i−1, j} , R _{i, j + 1} , R _{i, j−1} , R _{i, j} , R _{i + 1, j} are output to the Laplacian circuit, respectively, and the output of the first stage of the second shift register is output as new two lines. The output of the first stage of the third shift register is output to the line memory 23 as the previous data and the new one-line previous data is output to the line memory 23.

 The line memories 22 and 23 correspond to the data storage unit 4.

The Laplacian circuit 24 corresponds to the arithmetic processing circuit 3 and is a known circuit that realizes the arithmetic operation represented by the equation (1).

Z ′ _{i, j} = Z _{i, j} + K ｛4Z _{i, j} − (Z _{i−1, j} + Z _{i, j−1} + Z _{i, j + 1} + Z _{i + 1, j} )} (1) where K is As an arbitrary real number, the positional relationship between the _target pixel Z _{i, j} and the peripheral pixels is as shown in FIG.

 Next, the operation of FIG. 7 will be described.

If the input data format is plane-sequential data, and the R data of the target pixel is Ri, j, the relationship with the surrounding pixels is the same color data in each line in the sub-scanning direction as shown in FIG. The line signal 5 is selected as the reset signal 44 of the address counter 42 by the format signal 6, and as shown in FIG.
The address is initialized for each line, the data 51 two lines earlier and the data 52 one line earlier are read from the line memories 22 and 23, and the data is stored in FF53 and FF54. Also, FF54
Is output as the data 62 of the previous line and the output of FF55 as the data 63 of the previous line, and written to each line memory. Then, by selecting the output of FF56 by the selector 57 and the output of FF59 by the selector 61 according to the data format signal 6, the target pixel and the peripheral pixels are selected, and the Laplacian circuit 24 performs an operation and outputs the selected pixel.

In the case of line-sequential data, the R data of the pixel of interest is Ri, j
Then, the relationship with the peripheral pixels is the same color data in every two lines in the sub-scanning direction as shown in FIG. 11, so the data format signal 6 selects the three-line signal 43 as the reset signal 44 of the address counter 42. As shown in FIG. 5, the address is initialized every three lines. Other operations are the same as those in the frame sequential data processing.

In the case of dot sequential data, the R data of the pixel of interest is
_{If i and j} , the relationship with the peripheral pixels is as shown in FIG. 12, so control the address in the same way as in the frame sequential data processing, or select the output of FF 54 with the selector 57 and the output of FF 60 with the select 61 Then, the target pixel and peripheral pixels are selected. And
The Laplacian circuit 9 performs an operation on these data and outputs the result.

FIG. 13 is a block diagram showing the configuration of an embodiment of the present invention, which is an error diffusion circuit for reducing the overall error amount by using the error amount of peripheral pixels generated when binarizing multi-valued data at the time of calculating the pixel of interest. is there.

The control means 1 has the configuration shown in FIG. 3, and controls the address 9 of the line memory 29 as described above according to the data format.

The line memory 29 has a capacity of at least one line (the number of pixels of one line × the number of colors × the bit length of a pixel) or more.

As will be described in detail later, the sequential circuit 30 outputs error data of three neighboring pixels in addition to the input pixel data. As shown in FIG. FF, a second shift register which also receives the error amount 32 of the input data from the error operation unit 31 and also includes four FFs, and input data 7 And a first selector for selecting, based on a data format signal, a Q output of the second stage FF76 or a Q output of the last stage FF78 of the first shift register.
80, and a second selector 80 for selecting the Q output of the second stage FF77 or the Q output of the last stage FF79 of the second shift register based on a data format signal. The Q output of the first stage FF74 of the shift register is output to the pixel Z _{i−1, j}
And the output of the first selector 80 to the pixel Z _{i−1, j−1}
The output of the second selector 81 is output to the data of the same color of the pixel Z _{i, j−1} , for example, R _{i−1, j} , R _{i−1, j−1} , R
_{i, j−1} error amount Δ _{i−1, j} , Δ _{i−1, j−1} , Δ _{i, j−1}
The Q output of the FF to which the input data 7 is input is output to the error calculation unit as the same color data R _{i, j} of the pixel Z _{i, j} . Further, the Q output of the FF75 is newly stored in the line memory as an error amount one line before. The error calculation unit 31 corresponds to the calculation processing circuit 3 and implements a known error diffusion algorithm, and can be configured by an adder, a shift register, or the like. Here, the error of the surrounding pixels is weighted by the digital filter of FIG.

 Next, the operation of FIG. 13 will be described.

If the input data format is dot-sequential data, and the R data of the pixel of interest is R _{i, j} , the relationship with the surrounding pixels is 16th.
As shown in the figure, since the same color data is used for each line in the sub-scanning direction, the line signal 5 is selected by the selector 41 based on the data format signal 6, and the address is initialized for each line as shown in FIG. Then, the address 9 reads out the memory data 10 corresponding to the pixel from the line memory 61 as the error amount 72 one line before, and stores the data in the FF 74. In the sequential circuit 30, the selector is selected based on the data format signal 6.
Select the output of FF78 with 80, the output of FF79 with selector 81,
Along with the output of FF74, the error amount of peripheral pixels required for the operation is selected. The error calculation unit 31 performs a calculation on the input data 7 using the error amount obtained in this way and outputs the result. Also,
The error amount 32 generated at this time is written to the FF 75 and also written to the line memory 29 as new error data one line before.

In the case of line-sequential data, the R data of the pixel of interest is
_{If i and j} , the relationship with the peripheral pixels is the same color data in every two lines in the sub-scanning direction as shown in FIG. 17, so the selector 41 in FIG.
Is selected and the address 9 is set every three lines as shown in FIG.
Is initialized. Then, the address 9 reads out the memory data 10 corresponding to the pixel from the line memory 61 as the error amount 72 one line before, and stores the data in the FF 74. Other operations may be the same as in the case of the frame sequential data processing.

In the case of plane-sequential data, the R data of the pixel of interest is
_{Assuming that i, j} , the relationship with the peripheral pixels is the same color data in each line in the sub-scanning direction as shown in FIG. 18, so that the line signal 5 is selected by the selector 41 based on the data format signal 6, and the dot sequential data and Similarly, the address is initialized for each line. The address 9 reads the memory data 10 corresponding to the pixel from the line memory 61 as the error amount 72 for each line, and stores the data in the FF 74. Also, sequential circuit
At 30, the data format signal 6 outputs the output of FF76 by the selector 80,
The output of FF77 is selected by the selector 81, and the error amount of peripheral pixels required for the operation is selected in accordance with the output of FF74. The error calculation unit 31 performs a calculation on the input data 7 using the error amount obtained in this way and outputs the result. In addition, the error amount 32 generated at this time is written in the line memory 29 as the error data of the previous line and the FF75.

FIG. 2 is a block diagram showing the configuration of the embodiment of the present invention, which performs an operation on the memory data 10 and the input data 7 and outputs the result. Therefore, unlike FIG. 1, the sequential circuit 2 becomes unnecessary, and the input data is input to the arithmetic processing circuit 3. Further, the control means 1, the arithmetic processing circuit 3, and the data storage means 4 can be configured similarly to FIG.

 Next, the operation of FIG. 2 will be described.

The data format signal 6 indicating the data format of the input image, the line signal 5 indicating the effective range of the data, and the clock 7 synchronized with the data are input to the control means 1, and the reset signal 44 of the address counter 42 is inputted as described above. To the data format signal 6
To control the generation method of the address 9.

The data storage means 4 stores image data or coefficients used for the operation, outputs memory data 10 specified by the address 9 to the operation processing circuit 3, and stores input data and operation results in new data. Memory data 10
To be stored.

The arithmetic processing circuit 3 uses the memory data 10 corresponding to the pixel, performs a desired operation on the input data, and outputs the result.

FIG. 19 is a block diagram showing a configuration of an embodiment of the present invention, which is a shading correction circuit for correcting variations in illuminance of a light source and variations in sensitivity of an image sensor, a lens, and the like.

As described above, the control means 1 has a configuration as shown in FIG. 3, and the reset signal 44 of the address counter 42 is either a line signal 5 or a three-line signal 43 in which three line signals are used as one line. Is selected by the data format signal 6, and the address is controlled as described above.

The white reference data RAM 14 and the black reference data PAM 15 correspond to the data storage means 4 and have a capacity of at least one line (the number of pixels of one line × the number of colors × the bit length of a pixel) and store correction data. Static RAM.

The shading correction unit 18 corresponds to the arithmetic processing circuit 3, and the arithmetic method is well-known. The operation formula is shown below.

In the above equation, C is a normalization constant, which is 256 if the data length is 8 bits. D _in is the input data, D
_OUT is the output data, D _W is the white reference data, D _B represents the black reference data.

 Next, the operation of FIG. 19 will be described.

First, in order to write the white reference data 16 into the white reference data RAM 14 and the black reference data 17 into the black reference data RAM 15, the data format signal 6 is input to the control means 1 in advance, and the white reference data RAM 14 is selected. Then, the white reference data 16 is written to the address specified by the address. The black reference data 17 is similarly written into the black reference data RAM 15. At this time, the control means 1 changes the address generation method according to the data format. In the dot sequential data, the line signal 5 is selected as the reset signal 44 of the address counter 42, and the address is initialized line by line as shown in FIG. 3-line signal 43 for line-sequential data
And the address is initialized every three lines as shown in FIG. Plane-sequential data operates similarly to dot-sequential data.

The correction data is stored as described above, and when the image data is input, the address 9 is output by the control means 1 in accordance with the data format, and the white reference data RAM 5 and the black reference data RAM 6 correspond to each pixel. The correction data is read, and a correction operation of the image data is performed. In this case, the method of generating the address 9 is the same as when writing the correction data to the RAM.

FIG. 20 is a block diagram showing the configuration of the number of times of zooming according to the embodiment of the present invention, and performs zooming in the sub-scanning direction.

The control means 1 has the configuration shown in FIG. 3, and controls the address 9 of the line memory 20 as described above according to the data format.

The line memory 20 has a capacity of at least one line (the number of pixels for one line × the number of colors × the bit length of a pixel) or more.

The linear interpolation circuit 19 corresponds to the arithmetic processing circuit 3 and realizes a known linear interpolation calculation algorithm. Data is created and converted to pixel density using two data of the original cycle corresponding to the nearest 100% scaling factor sandwiching a certain cycle determined by the scaling factor.

 Next, the operation of FIG. 20 will be described.

The data format signal 6 is input to the control means 1 to select either the line signal 5 or the three-line signal 43 having three line signals as one line for the reset signal 44 of the address counter 42.

In the case of the dot-sequential data and the frame-sequential data, the address 9 is incremented as shown in FIG. 4 using the line signal 5 as the reset signal 44 of the address counter 42.
The line signal 43 is used as a reset signal 44 of the address counter 42 and is incremented as shown in FIG.

As described above, the same color data is arranged at the same address regardless of the data format.

When the input data 7 is input to the linear interpolation circuit 19, the control means 1 generates an address 9 according to the data format, and stores the same color data one line before from the line memory 20 into the memory data.
10, and the input data 7 is written to the line memory 20 at the same address. Assuming that the magnification is set to 200%, the linear interpolation circuit 19 outputs the input data 7, the memory data 10 read from the line memory 20, and the average data of the input data 7.

Needless to say, if an appropriate sequential circuit is used based on the configuration shown in FIG. 1, a scaling circuit in the main scanning direction can be similarly configured.

FIG. 21 is a block diagram showing a configuration of an embodiment of the present invention, which is a block diagram of a dither circuit for producing a halftone.

The control means 1 is configured to output the upper 2 bits and the lower 2 bits as shown in FIG. 22, and the portion for outputting the upper 2 bits is almost the same as the control circuit shown in FIG.
Line counter 40, selector 66, upper address counter
Consists of 64. The part that outputs the lower two bits is a clock counter 70 and a selector that outputs either the clock or the output of the clock counter 70 based on the data format signal.
67, and a lower address counter 65 to which a signal from the selector 67 is input to a clock terminal. The reset signals 68 and 69 of the address counter 64 and the lower address counter 65 are selected by the data format signal 6. The reset signal 102 of the upper address counter 64 is the upper address 2
The bit is enabled when both bits are "1", and reset at the next clock input 68. The reset signal 103 of the lower address counter 65 is enabled when both bits of the lower address are "1", and reset at the next clock input 69. Thereby, the control means 1 outputs the address 9 to the ROM 25 according to the data format.

The ROM 25 corresponds to the data storage means 4 and stores a dither pattern. For example, it is assumed that a 4 × 4 dither pattern shown in FIG. 23 is stored in accordance with an address map shown in FIG.

The comparator 26 corresponds to the arithmetic processing circuit 3 and sets the 8-bit output of the ROM 25 to a comparator level and binarizes the 8-bit input data 7.

 Next, the operation of FIG. 21 will be described.

In the case of dot-sequential data, the data format signal 6 causes the selector 66 to output the line signal 5 and the selector 67 outputs the three clock signal 71.
Is selected, and an address 9 is generated with a cycle of four lines as shown in FIG.

In the case of line sequential data, the selector 66 uses the data format signal 6 to output the three-line signal 43 and the selector 67 uses the clock signal 8.
26, an address 9 is generated with a cycle of 12 lines, and a comparison level 27 is output from the ROM 25 as shown in FIG.

In the case of frame sequential data, the line signal 5 is selected by the selector 66 by the data format signal 6 and the clock signal 8 by the selector 67, and an address 9 is generated with a period of 4 lines as shown in FIG. Output level 27.

Using the compare level 27 obtained as described above, the input data 7 is binarized and output.

〔The invention's effect〕

As described above, the present invention makes it possible to perform arithmetic processing on each data format, thereby significantly improving the versatility of an image processing apparatus and facilitating connection with other apparatuses.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a block diagram showing the configuration of the control means 1, and FIG. FIG. 5 is a timing chart at the time of dot-sequential data processing of the embodiment, FIG. 5 is a timing chart at the time of line-sequential data processing of the embodiment of the present invention, FIG. 6 is a block diagram of a sequential circuit, and FIG. FIG. 8 is a block diagram of a configuration of a contour emphasizing circuit of the embodiment, FIG. 8 is a block diagram of a sequential circuit (contour emphasizing circuit), FIG. 9 is a digital filter of the contour emphasizing circuit used in the embodiment, and FIG. Fig. 11 shows a digital filter for line-sequential data, and Fig. 11 shows a digital filter for line-sequential data.
13 is a block diagram of an error diffusion circuit according to an embodiment of the present invention. FIG. 14 is a block diagram of a sequential circuit (error diffusion circuit).
FIG. 16 shows the weighting filter of the error diffusion circuit used in the embodiment, FIG. 16 shows the weighting filter of FIG. 15 in the point-sequential data processing, and FIG. 17 shows the weighting filter of FIG. 15 in the line-sequential data processing. FIG. 18 is a weighting filter of FIG. 15 at the time of field sequential data processing, FIG. 19 is a block diagram showing the configuration of a shading correction circuit of an embodiment of the present invention, and FIG. FIG. 21 is a block diagram showing a configuration of a dither circuit according to an embodiment of the present invention. FIG. 22 is a block diagram showing a configuration of control means of the dither circuit. FIG. 23 is a block diagram showing an embodiment of the present invention. FIG. 24 is an address map of the ROM 25, FIG. 25 is a timing chart at the time of dot sequential data processing in the dither circuit according to the embodiment of the present invention, and FIG. 26 is a dither pattern using the dither circuit. In the example dither circuit FIG. 27 is a timing chart at the time of sequential data processing, FIG. 27 is a timing chart at the time of plane-sequential data processing in the dither circuit of the embodiment of the present invention, and FIG. 28 is an explanatory diagram showing a data array of dot-sequential data. FIG. 30 is an explanatory diagram showing a data array of line sequential data, and FIG. 30 is an explanatory diagram showing a data array of frame sequential data. DESCRIPTION OF SYMBOLS 1 ... Control circuit 2 ... Sequential circuit 3 ... Operation processing circuit 4 ... Data storage means 6 ... Data format signal 7 ... Shading correction circuit 8 ... Linear interpolation circuit 18 ... Shading correction unit 19 ... Linear interpolation circuit 24 Laplacian circuit 26 Comparator 31 Error calculator 40 Line counter 41 Selector 42 Address counter

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-271184 (JP, A) JP-A-1-1133791 (JP, A) JP-A-1-201780 (JP, A) JP-A-63-271184 307475 (JP, A) JP-A-60-14376 (JP, A)

Claims (4)

(57) [Claims] An image processing apparatus for performing an arithmetic process by paying attention to a pixel region of two-dimensional color image data stores either one of image data and coefficient data related to input pixel data. A data storage unit, a data format signal indicating whether the input pixel data is dot-sequential, line-sequential, or plane-sequential, a line signal indicating a data range of one line, and a clock signal synchronized with the input pixel data. Control means for generating an address signal corresponding to the data format of the input pixel data to the data storage means, and at least one color data of the input pixel data read from the data storage means based on Output data subjected to a desired arithmetic processing using the data corresponding to the one color of the image data or the coefficient data. And an arithmetic processing means for outputting data corresponding to any one of the read data as memory data to the data storage means according to the desired arithmetic processing. Image processing device. 2. An image processing apparatus for performing an arithmetic process by paying attention to a pixel area of two-dimensional color image data, comprising: data storage means for storing coefficient data inputted in advance related to input pixel data; Based on a data format signal indicating whether the input pixel data is dot-sequential, line-sequential, or plane-sequential, a line signal indicating a data range of one line, and a clock signal synchronized with the input pixel data, Control means for generating an address signal corresponding to the data format of the input pixel data to data storage means; and at least one color data of the input pixel data, the coefficient data of the coefficient data read from the data storage means. And an arithmetic processing means for performing desired arithmetic processing using the data corresponding to the one color and outputting the result. Place. 3. An image processing apparatus for performing an arithmetic process using data of a pixel of interest in a pixel region of two-dimensional color image data and pixels surrounding the pixel of interest, wherein image data related to input pixel data or Data storage means for storing any one of coefficient data; a data format signal indicating whether the input pixel data is dot-sequential, line-sequential, or plane-sequential; and a line signal indicating a data range of one line A control unit for generating an address signal corresponding to the data format of the input pixel data to the data storage unit based on a clock signal synchronized with the input pixel data, and a clock signal read from the data storage unit. The image data or coefficient data and the input pixel data are held, and based on the data format signal, the held data is held. Data corresponding to at least one color of the input pixel data is output as operation data according to the type of operation processing, and one of the data stored in the data storage means is output according to the operation processing. A sequential circuit means for outputting data corresponding to the data as memory data to the data storage means, and an arithmetic processing means for performing arithmetic processing according to the type of arithmetic processing on the arithmetic data output from the sequential circuit means. An image processing apparatus characterized in that: 4. The control means generates the same address signal when the data format is dot-sequential and frame-sequential.
4. The image processing apparatus according to claim 3, wherein said sequential circuit means is configured to selectively output data held at the same holding position when said data format is plane-sequential and line-sequential.