JP2888385B2 - Flip-chip connection structure of light receiving / emitting element array - Google Patents
Flip-chip connection structure of light receiving / emitting element arrayInfo
- Publication number
- JP2888385B2 JP2888385B2 JP23732391A JP23732391A JP2888385B2 JP 2888385 B2 JP2888385 B2 JP 2888385B2 JP 23732391 A JP23732391 A JP 23732391A JP 23732391 A JP23732391 A JP 23732391A JP 2888385 B2 JP2888385 B2 JP 2888385B2
- Authority
- JP
- Japan
- Prior art keywords
- bump
- gold
- tin
- bumps
- glass substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 67
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 58
- 229910052737 gold Inorganic materials 0.000 claims abstract description 58
- 239000010931 gold Substances 0.000 claims abstract description 58
- 229910052718 tin Inorganic materials 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 239000011521 glass Substances 0.000 claims abstract description 49
- 229910052709 silver Inorganic materials 0.000 claims abstract description 18
- 239000004332 silver Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 230000015572 biosynthetic process Effects 0.000 abstract description 19
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 18
- 230000005496 eutectics Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 11
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 238000003825 pressing Methods 0.000 abstract description 3
- 230000010355 oscillation Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000035939 shock Effects 0.000 description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 239000011135 tin Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011133 lead Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の利用分野】この発明は受発光素子アレイのフリ
ップチップ接続構造に関し、特にＬＥＤアレイ等の受発
光素子アレイをガラス等の透明基板にフリップチップ接
続する際に用いる接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip connection structure of a light emitting / receiving element array, and more particularly to a connection structure used when flip-chip connecting a light emitting / receiving element array such as an LED array to a transparent substrate such as glass.
【０００２】[0002]
【従来技術】従来のフリップチップ接続構造では、電子
部品と基板とにバンプを形成した後、収縮性の接着剤で
電子部品を基板に結合し、接着剤の収縮力でバンプを接
続するものが知れらている（特開平２−１５５，２５７
号）。またバンプ材料の組合せを半田と金、あるいは半
田と半田とし、リフロー炉でバンプとバンプとを接続す
るものも周知である（例えば特公平２−２６，７８０
号）。更に日経マイクロデバイス，１９９０年１２月
号，１５頁は、ワイヤボンディングに類似の手法で金バ
ンプを形成することを提案している。この手法では、金
の細線をワイヤボンディングして金ボールを形成した
後、ボールの上部で金線を切断し、金バンプとする。こ
の提案では他方のバンプには半田バンプを用い、リフロ
ー炉で熱処理して金バンプと半田バンプとを接続する。2. Description of the Related Art In a conventional flip-chip connection structure, after a bump is formed on an electronic component and a substrate, the electronic component is bonded to the substrate with a shrinkable adhesive, and the bump is connected by the shrinkage of the adhesive. Known (Japanese Unexamined Patent Publication No. 2-155,257)
issue). It is also well known that a combination of bump materials is solder and gold or solder and solder and the bumps are connected in a reflow furnace (for example, Japanese Patent Publication No. 2-26780).
issue). Further, Nikkei Microdevices, December 1990, page 15, proposes forming a gold bump by a method similar to wire bonding. In this method, a gold thin wire is wire-bonded to form a gold ball, and then the gold wire is cut at the upper portion of the ball to form a gold bump. In this proposal, a solder bump is used as the other bump, and a heat treatment is performed in a reflow furnace to connect the gold bump and the solder bump.
【０００３】半田バンプの形成では、特公平２−２６，
７８０号に示されているように、最初に基板や電子部品
にクロムやモリブデン等のバリア皮膜を形成し、バリア
皮膜上に金、ニッケル、銅等の導電性金属膜を形成す
る。次いでレジストでバンプの形成部以外をマスクし、
半田メッキによってバンプを形成する。バンプの形成後
には、レジストを除去し、導電性金属膜やバリア皮膜を
エッチングする工程が必要である。このことから明かな
ように、バンプの形成工程は長く、かつバリア皮膜や導
電性金属膜による汚染や、レジストでマスクした部分へ
の半田の拡散による汚染が問題となる。半田バンプの他
の問題として、半田がバンプの下地の電極の金メッキを
食べるため、接続が失敗し易いことが有る。結局半田バ
ンプは形成工程が複雑で、ＩＣ等を汚染する可能性が有
り、接続時に電極の金メッキと反応し易い。これらのた
め半田バンプを用いないフリップチップ接続構造が必要
である。In the formation of solder bumps, Japanese Patent Publication No. 2-26,
As shown in No. 780, first, a barrier film such as chromium or molybdenum is formed on a substrate or an electronic component, and a conductive metal film such as gold, nickel, or copper is formed on the barrier film. Next, mask the area other than the bump formation area with resist,
A bump is formed by solder plating. After the formation of the bump, a step of removing the resist and etching the conductive metal film or the barrier film is required. As is clear from this, the bump forming process is long, and there is a problem of contamination by a barrier film or a conductive metal film, and contamination by diffusion of solder into a portion masked with a resist. Another problem with solder bumps is that the connection tends to fail because the solder eats the gold plating on the underlying electrodes of the bumps. After all, the formation process of the solder bump is complicated, and there is a possibility of contaminating the IC and the like, and the solder bump easily reacts with the gold plating of the electrode at the time of connection. For these reasons, a flip-chip connection structure that does not use solder bumps is required.
【０００４】[0004]
【発明の課題】この発明の課題は、ガラス基板への受発
光素子アレイのフリップチップ接続構造において、 （１） バンプの形成とバンプ相互の接続を容易にする
と共に、 （２） 熱衝撃に弱く表面が平滑なガラス基板でも、フ
リップチップ接続を確実に行えるようにし、 （３） ガラス基板上面の受発光素子に対面する領域に
配線を設ける必要を無くし、受発光素子へ入出射する光
が、ガラス基板上面の配線で遮られないようにすること
にある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a flip-chip connection structure of a light emitting / receiving element array to a glass substrate, (1) to facilitate formation of bumps and connection between bumps, and (2) to be vulnerable to thermal shock. (3) Eliminates the need to provide wiring on the upper surface of the glass substrate facing the light emitting and receiving elements, so that light entering and exiting the light emitting and receiving elements can be reduced even when the glass substrate has a smooth surface. An object is to prevent interruption by wiring on the upper surface of a glass substrate.
【０００５】[0005]
【発明の構成】この発明は、下面に、複数個の受発光素
子と、該各受発光素子を縦断する複数個の電極と、該各
電極の両端部に設けた第１バンプとを有する受発光素子
アレイを、ガラス基板上に配設するとともに、前記ガラ
ス基板の上面で、前記受発光素子が対面する領域外に、
複数個の配線と、前記各第１バンプに対応する複数個の
第２バンプとを設け、これら第１バンプ及び第２バンプ
のいずれか一方を錫を主成分とする金属で、他方を金ま
たは銀を主成分とする金属で構成して、両バンプを溶着
してなる、受発光素子アレイのフリップチップ接続構造
にある。According to the present invention, there is provided a light receiving device having a plurality of light emitting / receiving elements on a lower surface thereof, a plurality of electrodes extending longitudinally through the respective light emitting / receiving elements, and first bumps provided at both ends of each of the electrodes. A light emitting element array is arranged on a glass substrate, and on the upper surface of the glass substrate, outside a region where the light emitting and receiving elements face each other,
A plurality of wirings and a plurality of second bumps corresponding to the respective first bumps are provided, and one of the first and second bumps is made of a metal mainly containing tin, and the other is made of gold or gold. A flip-chip connection structure of a light emitting / receiving element array, which is made of a metal containing silver as a main component and is formed by welding both bumps.
【０００６】[0006]
【発明の作用】この発明では、バンプの材料を一方を金
もしくは銀を主成分とするものとし、他方を錫を主成分
とするものとする。錫は金や銀と低温で共晶化合物を形
成し、容易にバンプ相互の接続ができる。例えば金と錫
との共融温度は２１７℃、銀と錫では２２７℃である。
次に金や銀は細い線に線引きすることが容易で、ワイヤ
ボンディングに類似の手法で容易にバンプを形成でき
る。同様に錫も細い錫線を得るのが容易で、バンプの形
成が容易である。錫線は更に金線や銀線に比べ軟らか
く、ボール形成後の切断が容易でバンプの形成が特に容
易である。According to the present invention, one of the bump materials is composed mainly of gold or silver, and the other is composed mainly of tin. Tin forms a eutectic compound with gold and silver at a low temperature, and can easily connect bumps. For example, the eutectic temperature of gold and tin is 217 ° C, and that of silver and tin is 227 ° C.
Next, gold and silver can be easily drawn into thin lines, and bumps can be easily formed by a method similar to wire bonding. Similarly, for tin, it is easy to obtain a thin tin wire, and it is easy to form a bump. The tin wire is softer than the gold wire and the silver wire, and can be easily cut after forming the ball, and the formation of the bump is particularly easy.
【０００７】これらのため、バンプの一方を金や銀、他
方を錫とすると、これらの細線を基板や受発光素子アレ
イにボンディングしてボールを形成した後、ボールの上
部で線を切断することでバンプを形成できる。金や銀と
錫は２００℃程度で共晶化合物を形成するので、熱圧着
や超音波圧着等で容易にバンプ相互を接続できる。これ
らのため、熱衝撃に弱く、バンプの下地電極との付着強
度が低いガラス基板でも、確実に受発光素子アレイの多
数の電極をフリップチップ接続できる。また受発光素子
は電極で縦断され、この電極の両端部に第１バンプを設
けて、ガラス基板上面の第２バンプに接続するので、ガ
ラス基板上面の配線を受発光素子に対面する領域に設け
る必要が無く、ガラス基板上面の配線による光の散乱が
ない。For this reason, if one of the bumps is made of gold or silver and the other is tin, these fine wires are bonded to a substrate or a light emitting / receiving element array to form a ball, and then the wire is cut at the top of the ball. Can form a bump. Since gold, silver and tin form a eutectic compound at about 200 ° C., the bumps can be easily connected to each other by thermocompression bonding or ultrasonic compression bonding. For this reason, even if the glass substrate is vulnerable to thermal shock and has low adhesion strength of the bump to the underlying electrode, a large number of electrodes of the light emitting / receiving element array can be reliably flip-chip connected. Further, the light emitting / receiving element is longitudinally cut by electrodes, and first bumps are provided at both ends of the electrode and connected to the second bumps on the upper surface of the glass substrate. Therefore, the wiring on the upper surface of the glass substrate is provided in a region facing the light emitting / receiving element. There is no need, and there is no scattering of light due to wiring on the upper surface of the glass substrate.
【０００８】[0008]
【実施例】ガラス基板への受発光素子アレイのフリップ
チップ接続について、実施例を説明する。ガラス基板を
例としたのは、ガラスは熱衝撃に弱く、表面が平滑なた
めバンプの下地の電極の付着強度が低く、フリップチッ
プ接続が特に困難な基板だからである。またガラス基板
を用いた他の理由は、受発光素子アレイの受発光面をガ
ラス基板に向き合わせ、ガラス基板を通じて受発光を行
い、受発光素子アレイの表面高さをガラス基板を基準に
揃え、受発光素子アレイの表面高さのばらつきによる焦
点精度の低下を防止するためである。EXAMPLE An example of flip-chip connection of a light emitting / receiving element array to a glass substrate will be described. The glass substrate is taken as an example, because glass is susceptible to thermal shock and the surface is smooth, so that the adhesion strength of the electrode under the bump is low, and flip-chip connection is particularly difficult. Another reason for using a glass substrate is to face the light emitting and receiving surface of the light emitting and receiving element array to the glass substrate, perform light receiving and emitting through the glass substrate, and align the surface height of the light receiving and emitting element array with respect to the glass substrate, This is to prevent a reduction in focus accuracy due to a variation in surface height of the light receiving / emitting element array.
【０００９】図１において、２はガラス等の透明基板、
４はＧａＡｓＬＥＤアレイである。ＧａＡｓＬＥＤアレ
イ４に変え、ＣＣＤや光電池アレイ等の受光素子アレイ
を用いても同様である。６はＧａＡｓにＺｎ等の不純物
を注入した発光体で、発光体６の底部と基板のＧａＡｓ
層との界面が発光面となる。８はＬＥＤアレイ４に接続
した共通リードで、例えばリードフレームをＬＥＤアレ
イ４の裏面の共通電極に熱圧着した後、リードフレーム
の基部を切断したものとする。１０はガラス基板２上の
ポリイミド樹脂等の絶縁層、１２はガラス基板２上の共
通電極である。１４はＬＥＤアレイ４に設けた電極で、
例えばＡｌ電極とし、１６はガラス基板２上に設けた電
極で、例えばＡｌ電極上に金をメッキ、あるいは金を蒸
着やスパッタリングで積層したものとするが、金被覆は
設けなくても良い。金被覆を設ける場合、バンプ形成部
にのみ設ければ良い。In FIG. 1, reference numeral 2 denotes a transparent substrate such as glass,
Reference numeral 4 denotes a GaAs LED array. The same applies when a light receiving element array such as a CCD or a photovoltaic array is used instead of the GaAs LED array 4. Reference numeral 6 denotes a luminous body obtained by injecting impurities such as Zn into GaAs.
The interface with the layer is the light emitting surface. Reference numeral 8 denotes a common lead connected to the LED array 4. For example, it is assumed that a lead frame is thermocompression-bonded to a common electrode on the back surface of the LED array 4 and then the base of the lead frame is cut. Reference numeral 10 denotes an insulating layer of a polyimide resin or the like on the glass substrate 2, and reference numeral 12 denotes a common electrode on the glass substrate 2. Reference numeral 14 denotes an electrode provided on the LED array 4.
For example, an Al electrode is provided, and 16 is an electrode provided on the glass substrate 2. For example, gold is plated on the Al electrode, or gold is deposited by vapor deposition or sputtering, but the gold coating may not be provided. In the case where a gold coating is provided, it may be provided only in the bump formation portion.
【００１０】１８は金バンプで、金を主成分とするもの
であれば良く、例えば１０重量％以下の範囲で銀やパラ
ディウム、ニッケル、錫等を含有させても良い。金バン
プ１８に変えて、銀バンプを用いても良く、その場合に
も例えば１０重量％以下の範囲で、銀を金やパラディウ
ム、錫等で置換しても良い。２０は錫バンプで、錫を主
成分とするものであれば良く、例えば１０重量％以下の
範囲でニッケルや鉛、金、銀等を含有させても良い。錫
バンプ２０や金バンプ１８に対する置換の範囲は、細線
への線引きを困難にせず、金や銀と錫との共晶形成を妨
げない範囲である。ＬＥＤアレイ４に金バンプ１８を設
け、ガラス基板２に錫バンプ２０を設けたのは、錫バン
プ２０の形成に用いる錫線が軟らかく、バンプ形成時の
錫のボール形成が容易で、かつボール形成後の錫線の切
断が容易だからである。これは脆弱で電極１６の付着強
度が低い、ガラス基板２に特に適している。またガラス
基板２側の電極１６の表面を金で被覆したのは、錫と金
との合金形成反応を利用し、バンプ２０の形成時のボー
ル形成を容易にするためである。これらの点を除けば、
ガラス基板２側に金バンプを設け、ＬＥＤアレイ４側に
錫バンプを設けても良い。Reference numeral 18 denotes a gold bump, which may be one containing gold as a main component. For example, silver, palladium, nickel, tin, etc. may be contained in a range of 10% by weight or less. Instead of the gold bump 18, a silver bump may be used, and in that case, silver may be replaced with gold, palladium, tin, or the like, for example, in a range of 10% by weight or less. Reference numeral 20 denotes a tin bump, which may contain tin as a main component, and may contain, for example, nickel, lead, gold, silver or the like in a range of 10% by weight or less. The range of substitution with the tin bumps 20 and the gold bumps 18 is a range that does not make it difficult to draw a fine wire and does not hinder the eutectic formation of gold or silver and tin. The reason why the gold bumps 18 were provided on the LED array 4 and the tin bumps 20 were provided on the glass substrate 2 is that the tin wire used for forming the tin bumps 20 is soft, so that the tin ball can be easily formed at the time of bump formation, This is because the subsequent cutting of the tin wire is easy. This is particularly suitable for the glass substrate 2 which is fragile and has low adhesion strength of the electrode 16. The reason why the surface of the electrode 16 on the glass substrate 2 is coated with gold is to facilitate the formation of a ball when the bump 20 is formed by utilizing an alloying reaction between tin and gold. Apart from these points,
A gold bump may be provided on the glass substrate 2 side, and a tin bump may be provided on the LED array 4 side.
【００１１】図２に、ＬＥＤアレイ４上の金バンプ１８
の配置を示す。電極１４は発光体６を縦断するように形
成し、発光体６の両側に金バンブ１８を設けた。図３
に、ガラス基板２上の錫バンプ２０の配置を示す。ガラ
ス基板２には例えば４０アレイ程度、ＬＥＤアレイ４を
直線状に配置し、電極１６はＬＥＤアレイ４毎にじぐざ
ぐに折り返して配置する。電極１６は、ＬＥＤアレイ４
からの発光を妨げないように、発光体６の部分には設け
ず、この部分をＬＥＤアレイ４の電極１４でバイパスす
る。このため発光体６毎に、図の上下２カ所で金バンプ
１８と錫バンプ２０を用いてフリップチップ接続する。FIG. 2 shows a gold bump 18 on the LED array 4.
The following shows the arrangement. The electrode 14 was formed so as to cross the luminous body 6, and gold bumps 18 were provided on both sides of the luminous body 6. FIG.
2 shows an arrangement of the tin bumps 20 on the glass substrate 2. For example, about 40 arrays of LED arrays 4 are linearly arranged on the glass substrate 2, and the electrodes 16 are arranged in a zigzag manner for each LED array 4. The electrode 16 is the LED array 4
In order not to hinder the emission of light from the light-emitting body 6, the light-emitting body 6 is not provided, and this part is bypassed by the electrode 14 of the LED array 4. Therefore, for each light emitting body 6, flip-chip connection is performed using gold bumps 18 and tin bumps 20 at two locations above and below the figure.
【００１２】図４により、フリップチップ接続の工程を
説明する。ガラス基板２に電極１６を形成し、ＬＥＤア
レイ４に電極１４を形成する。ＬＥＤアレイ４には金バ
ンプ１８を形成し、ガラス基板２には錫バンプ２０を形
成する。これらのバンプの形成は、金や錫の細線をキャ
ピラリーから供給し、ＬＥＤアレイ４やガラス基板２を
加熱した状態で、例えば超音波振動を金や錫の細線とＬ
ＥＤアレイ４やガラス基板２の間に加えて、金や錫の細
線をＬＥＤアレイ４やガラス基板２に押し付ける。この
時の熱と超音波振動による摩擦熱、加圧力で、金線や錫
線はＬＥＤアレイ４やガラス基板２にボンディングされ
る。ボンディングは、熱のみを用いたものや超音波振動
のみを用いたものでも良い。ボンディングにより、金線
や錫線の先端のＬＥＤアレイ４やガラス基板２へのボン
ディング部はボール状となり、ボンディング直後にボー
ルの上部で金線や錫線を切断すると、バンプ１８，２０
が得られる。金線や錫線の切断は、例えば超音波を加え
ながらキャピラリーを移動させて超音波振動で切断す
る、あるいはキャピラリーの先端を局所的に発熱させ
る、またレーザー等で切断するようにすれば良い。これ
らのバンプ形成方法自体は日経マイクロデバイスに記載
のものと変わらないが、錫線は軟質で、脆弱なガラス基
板２上の電極１６に対してもボール形成が容易で、かつ
ボール形成後の切断が容易である。また半田と異なり錫
は細線に線引きするのが容易で、かつ金線に比べ安価
で、軟質なため、ボール形成時の温度を低くし、超音波
振動を弱くし、かつ加圧力を小さくできる。例えば金と
錫との共融点は２１７℃で、電極１６の表面の金と錫線
とは超音波や熱で接触面を２００℃程度に加熱すれば、
共晶を形成してボールを形成できる。Referring to FIG. 4, the steps of flip-chip connection will be described. The electrodes 16 are formed on the glass substrate 2, and the electrodes 14 are formed on the LED array 4. Gold bumps 18 are formed on the LED array 4, and tin bumps 20 are formed on the glass substrate 2. The formation of these bumps is performed by supplying a gold or tin fine wire from a capillary and heating the LED array 4 or the glass substrate 2 by, for example, applying ultrasonic vibration to the gold or tin fine wire.
In addition to the space between the ED array 4 and the glass substrate 2, a thin line of gold or tin is pressed against the LED array 4 or the glass substrate 2. The gold wire and the tin wire are bonded to the LED array 4 and the glass substrate 2 by the heat at this time, the frictional heat generated by the ultrasonic vibration, and the pressing force. The bonding may be performed using only heat or using only ultrasonic vibration. By bonding, the bonding portion of the gold wire or tin wire to the LED array 4 or the glass substrate 2 is formed into a ball shape. Immediately after bonding, when the gold wire or tin wire is cut at the top of the ball, the bumps 18 and 20 are cut.
Is obtained. The cutting of the gold wire or the tin wire may be performed, for example, by moving the capillary while applying ultrasonic waves and cutting by ultrasonic vibration, or by locally generating heat at the tip of the capillary, or by cutting with a laser or the like. Although these bump forming methods themselves are the same as those described in Nikkei Microdevices, the tin wire is soft and easy to form a ball even on the electrode 16 on the fragile glass substrate 2, and cutting after the ball is formed. Is easy. Unlike solder, tin can be easily drawn into a fine wire, and it is cheaper and softer than a gold wire. Therefore, the temperature at the time of ball formation can be lowered, ultrasonic vibration can be reduced, and the pressing force can be reduced. For example, the eutectic point of gold and tin is 217 ° C., and the gold and tin wires on the surface of the electrode 16 are heated to about 200 ° C. by ultrasonic waves or heat,
A ball can be formed by forming a eutectic.
【００１３】このようにワイヤボンディングと類似の手
法で金バンプ１８と錫バンプ２０を形成すると、金バン
プ１８や錫バンプ２０の大きさを一定にできる。これは
金線や錫線の線径で、バンプ１８，２０の大きさが定ま
るからである。次にバンプの形成工程はワイヤボンディ
ングと類似で、半田バンプの形成に比べ工程数が少な
い。更にバリア皮膜や導電性金属膜の形成、半田メッキ
等に伴う、ＬＥＤアレイ４やガラス基板２上の電極１６
の汚染がないため、バンプ形成時のＬＥＤアレイ４の無
駄が無い。When the gold bumps 18 and tin bumps 20 are formed in a manner similar to wire bonding, the sizes of the gold bumps 18 and tin bumps 20 can be made constant. This is because the size of the bumps 18, 20 is determined by the diameter of the gold wire or the tin wire. Next, the bump formation process is similar to wire bonding, and the number of processes is smaller than that of solder bump formation. Further, the electrodes 16 on the LED array 4 and the glass substrate 2 accompanying the formation of the barrier film and the conductive metal film, the solder plating, and the like.
Therefore, there is no waste of the LED array 4 during bump formation.
【００１４】バンプ１８，２０の形成後、例えばコレッ
ト２２でＬＥＤアレイ４をピックアップし、ダイマウン
ターで金バンプ１８を錫バンプ２０に熱圧着する。この
ため例えば図示しないダイマウンターでガラス基板２を
２００℃程度に加熱し、コレット２２でＬＥＤアレイ４
を接続位置に降下させれば良い。このようにすれば、コ
レット２２からの加圧とダイマウンターによる加熱で、
金バンプ１８は錫バンプ２０と共晶を形成し、相互に溶
着されて接続できる。共晶の形成はバンプ１８，２０の
奥まで進行させる必要はなく、表面部だけで良い。また
加熱温度は共融点の２１７℃よりも低くても良く、ダイ
マウンターで均一に加熱する変わりに超音波振動で金バ
ンプ１８と錫バンプ２０の接触面を加熱しても良い。銀
と錫との共融点は２２７℃で金と錫との共融の場合と同
様に低く、金バンプ１８に変えて銀バンプを用いても良
い。After the bumps 18 and 20 are formed, the LED array 4 is picked up by, for example, a collet 22, and the gold bump 18 is thermocompression-bonded to the tin bump 20 by a die mounter. Therefore, for example, the glass substrate 2 is heated to about 200 ° C. by a die mounter (not shown),
Should be lowered to the connection position. By doing so, the pressure from the collet 22 and the heating by the die mounter allow
The gold bump 18 forms a eutectic with the tin bump 20 and can be connected to each other by welding. The formation of the eutectic does not need to be advanced to the depths of the bumps 18 and 20, but only on the surface. The heating temperature may be lower than the eutectic point of 217 ° C., and instead of heating uniformly with a die mounter, the contact surface between the gold bump 18 and the tin bump 20 may be heated by ultrasonic vibration. The eutectic point of silver and tin is as low as eutectic of gold and tin at 227 ° C., and a silver bump may be used instead of the gold bump 18.
【００１５】金バンプ１８と錫バンプ２０は低温で接続
できるため、ＬＥＤアレイ４やガラス基板２に負荷が加
わらない。また半田バンプの場合と異なりリフロー炉で
の処理を要しないため、半田の拡散により電極１６表面
の金層が侵されたり、あるいは半田が拡散して発光体６
が汚染されたりすることが無い。そして１回のダイマウ
ンターによる熱圧着で、１個のＬＥＤアレイ４全体をフ
リップチップ接続でき、単純な工程でバンプを形成でき
る。これらのためバンプ相互の接続時の収率が高く、高
価なＬＥＤアレイ４の損失が少ない。Since the gold bump 18 and the tin bump 20 can be connected at a low temperature, no load is applied to the LED array 4 and the glass substrate 2. Further, unlike the case of the solder bump, since the treatment in the reflow furnace is not required, the gold layer on the surface of the electrode 16 is eroded by the diffusion of the solder, or the luminescent material 6 is diffused by the diffusion of the solder.
Is not contaminated. Then, the entire LED array 4 can be flip-chip connected by a single thermocompression bonding using a die mounter, and bumps can be formed by a simple process. Therefore, the yield at the time of connecting the bumps to each other is high, and the loss of the expensive LED array 4 is small.
【００１６】[0016]
【発明の効果】以上に述べたように、この発明では以下
の効果が得られる。 （１） 錫線や金線、あるいは銀線を用いてバンプを形
成するため、バンプの形成が容易で、バンプの下地電極
の付着力が低いガラス基板でも、容易に均質なバンプが
得られる。 （２） バンプの形成工程が単純で、バンプ形成時の受
発光素子アレイや基板の汚染・無駄がない。 （３） 金バンプや銀バンプは２００℃程度で錫バンプ
と接続できるため、熱衝撃に弱いガラス基板でも、バン
プ相互の接続が容易で、接続不良や接続時の歩止まりの
低下が無い。 （４） 用いる錫バンプは極めて安価である。 （５） ガラス基板上面の受発光素子に対面する領域に
配線を設ける必要が無く、受発光素子へ入出射する光
が、ガラス基板上面の配線で遮られない。As described above, the present invention has the following advantages. (1) Since a bump is formed using a tin wire, a gold wire, or a silver wire, the bump can be easily formed, and a uniform bump can be easily obtained even on a glass substrate having a low adhesive strength of a base electrode of the bump. (2) The bump forming process is simple, and there is no contamination / waste of the light emitting / receiving element array or the substrate during bump formation. (3) Since the gold bump and the silver bump can be connected to the tin bump at about 200 ° C., even if the glass substrate is vulnerable to thermal shock, the connection between the bumps is easy, and there is no poor connection and no reduction in the yield at the time of connection. (4) Tin bumps used are extremely inexpensive. (5) There is no need to provide a wiring in a region facing the light emitting and receiving element on the upper surface of the glass substrate, and light entering and exiting the light receiving and emitting element is not blocked by the wiring on the upper surface of the glass substrate.
【図１】 実施例の側面図FIG. 1 is a side view of an embodiment.
【図２】 実施例で用いたＬＥＤアレイ上の金バンプ
を示す平面図FIG. 2 is a plan view showing gold bumps on the LED array used in the embodiment.
【図３】 実施例で用いたガラス基板上の錫バンプを
示す平面図FIG. 3 is a plan view showing a tin bump on a glass substrate used in the example.
【図４】 実施例での熱圧着工程を示す側面図FIG. 4 is a side view showing a thermocompression bonding step in the embodiment.
２ ガラス基板 ４ ＬＥＤアレイ ６ 発光体 １４ 電極 １６ 電極 １８ 金バンプ ２０ 錫バンプ ２２ コレット 2 glass substrate 4 LED array 6 illuminant 14 electrode 16 electrode 18 gold bump 20 tin bump 22 collet
フロントページの続き (56)参考文献 特開 昭63−306634（ＪＰ，Ａ) 特開 昭56−45044（ＪＰ，Ａ) 特開 平１−202831（ＪＰ，Ａ) 特開 平４−225542（ＪＰ，Ａ) 特開 平４−356978（ＪＰ，Ａ) 特開 平２−196476（ＪＰ，Ａ) 特開 昭64−82574（ＪＰ，Ａ) 実開 昭63−84352（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311 H01L 33/00 Continuation of front page (56) References JP-A-63-306634 (JP, A) JP-A-56-45044 (JP, A) JP-A-1-2022831 (JP, A) JP-A-4-225542 (JP) JP-A-4-356978 (JP, A) JP-A-2-196476 (JP, A) JP-A-64-82574 (JP, A) JP-A-63-84352 (JP, U) (58) Field surveyed (Int. Cl. 6 , DB name) H01L 21/60 311 H01L 33/00
Claims (1)
発光素子を縦断する複数個の電極と、該各電極の両端部
に設けた第１バンプとを有する受発光素子アレイを、ガ
ラス基板上に配設するとともに、前記ガラス基板の上面
で、前記受発光素子が対面する領域外に、複数個の配線
と、前記各第１バンプに対応する複数個の第２バンプと
を設け、これら第１バンプ及び第２バンプのいずれか一
方を錫を主成分とする金属で、他方を金または銀を主成
分とする金属で構成して、両バンプを溶着してなる、受
発光素子アレイのフリップチップ接続構造。1. A light emitting / receiving element array having a plurality of light emitting / receiving elements on a lower surface, a plurality of electrodes extending longitudinally through the respective light emitting / receiving elements, and first bumps provided at both ends of each of the electrodes. A plurality of wirings and a plurality of second bumps corresponding to each of the first bumps are provided on the upper surface of the glass substrate and outside a region facing the light emitting and receiving elements. The first and second bumps are made of a metal containing tin as a main component, and the other is made of a metal containing gold or silver as a main component. Flip chip connection structure of element array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23732391A JP2888385B2 (en) | 1991-08-22 | 1991-08-22 | Flip-chip connection structure of light receiving / emitting element array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23732391A JP2888385B2 (en) | 1991-08-22 | 1991-08-22 | Flip-chip connection structure of light receiving / emitting element array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555635A JPH0555635A (en) | 1993-03-05 |
| JP2888385B2 true JP2888385B2 (en) | 1999-05-10 |
Family
ID=17013672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23732391A Expired - Fee Related JP2888385B2 (en) | 1991-08-22 | 1991-08-22 | Flip-chip connection structure of light receiving / emitting element array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2888385B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3348528B2 (en) | 1994-07-20 | 2002-11-20 | 富士通株式会社 | Method for manufacturing semiconductor device, method for manufacturing semiconductor device and electronic circuit device, and electronic circuit device |
| JP4104889B2 (en) * | 2002-03-29 | 2008-06-18 | 株式会社東芝 | Optical semiconductor device |
| JP3993475B2 (en) * | 2002-06-20 | 2007-10-17 | ローム株式会社 | LED chip mounting structure and image reading apparatus having the same |
| JP2007035881A (en) * | 2005-07-26 | 2007-02-08 | Matsushita Electric Works Ltd | Mounting structure of surface-mounting electronic component and illumination instrument |
| US7854365B2 (en) * | 2008-10-27 | 2010-12-21 | Asm Assembly Automation Ltd | Direct die attach utilizing heated bond head |
| DE102009039890A1 (en) * | 2009-09-03 | 2011-03-10 | Osram Opto Semiconductors Gmbh | Optoelectronic component with a semiconductor body, an insulating layer and a planar conductive structure and method for its production |
| JP2013012517A (en) | 2011-06-28 | 2013-01-17 | Ricoh Co Ltd | Reflective photosensor and image formation apparatus having the same |
| JP2013145838A (en) * | 2012-01-16 | 2013-07-25 | Kyocera Corp | Photoelectric conversion element mounting member and photoelectric conversion device |
| KR20240006084A (en) * | 2017-12-26 | 2024-01-12 | 에피스타 코포레이션 | Light emitting device, and manufacturing method and display module thereof |
-
1991
- 1991-08-22 JP JP23732391A patent/JP2888385B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0555635A (en) | 1993-03-05 |
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