JP2876636B2 - Circuit data division method for logic simulation - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation circuit data division method, and in particular, a logic simulation as preprocessing for generating circuit data to be input to a multiprocessor logic simulation apparatus. Circuit data division method.

[Technical environment]

In recent years, the scale of integrated circuits has increased due to advances in VLSI technology,
With the increase in density, it is becoming indispensable to verify the logic by simulation before manufacturing an actual device in terms of development period and cost.

Initially, the logic simulation was realized by software, but with the increase in the size of the circuit to be verified, a dedicated engine for executing the logic simulation by hardware has been developed and partially put into practical use. These dedicated engines generally employ a multiprocessor system using a plurality of general-purpose 8- to 32-bit microprocessors, and divide the circuit under test into several partial circuits to execute simulations to improve processing speed. ing. However, in general, during the execution of a simulation, it is necessary to synchronize each processor at each simulation time (time slot) in order to guarantee the validity of the result, and the waiting time of each processor increases depending on the method of dividing circuit data. On the contrary, there is a possibility that the processing speed is deteriorated.

[Conventional technology]

Generally, the division of circuit data is processed based on the following two basic principles.

(1) Minimize the traffic between processors.

(2) The number of elements evaluated by each processor at each simulation time is averaged.

The conventional circuit data division method extracts a plurality of series-connected element groups consisting of elements connected in cascade from each input terminal from circuit data of a circuit under test based on connection information of the circuit under test. Means for dividing into groups, means for distributing elements other than this series-connected element group to each group, and a threshold in which the difference between the maximum value and the minimum value of the number of elements is set in advance by comparing the number of elements included in each group. Means for re-distributing the circuit data so as to be smaller than the value, thereby dividing the circuit data.

[Problems to be solved by the invention]

As described above, in the conventional circuit data division method for logic simulation, when the series-connected element group from the input terminal and the element group branched therefrom are processed by different processors, the validity of the simulation result during the simulation is executed. Each processor must synchronize in order to guarantee the performance, but no special measures are taken to reduce the number of times that synchronization is required. Also, since only the number of elements is simply averaged and the input pattern information is not taken into account, it is difficult to average the number of executions of the processing for evaluation actually performed by each processor at each simulation time, and the There is a disadvantage that the operation rate is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit data division method for logic simulation that can reduce the number of synchronizations and the amount of communication between processors and improve the operation rate of the processors.

[Means for solving the problem]

In the circuit data division method for logic simulation of the present invention, the priority is given to the input terminals of the circuit under test in descending order of the product value of the number of edges of the applied input pattern and the number of fanouts when the input buffer is removed. Input terminal priority assigning means for assigning, element classifying means for classifying elements constituting the circuit under test into zero delay elements and delay elements according to delay values, and the input terminal based on connection information of the circuit under test. A series-connected element group extracting means for extracting a series-connected element group consisting of cascade-connected elements from each input terminal according to the priority given by the priority assigning means to form a plurality of groups; Have multiple fan-outs in each series-connected element group according to the priority order of the input terminals included in the series-connected element group until they are sorted into A direct-connected element group extracted from the extension element and connected in cascade is extracted and assigned to a group different from the delay element, and a series connection element branched from the zero delay element having a plurality of fanouts and connected in cascade. A remaining element grouping means for extracting a group and assigning it to the same group as the zero delay element, and a threshold for presetting a difference between a maximum value and a minimum value of the number of elements by comparing the number of elements included in each group. Element number averaging means for changing the series-connected element group from the delay element of the group having the largest number of elements to the group having the smallest number of elements until the value becomes smaller than the value.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional block diagram of a circuit data division system for logic simulation showing one embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes an input terminal priority assigning means;
Denotes element classification means, 13 denotes a series connection element group extraction means, 14 denotes remaining element grouping means, and 15 denotes element number averaging means.

The input terminal priority assigning means 11 supplies, to each input terminal of the circuit to be verified, the number of edges (the number of rising and falling edges) of the input pattern applied thereto and the fan-out (output transmission) when the input buffer is removed. First) priorities are assigned in descending order of the product of numbers.

The element classifying means 12 classifies the elements constituting the circuit under verification into a zero delay element and a delay element according to the delay value.

The series-connected element group extracting means 13 is a series-connected element consisting of elements connected in cascade from each input terminal in accordance with the connection information of the circuit to be verified and the order of priority given by the input terminal priority giving means 11. The groups are extracted, and each group is formed to divide the circuit under test into a plurality of groups.

The remaining element grouping means 14 sequentially generates a plurality of fan-outs in each series-connected element group according to the priority order of the input terminals included in the series-connected element group until all the elements are assigned to one of the groups. A series connected element group consisting of elements cascaded from the element having delay and having a cascade connection is extracted and assigned to a different group from the element having delay at the branch source. Similarly, a branch is made from a zero delay element having a plurality of fan-outs, a series-connected element group connected in cascade is extracted, and is assigned to the same group as the branch source zero delay element.

The element number averaging means 15 compares the number of elements included in each group, and until the difference between the maximum value and the minimum value of the element number becomes smaller than a preset threshold value, the group having the largest number of elements Of the serially connected element group from the delay element having the same number is changed to the group having the smallest number of elements.

FIG. 2 shows the input terminal priority assigning means shown in FIG.
11 is a flowchart showing the flow of the processing of Step 11. In this means, for each input terminal, the product of the fan-out number of the input terminal when the buffer is removed and the edge number of the input pattern of the input signal applied to the input terminal is calculated (step 21). This operation is performed for all input terminals (step 22). When the calculation is completed for all the input terminals, the input terminals are sorted in descending order of the value according to the calculated product, and priorities are assigned.

FIG. 3 is a flowchart showing the flow of processing of the element classification means 12 shown in FIG. In this means, the elements constituting the circuit to be verified are classified into zero delay elements and delay elements according to their delay values (step 31). This is performed for all elements (steps 32 and 33).

FIG. 4 is a flowchart showing the flow of the process of the series connection element extracting means 13 shown in FIG. By this means,
First, the value i of the internal counter is initialized (step 41), and an input terminal is selected as an active gate for searching for a circuit to be verified in accordance with the priority given by the input terminal priority assigning means 11 (step 42). Next, the active gate is assigned to the series-connected element group [i] (step 42). It is checked whether or not the active gate has a fan-out. If the active gate has a fan-out, the active gate is set as an arbitrary element of a fan-out destination (step 45), and the process returns to step 42, where the element is connected to a series-connected element group [ i]. This is repeated until the active gate has no fan-out, and the series-connected element group [i] is extracted to form the group [i].
Next, this operation is repeated until all the input terminals have been processed (steps 46, 47, 48) to form a plurality of groups.

FIG. 5 is a flowchart showing the flow of processing of the remaining element grouping means shown in FIG. In this means, it is checked whether there is a delay element having a plurality of fan-outs in the series-connected element group according to the priority order of the input terminals included in the series-connected element group (step 51). Then, a series connected element group from the fan-out destination element branched from the delay element is extracted and assigned to a different group from the delay element at the branch source (step 52). This process is performed for all delay elements having a plurality of fan-outs in the series connection element group. Next, according to the priority order of the input terminals included in the series connection element group, it is checked whether there is a zero delay element having a plurality of fan-outs in the series connection element group (step 53). A series-connected element group from the element at the fan-out destination is extracted and assigned to the same group as the zero-delay element at the branch source (step 54).
This is processed for all the zero delay elements having a plurality of fanouts in the series connection element group. The above-described extraction of the series-connected element group from the delay element and the zero delay element and the assignment to the group are repeated until all the elements are assigned to the group.

FIG. 6 is a flowchart showing a flow of processing of the element number averaging means 15 shown in FIG. In this means, first, the number of elements included in each group is calculated, and whether the difference between the maximum number of elements (max) and the minimum number of elements (min) is larger than a preset threshold ε is determined. It is checked whether it is (step 61). If the number is large, a series-connected element group from the delay elements having a plurality of fanouts is extracted from the group having the largest number of elements, and is assigned to the group having the smallest number of elements. The above-described processing is performed using the threshold value ε
Repeat until smaller.

〔The invention's effect〕

As described above in detail, according to the present invention, the series-connected element group branched from the zero-delay element is classified into the same group as the series-connected element group from the input terminal. Only the serially connected element group from the delay elements is assigned.
Therefore, it is sufficient to synchronize between different processors only when evaluating the serially connected element group from the delay elements, and the number of times of occurrence of synchronization can be reduced as compared with the case of the conventional circuit data division method, and the communication volume between the processors can be reduced. And the waiting time of each processor can be reduced. In addition, priorities are assigned to input terminals by using input pattern information of a signal which has the greatest influence on the number of times the processor actually executes processing during a logic simulation. By allocating to processors, it becomes easier to average the number of executions of processing for evaluation actually performed by each processor at each simulation time, and therefore, it is possible to improve the operation rate of the processor and reduce the processing time. There is an effect.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of an embodiment of the present invention, FIG. 2 is a flowchart showing the flow of processing of the input terminal priority assigning means of FIG. 1, and FIG. 3 is processing of the element classifying means of FIG. 4, FIG. 4 is a flowchart of the processing of the series-connected element group extracting means shown in FIG. 1, FIG. 5 is a flowchart of the processing of the remaining element grouping means shown in FIG. 1, and FIG. 6 is a flowchart of FIG. It is a flowchart of the processing of the number-of-elements averaging means shown. 11 ... input terminal priority assigning means, 12 ... element classification means, 13 ... series-connected element group extraction means, 14 ... remaining element grouping means, 15 ... element number averaging means.

Claims (1)

(57) [Claims] An input terminal priority assigning unit assigns priorities to input terminals of a circuit to be verified in accordance with a larger value of a product of the number of edges of an applied input pattern and the number of fanouts when an input buffer is removed. Means, an element classifying means for classifying elements constituting the circuit under test into a zero delay element and a delay element according to a delay value, and the input terminal priority assigning means based on connection information of the circuit under test. A series-connected element group extracting means for extracting a series-connected element group composed of elements connected in cascade from each input terminal according to the priority order to form a plurality of groups; and a series-connected element until all elements are sorted into groups. Direct connections cascaded from the delay elements with multiple fanouts in each series connection element group according to the priority of the input terminals included in the group. An element group is extracted and assigned to a different group from the delay element, and a series connection element group branched from a zero delay element having a plurality of fanouts and connected in cascade is extracted, and the same element as the zero delay element is extracted. The remaining element grouping means to be assigned to the group and the group having the largest number of elements until the difference between the maximum value and the minimum value of the number of elements is smaller than a preset threshold value by comparing the number of elements included in each group. A circuit number dividing means for changing the serially connected element group from the delay element to the group having the smallest number of elements.