JP2875711B2 - Program conversion device and processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program conversion device for converting a high-level language program into a machine language program, and
The present invention relates to a processor that executes the machine language program.

[0002]

2. Description of the Related Art With the recent development of electronic technology, information processing devices such as microprocessors have become widespread and are used in all fields. . As a conventional processor, for example, Iwao Morishita, "Microprocessor hardware"
(November 9, 1984, Iwanami Shoten),
There is a 16-bit processor of the segment address system.

The 16-bit processor of the segment address system has a segment register for storing an upper address including bits higher than 16 bits.
Address space greater than 4 kilobytes can be handled. That is, the entire address space exceeding 64 kilobytes is divided into 64 kilobyte units called segments, and a number is assigned to each segment. The address is managed by the segment number stored in the segment register and the distance (offset) from the head of the segment represented by 16 bits, which is the same as the data bit width. Thus, in the 16-bit processor of the segment address system, the data bit width is 16 bits and 6 bits.
Address space greater than 4 kilobytes can be handled.

Further, as a conventional processor, there is a 32-bit processor shown in the same book. This 32-bit processor manages a 32-bit address in the same way as 32-bit data, and can handle a 4-gigabyte address space. The machine language program executed on such a processor is generated by a program conversion device such as a compiler.

[0005] Compilers for the 16-bit processor include a large model method and a near-far model method for address management. A compiler adopting the large model method always sets a pointer variable by pairing a segment register with a 16-bit offset. For this reason, the processor that executes the object code by this compiler requires the operation of calculating and updating the contents of the segment register every time the address is calculated, and the performance is significantly degraded as compared with a 16-bit processor that does not employ the segment address method. It has the disadvantage of doing so.

A compiler adopting the near-far model method solves the above-mentioned disadvantages in the large model method as follows. In this method, two types of pointer variables can be designated: a near pointer variable for accessing the same segment and a far pointer variable for accessing over a segment boundary. The compiler uses 16 for near pointer variables.
Only the bit offset is set, and the far pointer variable is set by pairing the segment register and the 16-bit offset. The programmer selects whether to use the near pointer variable or the far pointer variable.

In the near-far model system, the performance is improved as compared with the large model system in the case of using the near pointer variable, but it is necessary for the programmer to recognize the segment boundary when creating a program and to use two types of pointer variables properly. However, there is a new problem that the program development efficiency is significantly reduced. On the other hand, compilers for 32-bit processors do not have the above problems. That is, since the compiler sets a 32-bit address for the pointer variable as well as the 32-bit data variable, there is no need for the programmer to recognize the segment boundaries, so that the program development efficiency is not reduced. Further, the processor that executes the compiled program does not cause performance degradation due to address calculation. And it can handle a huge address space of 4 gigabytes.

[0008]

However, according to the processor and the program conversion device of the prior art, a 32-bit data width is not required for an application using an embedded microcomputer, and the application is not required. Most do not require gigabytes of address space. In many applications,
A data width of 16 bits is sufficient, but an address space of 64 kilobytes is insufficient. In view of this situation, in applications where the data bit width is required to be 16 bits and the address space requires 64 KB or more but does not require a size as large as 4 gigabytes, an optimal microcomputer and compiler are required. There was a problem that there was no.

More specifically, since a 32-bit processor has hardware for processing 32-bit data and addresses, the hardware becomes excessive and the cost and power consumption increase. have. In the 16-bit processor, the management of the address space cannot avoid the performance deterioration in the address calculation as described in the related art. Further, since the programmer needs to recognize the segment boundaries, the development efficiency of the program is reduced.

A compiler for a 32-bit processor uses a machine instruction having a basic word length of 16 bits or 32 bits, and requires a 32-bit address designation in a program, thereby increasing the code size of the program. . When the bit width of the data bus connecting the 32-bit processor and the memory is 16 bits, 32 bits are used.
There is also a problem that the performance is significantly deteriorated as compared with the bit.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has as its object to provide a program conversion device and a processor suitable for an application in which a data bit width is 16 bits and an address space of about 16 megabytes is required.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a program conversion apparatus according to the present invention is intended for a processor which handles an address having a bit width longer than an effective bit width in a main data type, and uses a high-level language. A program conversion device for generating a machine language instruction based on a program, comprising: parameter holding means for holding an effective bit width and a bit width of an address in a main data type based on a user setting; When the variable used in the machine language instruction is a variable representing data, an instruction for validating the bit width of the data held by the parameter holding unit is generated, and when the variable is an address, the parameter holding unit holds the instruction. Generating means for generating an instruction for validating the bit width of the address.

The bit width M of the data may be 16, and the bit width N of the address may be 17 or more and 31 or less. Further, when the machine language instruction to be generated is an instruction for accessing a memory, the generation unit is configured to store the corresponding instruction stored in the parameter storage unit according to whether a variable to be accessed is data or an address. Memory management means for instructing that a bit width to be used should be an access width, and when a machine language instruction to be generated is an instruction using a register, whether a variable read or written to the register is data or an address. And register management means for instructing that the corresponding bit width held in the parameter holding means should be made valid. If the machine language instruction to be generated is an instruction that uses an immediate value, the immediate value is Immediate value management means for instructing that an immediate value of the corresponding bit width held in the parameter holding means be used depending on whether the data is an address or an address. Memory management unit, the register managing unit, according to an instruction from the immediate managing means may consist of a code generating means for generating machine after instruction.

A processor according to the present invention is a processor for executing a program generated by the above-mentioned program conversion device, and comprises an N-bit length program counter, an N-bit length operation, and a bit width M of data.
Execution means for executing a bit-length operation.

Here, N may be 24 and M may be 16.

[0016]

According to the above-mentioned means, in the program conversion device of the present invention, when the variable used in the machine language instruction to be generated is a variable representing data, the generating means sets the bit width of the data held by the parameter holding means. Generate an instruction to be valid. If it is a variable representing an address, an instruction for validating the bit width of the address held by the parameter holding unit is generated.

In the generation means, when the machine language instruction to be generated is an instruction for accessing a memory, the memory management means determines whether a variable to be accessed is data or an address. It instructs the code generation means that the corresponding bit width held in the parameter holding means should be used as the access width. The register management means is:
When the machine language instruction to be generated is an instruction that uses a register, the corresponding bit width held in the parameter holding unit is set according to whether the variable read or written to the register is data or an address. It instructs the code generation means to make it valid. When the machine language instruction to be generated is an instruction using an immediate value, the immediate value management means uses the immediate value of the corresponding bit width held in the parameter holding means according to whether the immediate value is data or an address. Instruct the code generation means what to do.

Further, the processor according to the present invention has N (24)
A 2 N (16 Mbytes) address space can be used by the bit-length program counter, and the execution means executes an operation of N (24) bits and an operation of M (16) bits, which is the data bit width. I can do it.

[0019]

FIG. 1 is a block diagram of a microcomputer and a program conversion device (hereinafter, abbreviated as a compiler; an information processing device including a microcomputer and a compiler) according to an embodiment of the present invention. In FIG. 1, the information processing apparatus includes a storage device 1 storing a C language program, a compiler 2 for translating a C language program into a machine language program, and hardware 3 for executing object code.

The compiler 2 comprises the following. 5
Is a syntax analysis unit that analyzes the syntax of the C language program and generates an intermediate file including an intermediate format statement and an intermediate code in which the program statement is converted into an intermediate format. A code generation unit 7 generates an object code based on the intermediate file.

Reference numeral 8 denotes a parameter setting unit which holds the bit width of an integer data variable and the bit width of a pointer variable. In the present embodiment, it is assumed that the bit width of the integer type data variable is set to 16 bits and the bit width of the pointer variable is set to 24 bits in advance by the user. Reference numeral 9 denotes a memory management unit which designates a bit width for reading and writing from and to a memory in accordance with a type of a variable targeted by the load / store instruction to be generated by the code generation unit 7.

Reference numeral 10 denotes a register management unit, and a code generation unit 7
Specifies an effective bit width according to the type of a variable read / written from / to a register for an instruction using a register to be generated. Reference numeral 11 denotes an immediate value management unit, which instructs the bit width of the immediate value in the instruction code according to the type of the variable that is the immediate value for the instruction using the immediate value to be generated by the code generation unit 7.

The hardware 3 comprises the following. A memory 13 stores object codes and data used in programs. An address bus 14 has a bit width of 24 bits. Reference numeral 15 denotes a data bus having a bit width of 16 bits.

A bus control circuit 16 is an address bus 14.
It is connected to the memory 13 via the data bus 15 and reads out the object code stored in the memory 13 as an instruction one by one, and reads and writes data from and to the memory 13. Reference numeral 17 denotes an instruction control circuit, which is a program counter 1
9 to indicate an instruction address to the bus control circuit 16,
An instruction is received from the bus control circuit 16 and decoded.

The program counter 19 outputs a 24-bit instruction address. Reference numeral 18 denotes an operation execution circuit, which comprises a register file 20 and an operation unit 21. The register file 20 has a plurality of 24-bit registers. The arithmetic unit 21 executes a 24-bit arithmetic logic operation using the values held in the register file 20.

FIG. 2 shows a processing flow of the code generator 7. In step 20, data variables are extracted from the intermediate file, and a variable table (symbol table) containing information on each variable is created. FIG. 7 shows an example of the symbol table. In the figure, the symbol column allocates the symbol of the data variable, the type column allocates whether the data variable is of the integer type or the pointer type, the byte number column allocates the number of bytes of the data variable, and the head address column allocates the memory. And the register column shows the register name when a register is assigned.

In step 21, it is determined whether or not there is an intermediate instruction whose code has not been processed from the intermediate file. If so, the process proceeds to step 22; otherwise, the code generation ends. Step 22 reads one intermediate instruction in the order to be processed next from the intermediate file. Step 23 selects one or more machine instructions that implement one intermediate instruction.

Step 24 designates one machine language instruction to be processed next from the selected machine language instruction. Step 25 performs processing (hereinafter, referred to as individual processing) for generating an instruction code of one designated machine language instruction (hereinafter, referred to as individual instruction). A step 26 determines whether or not there is a next machine language instruction to be processed among the machine language instructions selected in the step 23. If so, return to step 24,
If not, the process returns to step 21.

FIG. 3 to FIG. 6 show the flow of the individual processing in step 25 described above. First, step 30 determines whether the individual instruction belongs to the type of load / store instruction,
If so, the memory management unit 9 is notified; otherwise, the process proceeds to step 31. FIG. 4 shows the processing flow of the memory management unit 9 receiving this notification. In FIG. 4, step 40 is to determine the variables to be loaded / stored with the memory in the individual instruction (load / store instruction)
Look up the symbol table to determine the type of the variable.

In step 41, it is determined whether the type of the variable is an integer type data variable or a pointer type data variable. If it is the former, the process proceeds to step 42, and if it is the latter, the process proceeds to step 43. A step 42 instructs the code generator 7 to generate a load / store instruction having a data width of 2 bytes to be accessed, and the process proceeds to a step 31.

In step 43, the code generator 7 is instructed to generate a load / store instruction having a data width of 3 bytes to be accessed, and the flow advances to step 31. Secondly, step 31 determines whether or not the individual instruction uses a register, and if so, notifies the register management unit 10; otherwise, proceeds to step 32. FIG. 5 shows a processing flow of the register management unit 10 when receiving this notification. In FIG. 5, a step 50 refers to a symbol table for a variable stored in a register used by the individual instruction and checks the type of the variable.

In step 51, it is determined whether the type of the variable is an integer type data variable or a pointer type data variable. If it is the former, the process proceeds to step 52, and if it is the latter, the process proceeds to step 53. A step 52 instructs the code generation unit 7 to generate an instruction for validating the lower 16 bits of the register to be used, and proceeds to a step 32.

In step 53, all the registers 2 to be used are used.
It instructs the code generation unit 7 to generate an instruction that makes 4 bits valid, and proceeds to step 32. Third, step 32 determines whether or not the individual instruction uses immediate data, and if so, notifies the immediate management unit 11; otherwise, proceeds to step 33. FIG. 6 shows a processing flow of the immediate value management unit 11 when receiving this notification.

In FIG. 6, step 60 is a step for variables that are immediate data used in the individual instruction.
Look up the symbol table to determine the type of the variable. In step 61, it is determined whether the type of the variable is an integer type data variable or a pointer type data variable. If the former is the former, the process proceeds to step 62, and if the latter is the latter, the process proceeds to step 63.

Step 62 instructs the code generator 7 to generate an instruction having an immediate value of 2 bytes, and proceeds to step 33. A step 63 instructs the code generator 7 to generate an instruction having an immediate value of 3 bytes, and proceeds to a step 33. Fourth, in step 33, if there is an instruction from the memory management unit 9, the register management unit 10, and the immediate value management unit 11, an instruction code of an individual instruction is generated according to the instruction.

The operation of the microcomputer and the program conversion device of the present embodiment configured as described above will be described below. For the sake of simplicity, a C language program stored in the storage device 1 will be described below as an example. The syntax analysis unit 5 extracts the C language program from the storage device 1, analyzes the syntax according to the grammar, and generates an intermediate file described in an intermediate format language. The image of this intermediate file is shown below. However, for convenience,
The description in the intermediate format has been rewritten to make sense.

Intermediate form statement 1: (int * a, b, c) Intermediate instruction 1: t1: = * a Intermediate instruction 2: t2: = t1 + b Intermediate instruction 3: t3: = t2 + 1 Intermediate instruction 4: c: = t3 The intermediate form statement 1 corresponds to the declaration statement int * a, b, c, and the intermediate instructions 1 to 4 correspond to the arithmetic expression c = * a + b + 1.

These intermediate form statements and intermediate instructions are respectively converted into object codes as follows.
When this intermediate file is input, the code generation unit 7
The data variables (including those without declarations) in the intermediate file are extracted, the type of each variable is examined, and if necessary, allocated to the memory, and the symbol table shown in FIG. 7 is created (FIG. 2). Step 20).

In the above example, the variables * a, b, c explicitly declared from the intermediate form statement 1 are extracted. For the variable * a declared as a pointer variable, since the bit width of the pointer variable is set to 24 bits in the parameter setting unit 8,
An area of 24 bits (3 bytes) is secured and allocated on the memory. The two variables b and c declared as integer data variables have 16 bits (2 bytes) in the memory, respectively, because the bit width of the integer data variables is set to 16 bits in the parameter setting unit 8. Are allocated and allocated. Here, the variables * a, b, c
Are allocated to areas of 3 bytes from address 1000, 2 bytes from address 1004, and 2 bytes from address 1006, respectively. However, one byte at address 1003 is an empty area.

Further, temporary variables t1, t
2, t3 is extracted. The temporary variables t1, t2, and t3 are each treated as an integer data variable according to the variable to be operated. Information about these variables is written to the symbol table. The contents of the symbol table are dynamically rewritten each time there is a change in register assignment or the like. FIG. 7 already shown shows the contents of the symbol table at this point. At this point, the register column and the head address column of the temporary variable are left blank because there is no assignment.

Thereafter, the code generator 7 generates a corresponding machine language instruction for each of the intermediate instructions as follows. << Intermediate instruction 1: t1: = * a >> The code generation unit 7 determines whether an intermediate instruction to be processed (unprocessed) remains in the intermediate file (Step 21 in FIG. 2). At this point, since intermediate instructions 1 to 4 remain, the process proceeds to step 22.

Next, the code generation unit 7 reads one head intermediate instruction among the unprocessed intermediate instructions (step 2).
2), select one or a plurality of machine language instructions that realize the intermediate instruction (step 23). The selection of one or more instructions that implement the intermediate instruction 1 in step 23 will be specifically described.

Intermediate instruction 1 reads "3 bytes from address 1000 to which pointer variable * a is assigned,
The content is read out as 2 bytes as an address and stored in a temporary variable t1. " Code generator 7
Selects a machine language instruction corresponding to the above in order to realize this content. That is, mo stored in the first address register with the address 1000 as immediate data
The v instruction, the mov instruction to read the contents (pointer) of * a as an address using the first address register to the second address register, and the data indicated by the pointer to the data register using the second address register The mov instruction is selected. The above first and second
It is assumed that A0 and A1 are assigned to the address register. This is entered in the symbol table.

<Generation of Individual Instruction> Further, the code generation unit 7 designates one instruction (individual instruction) to be processed from among the plurality of instructions (step 24), and generates an instruction code for the individual instruction. (Step 25). The generation of the instruction code of the individual instruction in step 25 will be specifically described with reference to the flowcharts of FIGS.

The code generation unit 7 determines that the individual instruction specified in step 24 is not a load / store instruction for memory access (step 30 in FIG. 3) but an instruction that uses the register A0. To the effect (step 31). The register management unit 10 refers to the symbol table (Step 50 in FIG. 5), and since the variable to be stored in the register A0 is a pointer (Step 5).
1) Instruct the code generation unit 7 to generate an instruction in which all 24 bits of the register are valid (step 53).

Further, since the individual instruction uses immediate data, the code generation unit 7 notifies the immediate management unit 11 of the fact (step 32). The immediate value management unit 11 refers to the symbol table (Step 60 in FIG. 6), and since the immediate value to be stored in the register A0 is a pointer (Step 6).
1) Instruct the code generation unit 7 to generate an instruction having immediate data of 3 bytes (step 6)
3).

According to the instructions from steps 53 and 63,
The code generator 7 generates the following instruction 1 corresponding to the individual instruction (step 33). Instruction 1: MOV # 001000, A0 Thereafter, the code generation unit 7 executes an instruction to generate the next instruction code among the plurality of instructions selected in step 23,
Remain (step 26), the process proceeds to step 24.

<Generation of Individual Instruction> The code generation unit 7
One instruction (individual instruction) to be processed is designated from the plurality of instructions (step 24), and an instruction code for the individual instruction is generated (step 25). The instruction code generation of the individual instruction in this step 25 is shown in FIGS.
This will be specifically described using the flow of FIG.

Since the individual instruction is a load / store instruction for accessing the memory, the code generation unit 7 notifies the memory management unit 9 (step 30 in FIG. 3). The memory management unit 9 refers to the symbol table (Step 40 in FIG. 4), and since the variable to be stored in the second register A1 is a pointer (Step 41), the access width in memory access is 3 bytes. The code generation unit 7 is instructed to generate a load instruction (step 43).

Further, since the individual instruction is an instruction using registers A0 and A1, the code generation unit 7 notifies the register management unit 10 of the fact (step 31). The register management unit 10 refers to the symbol table (step 50 in FIG. 5), and since the variable to be stored in the second register A1 is a pointer (step 51), all of the registers 24
The code generation unit 7 is instructed to generate an instruction whose bit is valid (step 53).

Thereafter, the code generator 7 proceeds to step 33 because the individual instruction does not use immediate data (step 32). According to the instructions from steps 43 and 53,
The code generator 7 generates the following instruction 2 corresponding to the individual instruction (step 33). Instruction 2: MOV @ A0, A1 Thereafter, the code generator 7 proceeds to step 24 because there is an instruction to generate the next instruction code among the plurality of instructions selected in step 23 (step 26). .

<Generation of Individual Instruction> For the individual instruction, the code generation unit 7 generates the next instruction 3 in the same manner as described above (steps 24 to 26). At this point, the temporary variable
At t1, a D0 register is assigned. Instruction 3: MOV @ A1, D0 Hereinafter, similarly to the above, the processing of each intermediate instruction in the loop of steps 21 to 26 is performed in steps 24, 25 (flows in FIGS. 3 and 4), and the processing of each individual instruction in steps 26, 26. Is performed, a detailed description is omitted and an outline is shown.

<< Intermediate instruction 2: t2: = t1 + b >> This intermediate instruction reads "2 bytes from address 1004 to which variable b is assigned, and adds the contents thereof to temporary variable t1 to temporarily Stored in variable t2. " First, the code generation unit 7 generates an instruction 4 for loading an address four addresses away from the address 1000 indicated by the contents of the A0 register corresponding to the individual instruction. At this time, the memory management unit 9 refers to the symbol table (step 40), and the individual instruction 4 loads an integer data variable (step 4).
1) Instruct that a load instruction having an access width of 2 bytes should be generated (step 42). Register management unit 10
Refers to the symbol table (step 50) and stores the integer type data in the register (step 5).
1) Instruct that an instruction in which the lower 16 bits of the register become valid should be generated (step 52). At this point, the variable b is stored in the register D1.

Instruction 4: MOV @ (04, A0), D1 Next, the code generation unit 7 determines a variable b stored in the D1 register corresponding to the individual instruction and a temporary variable t1 indicated by the contents of the D0 register. Is generated, and an instruction 5 for storing the result in the D1 register is generated. At that time, the register management unit 10
Referring to the symbol table (step 50), since the integer type data is stored in the register (step 51), it is instructed to generate an instruction in which the lower 16 bits of the register are valid (step 52). At this point, the register D1 is assigned to the temporary variable t2.

Instruction 5: ADD D0, D1 << Intermediate instruction 3: t3: = t2 + 1 >> This intermediate instruction has a content that "1 is added to temporary variable t2 and stored in temporary variable t3". I do. The code generation unit 7 generates the next instruction 6 to store the result of adding the 2-byte immediate value # 0001 and the register D1 in the D1 register in accordance with the instructions of the register management unit 10 and the immediate value management unit 11. At this point, the register D1 is assigned to the temporary variable t3.

Instruction 6: ADD # 0001, D1 << Intermediate instruction 4: c: = t3 >> This intermediate instruction is "write temporary variable t3 to 2-byte area from address 1006 to which variable c is allocated." The contents. Code generator 7
Generates the next instruction 7 for storing the contents of the register D1 at an address 6 addresses away from the address indicated by the contents of the register A1, according to the instruction of the memory management unit 9.

Instruction 7: MOV D1, @ (06, A0) Processing of each intermediate instruction is completed as described above. As a result, the following object code is output from the code generation unit 7 to the memory 13. On the memory 13, the instructions 1 to 7 respectively correspond to addresses 100000, 100005,
Address 100007, address 100008, address 10000a, address 10000b, 10
It shall be located at address 000f.

Instruction 1: Address 100000 MOV # 001000, A0 Instruction 2: Address 100005 MOV @ A0, A1 Instruction 3: Address 100007 MOV @ A1, D0 Instruction 4: Address 100008 MOV @ (04, A0), D1 Instruction 5: Address 10000a ADD D0, D1 Instruction 6: Address 10000b ADD # 0001, D1 Instruction 7: Address 10000f MOV D1, @ (06, A0) These instructions represent the object code in mnemonics (assembly language) for convenience. , Memory 1
3 is represented by a binary number. All the above numbers are hexadecimal. Hereinafter, an operation performed by the microcomputer for the object code arranged in the memory 13 will be described.

(Instruction 1: Address 100000 MOV # 001000, A0
The bus control circuit 16 and the instruction control circuit 17 output the value 100000 held by the program counter 19 to the address bus 14, and fetch and decode the instruction 1 via the data bus 15. Operation execution circuit 1 according to the decoding result
8 is the immediate value 001000 specified by the operand of instruction 1
From the instruction control circuit 17 and register file 2
Store it in A0 register of 0.

(Instruction 2: MOV @ A0, A1 at 100005) The bus control circuit 16 and the instruction control circuit 17 similarly fetch and decode the instruction 2. Arithmetic execution circuit 18
Reads the contents of the A0 register, outputs it to the address bus 14, reads the memory 13, and reads the data bus 15
Is stored in the lower 16 bits of the A1 register. Subsequently, the operation execution circuit 1
In 8, the arithmetic unit 21 adds 2 to the value 001000 of the A0 register, the bus control circuit 16 outputs the addition result 001002 to the address bus 14, reads the memory 13, and reads 8 via the data bus 15. The bit data is stored in the upper 8 bits of the A1 register.

(Instruction 3: MOV @ A1, D0 at address 100007) The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 3. The arithmetic execution circuit 18 reads the contents of the A1 register and outputs it to the address bus 14,
The memory 13 is read. Thereafter, the arithmetic execution circuit 18 converts the 16-bit value read via the data bus 15 to D0
It is stored in the lower 16 bits of the register. The D0 register is
The data pointed to by the pointer variable * a is held.

(Instruction 4: Address 100008 MOV @ (04, A0), D1
The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 4. The arithmetic execution circuit 18 receives the displacement value 04 from the instruction control circuit 17 and adds the displacement value 04 to the value 001000 of the A0 register read by the arithmetic unit 21, and outputs the addition result 001004 to the address bus 14 by the bus control circuit 16.
To read the data from the memory 13. After that, the arithmetic execution circuit 18 stores the 16-bit value read out to the data bus 15 in the lower one of the D1 register in the register file 20.
Stored in 6 bits. The D1 register holds the variable b.

(Instruction 5: ADD D0, D1 at address 10000a) The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 5. The arithmetic execution circuit 18 includes an arithmetic unit 21
, The value of the D0 register read from the register file 20 and the value of the D1 register are added, and the addition result is stored in the D1 register in the register file 20. The arithmetic unit 21 performs this addition with 24 bits, but the lower 16 bits of the D1 register are valid. The D1 register holds an added value of the data indicated by the pointer variable * a and the variable b.

(Instruction 6: address 10000b ADD # 0001, D1)
The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 6. The arithmetic execution circuit 18 includes the arithmetic unit 2
1, the value of the D1 register read from the register file 20 and the immediate value 00 received from the instruction control circuit 17.
01 is added, and the addition result is stored in the D1 register. The D1 register contains the data indicated by the pointer variable * a, the variable b, and the immediate value 0.
The value added to 001 is held.

(Instruction 7: address 10000f MOV D1, @ (06, A0)
The bus control circuit 16 and the instruction control circuit 17 fetch and decode the instruction 7. The operation execution circuit 18 receives the displacement position 06 from the instruction control circuit 17, adds the value 001000 of the A0 register read from the register file 20 in the operation unit 21, and adds the addition result 001006 to the bus control circuit 1.
6 and outputs the value of the lower 16 bits of the D1 register to the data bus 15, and writes 16-bit data to the memory 13.
At address 001006 of the memory 13, an added value of the data indicated by the pointer variable * a, the variable b, and the immediate value 0001 is written.

The object code generated by translating the C language program by the compiler 2 is
It is executed by hardware 3. As described above, according to the present embodiment, the compiler 2 manages the arrangement of all variables and the object code to be generated on the memory by using 24-bit addresses, and the microcomputer uses the 24-bit register file 20 and the arithmetic unit. Since these addresses are calculated at 21 and the memory 13 is accessed via the 24-bit address bus 14, the information processing apparatus of this embodiment can realize a completely uniform 16-megabyte address space which is not divided into segments. A programmer who writes a C language program does not need to be aware of spatial non-uniformity such as segment boundaries, and does not suffer from performance degradation in address calculations such as segment register operations. Along with that, the program development efficiency also improves.

The data bit width is 16 bits and 1
For an application requiring an address space of 6 megabytes, the information processing apparatus of the present embodiment uses a 24-bit register file 20 and a computing unit 21.
, There is no increase in cost and power consumption due to excessive hardware as in a conventional 32-bit processor.

The basic word length of the machine language instruction of the microcomputer is 8 bits, and even when the immediate value of the address is included in the instruction as in the above-mentioned instruction 1, the immediate value is at most 24 bits. 2 is much smaller than an information processing device of a 32-bit processor in which the basic word length of a machine language instruction is 16 or 32 bits and the immediate value of an address is a maximum of 32 bits. Also, compared to a 16-bit processor that can handle only a 64-kilobyte address space, the size of the object code hardly increases because the factor of the increase in the code size is only a maximum of 1 byte due to the immediate value of the address accompanying the instruction.

Although the width of the data bus 15 of the microcomputer of this embodiment is 16 bits, the value related to the 24-bit address stored in the register file 20 is stored in the memory 13 as compared with the case where the width is set to 24 bits. However, only the execution time becomes longer when reading and writing data, and this performance degradation is caused by the fact that the bit width of the data bus of an information processing device of a 32-bit processor that always reads and writes data in 32-bit memory is 16 bits. Very small compared to.

In this embodiment, the bit width of the address bus 14, the program counter 19, the register file 20, and the computing unit 21 of the microcomputer is set to 24 bits, and the bit width of the pointer variable of the parameter setting unit 8 of the compiler 2 is set to 24 bits. Although set to 24 bits, an arbitrary bit width of 17 bits to 31 bits may be set according to the required address space. The response is as follows.

Necessary address space Bit width 128 kilobytes 17 bits 256 kilobytes 18 bits 512 kilobytes 19 bits 1 megabyte 20 bits 2 megabytes 21 bits 4 megabytes 22 bits 8 megabytes 23 bits 16 megabytes 24 bits (this embodiment) 32 megabytes 25 bits 64 megabytes 26 bits 128 megabytes 27 bits 256 megabytes 28 bits 512 megabytes 29 bits 1 gigabyte 30 bits 2 gigabytes 31 bits By doing so, there is no extra hardware that exceeds the bit width of the address. Power consumption can be optimized.

Although the width of the data bus 15 of the microcomputer is 16 bits in this embodiment, it may be 24 bits. In the present embodiment, the address bus 14 of the microcomputer, the program counter 1
9. The bit width of the register file 20 and the arithmetic unit 21 and the set value of the bit width of the pointer variable of the parameter setting unit 8 of the compiler 2 are set to 24 bits, and the bit width of the data variable of the parameter setting unit 8 of the compiler 2 is set. Although the value is 16 bits, these bit widths are not limited. By making the latter equal to the bit width (M) of data of the type mainly handled by the program, and setting the former to a value larger than M (N), the information processing apparatus enables the bit width of data of the type mainly handled by the program. Can be expressed by 2
Can handle an address space of 2N bytes exceeding the space of M bytes.

In this embodiment, the type of the data variable for which the bit width is set by the parameter setting section 8 is an integer type. However, this type may be any type in accordance with the type of data mainly handled in a C language program. . In this embodiment,
It compiles and executes a C language program, but does not limit the language. By making the compiler 2 correspond to the description language of the program, the information processing apparatus can execute a program in any language.

[0074]

As described above, according to the present invention, the data width and the pointer width can be arbitrarily set in the parameter holding means, so that the programmer can recognize the nonuniformity of the space such as the boundary of the segment. It can handle any address space larger than the space that can be represented by the bit width of the data of the type to be handled, without any performance degradation in address calculation such as segment register operation. effective.

In an application using an embedded microcomputer, a data bit width is required to be 16 bits and an address space is 64 bits.
There is an effect that optimization can be achieved for a device that requires more than kilobytes but does not require a size of 4 gigabytes. Further, according to the present invention, the code size of the program is smaller than that of the conventional 32-bit processor, and the bit width of the data bus is 16 bits.
Even in the case of bits, there is an effect that an information processing apparatus with almost no performance degradation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 shows a processing flow of a code generation unit 7 in the embodiment.

FIG. 3 shows a flow of individual processing among processing flows of a code generation unit 7 in the embodiment.

FIG. 4 shows a processing flow of a memory management unit 9 in the embodiment.

FIG. 5 shows a processing flow of a register management unit 10 in the embodiment.

FIG. 6 shows a processing flow of an immediate value management unit 11 in the embodiment.

FIG. 7 shows a symbol table in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Storage device 2 Compiler 3 Hardware 5 Syntax analysis part 7 Code generation part 8 Parameter setting part 9 Memory management part 10 Register management part 11 Immediate value management part 13 Memory 14 Address bus 15 Data bus 16 Bus control circuit 17 Instruction control circuit 18 Operation Execution circuit 19 Program counter 20 Register file 21 Operation unit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-84735 (JP, A) JP-A-4-14144 (JP, A) V. Eiho et al., Translated by Kenichi Harada, "Compiler II: Principles, Techniques, and Tools", Science Co., Ltd., November 10, 1990, p. 483−485 (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/45 G06F 9/30

Claims (5)

(57) [Claims] 1. A program conversion apparatus for generating a machine language instruction based on a high-level language program for a processor that handles an address having a bit width N longer than an effective bit width M in a main data type, Parameter holding means for holding the effective bit width and the bit width of the address in the main data type based on the setting of the user, and when the variable used in the machine language instruction to be generated is a variable representing data, Generating means for generating an instruction for validating the bit width of the data held by the parameter holding means and generating an instruction for validating the bit width of the address held by the parameter holding means when the variable is an address. A program conversion device characterized in that: 2. The program conversion device according to claim 1, wherein a bit width M of the data is 16, and a bit width N of the address is 17 or more and 31 or less. 3. When the machine language instruction to be generated is an instruction for accessing a memory, the generation unit stores the instruction in a parameter storage unit according to whether a variable to be accessed is data or an address. A memory management means for instructing that the corresponding bit width to be used as an access width, and, when the machine language instruction to be generated is an instruction using a register, a variable read or written to the register is data. Register management means for instructing that the corresponding bit width held in the parameter holding means should be validated, depending on whether there is an address or an address; and if the machine language instruction to be generated is an instruction using an immediate value, Depending on whether the immediate value is data or an address,
Code management means for generating a machine language instruction in accordance with instructions from the immediate management means and the memory management means, the register management means and the immediate management means for instructing that an immediate value of the corresponding bit width held in the parameter holding means should be used; 3. The program conversion device according to claim 1, wherein the program conversion device comprises: 4. A processor for executing a program generated by the program conversion device according to claim 1, wherein the program counter has an N-bit length, an N-bit operation, and a data bit width. And an execution unit for executing an operation having an M-bit length. 5. The processor according to claim 3, wherein said N is 24.