JP2862081B2 - IC chip mounting structure - Google Patents
IC chip mounting structureInfo
- Publication number
- JP2862081B2 JP2862081B2 JP10023462A JP2346298A JP2862081B2 JP 2862081 B2 JP2862081 B2 JP 2862081B2 JP 10023462 A JP10023462 A JP 10023462A JP 2346298 A JP2346298 A JP 2346298A JP 2862081 B2 JP2862081 B2 JP 2862081B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring
- mounting structure
- connection
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＩＣチップの実装構
造に関する。詳しくはプラズマディスプレイや液晶など
の平板形表示装置のパネル基板に直接ＩＣチップを搭載
する場合等に用いられるＩＣチップの実装技術に関す
る。The present invention relates to an IC chip mounting structure. More specifically, the present invention relates to an IC chip mounting technique used when an IC chip is directly mounted on a panel substrate of a flat panel display device such as a plasma display or a liquid crystal display.
【０００２】ＩＣはその機能の拡大に伴い、端子数の増
大と端子ピッチの縮小化が益々進みつつある。このため
ＩＣパッド端子と配線基板との接続手法も、ＴＡＢ（テ
ープオートメイテッドボンディング）方式などにより多
端子、ファインピッチ端子に対する接続方法として採用
されて来ている。しかしながらこの方式においても複雑
で多様な配線基板への接続に対する要求を満たしきれる
ものではない。このため多端子、ファインピッチのＩＣ
チップと、複雑で多種多様な配線基板への電気的接続を
可能とする実装方法が要求されている。[0002] As the functions of ICs have been expanded, the number of terminals and the pitch of terminals have been increasingly reduced. For this reason, a connection method between an IC pad terminal and a wiring board has been adopted as a connection method for multiple terminals and fine pitch terminals by TAB (tape automated bonding) or the like. However, even this method cannot satisfy the requirements for connection to complicated and various wiring boards. For this reason, multi-terminal, fine-pitch ICs
There is a demand for a mounting method that enables electrical connection to a chip and a variety of complicated wiring boards.
【０００３】[0003]
【従来の技術】以下平板形表示パネルの実装構造を例に
とり説明する。平板形表示パネルのドライバ用ＩＣチッ
プをパネル基板端面に直接搭載する実装技術（ＣＯＧ方
式など）は、表示ユニットの小型化、低価格化を実現す
る方式として開発が進められている。現在までに開発さ
れている方式は、パネル基板上に形成されているマトリ
クス表示電極と制御用の信号配線および電源配線に対し
て、図５（ａ）の如くＩＣチップ１をパネル基板２上に
フェースアップ状に配置しＩＣパッド電極端子からワイ
ヤ３によりワイヤボンディングすることにより電気的接
続を行うか、あるいは図５（ｂ）に示すように、ＩＣチ
ップ１をパネル基板２上にフェースダウン状に配置し、
予めＩＣパッド電極端子上に形成されたバンプ４により
直接接続を行う方式などが考えられている。何れにして
も、パネル基板上に全ての電気配線が形成されており、
これらとＩＣパッド電極端子との接続をとる実装形態に
なっている。2. Description of the Related Art A mounting structure of a flat display panel will be described below as an example. 2. Description of the Related Art A mounting technology (such as a COG method) for directly mounting a driver IC chip of a flat panel display panel on an end face of a panel substrate is being developed as a method for realizing miniaturization and cost reduction of a display unit. In the method developed up to now, the IC chip 1 is mounted on the panel substrate 2 as shown in FIG. 5A with respect to the matrix display electrodes formed on the panel substrate and the control signal wiring and the power supply wiring. The IC chip 1 is placed face-up and electrically connected by wire bonding from the IC pad electrode terminal with a wire 3 or, as shown in FIG. 5B, the IC chip 1 is placed face-down on the panel substrate 2. Place,
A method of directly connecting with a bump 4 formed on an IC pad electrode terminal in advance has been considered. In any case, all the electrical wiring is formed on the panel substrate,
The mounting form is such that these are connected to the IC pad electrode terminals.
【０００４】[0004]
【発明が解決しようとする課題】上記従来の配線方式で
は、パネル基板上の信号線および電源供給線は複数本あ
って、これらを並列させてＩＣチップに供給する必要が
あるため、クロスオーバーを施した多層配線形態を採ら
ざるを得なくなる。パネル基板の製造工程において、こ
のクロスオーバー多層配線は、例えば２層配線の場合、
最下層配線を形成した後、配線のクロス部分に絶縁層を
形成し、その上に次の配線層を形成するという複雑な工
程が必要になる。配線層数が増えれば、さらに工程が複
雑化するのは明らかであり、この結果、従来のＩＣチッ
プを搭載しない構造に比べて、工程数の増加、歩留り低
下などにより価格が上昇し、低価格化を達成できないと
いう問題が発生する。In the above conventional wiring method, there are a plurality of signal lines and power supply lines on the panel substrate, and it is necessary to supply these in parallel to the IC chip. It is inevitable to adopt a multi-layered wiring configuration. In the manufacturing process of the panel substrate, this crossover multilayer wiring is, for example, a two-layer wiring,
After forming the lowermost wiring, a complicated process of forming an insulating layer in a cross portion of the wiring and forming a next wiring layer thereon is required. Obviously, if the number of wiring layers increases, the process becomes more complicated. As a result, compared to a structure without a conventional IC chip, the cost increases due to an increase in the number of processes and a decrease in yield, resulting in lower cost. The problem that the conversion cannot be achieved occurs.
【０００５】そこで、以上のパネル基板上の多層配線を
避ける方法として、ＩＣチップは直接パネル基板上に搭
載するが、配線層のみ別基板で製作し、この配線基板を
パネル基板の端部に熱圧着する等して接続する方法も考
えられているが、接続端子数が増えるので、低価格化、
高信頼化のメリットはなくなる。Therefore, as a method of avoiding the above-mentioned multilayer wiring on the panel substrate, the IC chip is directly mounted on the panel substrate, but only the wiring layer is manufactured on a separate substrate, and this wiring substrate is heated to the end of the panel substrate. A method of connecting by crimping or the like is also considered, but since the number of connection terminals increases, cost reduction,
There is no merit of high reliability.
【０００６】さらに、従来の直接実装法（ＣＯＧ方式）
では、パネル基板の端面部分において、ＩＣチップを実
装する面積と、このＩＣチップへの制御信号および電源
配線を施すための配線エリアが必要になっていたため、
全体の実装エリアの面積、すなわち表示部以外の“額
縁”部の面積が大きくなってしまい、小型化のメリット
が半減するという問題があった。Further, a conventional direct mounting method (COG method)
Therefore, an area for mounting an IC chip and a wiring area for providing a control signal and a power supply wiring to the IC chip are required in an end portion of the panel substrate.
There is a problem that the area of the entire mounting area, that is, the area of the "frame" portion other than the display portion becomes large, and the advantage of miniaturization is reduced by half.
【０００７】本発明は、ファインで多くのパッド端子を
有するＩＣチップと、複雑で多種多様な配線基板への電
気的接続を可能とし、且つＩＣチップと配線部を含めた
実装エリアの小型化及び高信頼化が可能なＩＣチップの
実装構造を実現しようとする。The present invention makes it possible to make an electrical connection to an IC chip having many fine pad terminals and a complicated and diverse wiring board, and to reduce the mounting area including the IC chip and the wiring portion. An attempt is made to realize an IC chip mounting structure capable of achieving high reliability.
【０００８】[0008]
【課題を解決するための手段】本発明のＩＣチップの実
装構造においては、ＩＣチップと、該ＩＣチップと電気
的な接続を行うための複数の配線基板とを備えたＩＣチ
ップの実装構造であって、該ＩＣチップは、該ＩＣチッ
プの一の主面に設けられた複数のパッド電極について、
該複数の配線に対してそれぞれ異なる接続方式にて接続
されてなることを特徴とする。また、それに加えて、前
記異なる接続方式は、ワイヤボンディング、バンプ接
続、導電性接着剤による接続、および導電性粒子の単体
または複数の集合体による接続の中から選ばれる接続方
式を含むことを特徴とする。According to the present invention, there is provided an IC chip mounting structure comprising an IC chip and a plurality of wiring boards for electrically connecting the IC chip. The IC chip has a plurality of pad electrodes provided on one main surface of the IC chip.
The plurality of wirings are connected by different connection methods. In addition, the different connection methods include a connection method selected from wire bonding, bump connection, connection using a conductive adhesive, and connection using a single or a plurality of aggregates of conductive particles. And
【０００９】また、それに加えて、ＩＣチップと、該Ｉ
Ｃチップと電気的な接続を行うための複数の配線基板と
を備えたＩＣチップの実装構造であって、該ＩＣチップ
は、該複数の配線基板に対して、高さまたは大きさが異
なるバンプまたは導電性粒子の単体あるいは複数の集合
体を用いて接続されてなることを特徴とする。また、そ
れに加えて、ＩＣチップと、該ＩＣチップと電気的な接
続を行うための複数の配線基板とを備えたＩＣチップの
実装構造であって、該ＩＣチップは、該複数の配線基板
に対して、弾力性のあるバンプまたは導電性粒子の単体
あるいは複数の集合体を用いて接続されてなることを特
徴とする。[0009] In addition, an IC chip and the I chip
An IC chip mounting structure including a C chip and a plurality of wiring boards for making an electrical connection, wherein the IC chip has bumps having different heights or sizes with respect to the plurality of wiring boards. Alternatively, the conductive particles are connected using a single or a plurality of aggregates of conductive particles. Further, in addition to the above, an IC chip mounting structure including an IC chip and a plurality of wiring boards for electrically connecting the IC chip, wherein the IC chip is mounted on the plurality of wiring boards. On the other hand, it is characterized by being connected using a single or a plurality of aggregates of elastic bumps or conductive particles.
【００１０】また、それに加えて、ＩＣチップと、該Ｉ
Ｃチップと電気的な接続を行うための複数の配線基板と
を備えたＩＣチップの実装構造であって、該複数の配線
基板は、多層配線構造を有する該ＩＣチップを搭載する
第１の基板と、同一配線層に並行的に複数の配線が設け
られた単層配線構造を有するフレキシブル基板からなる
第２の基板とを含み、該第２の基板は、該ＩＣチップが
搭載される該第１の基板上に貼りつけられてなり、該第
１、第２の基板上の端子は、該ＩＣチップの対応する端
子にそれぞれ接続されてなることを特徴とする。[0010] In addition, an IC chip and the I
A mounting structure of an IC chip including a C chip and a plurality of wiring boards for making electrical connection, wherein the plurality of wiring boards are a first substrate on which the IC chip having a multilayer wiring structure is mounted. And a second substrate made of a flexible substrate having a single-layer wiring structure in which a plurality of wirings are provided in parallel on the same wiring layer, wherein the second substrate has the second substrate on which the IC chip is mounted. One terminal is attached to one substrate, and terminals on the first and second substrates are connected to corresponding terminals of the IC chip, respectively.
【００１１】また、それに加えて、複数の表示電極端子
を有する表示パネルのパネル基板と、該表示電極端子と
電気的に接触されるＩＣチップとを備えたＩＣチップの
実装構造であって、複数の制御信号線または電源線を形
成された少なくとも１つの配線基板を有し、該ＩＣチッ
プは、該パネル基板または該配線基板上に搭載され、該
パネル基板上の表示電極端子および、該配線基板上の制
御信号線または電源線端子は、該ＩＣチップの対応する
端子近傍に設けられ、それぞれ対応する端子間を接続さ
れてなることを特徴とする。Further, in addition to the above, there is provided an IC chip mounting structure including a panel substrate of a display panel having a plurality of display electrode terminals, and an IC chip electrically connected to the display electrode terminals. The IC chip is mounted on the panel substrate or the wiring substrate, the display electrode terminal on the panel substrate, and the wiring substrate. The upper control signal line or the power supply line terminal is provided near the corresponding terminal of the IC chip, and is connected between the corresponding terminals.
【００１２】この構成を採ることによりファインで多く
のパッド端子を有するＩＣチップと複雑で多種多様な配
線基板への電気的接続を可能とし、且つＩＣチップと配
線部を含めた実装エリアの小型化及び高信頼化が可能な
ＩＣチップの実装構造が得られる。By adopting this configuration, it is possible to electrically connect a fine IC chip having many pad terminals and various complicated wiring boards, and to reduce the mounting area including the IC chip and the wiring section. In addition, a mounting structure of the IC chip which can achieve high reliability can be obtained.
【００１３】[0013]
【作用】本発明では、図１に示すようにＩＣチップ１２
と複数の配線基板１０，１１との接続に、ワイヤボンデ
ィング、熱圧着あるいは接着剤等の異なる接続方法、ま
たは図３に示すサイズを異ならせたり、弾力性を持たせ
たバンプや導電性粒子３５を用いることにより、複雑多
様な接続を行うことが可能となる。According to the present invention, as shown in FIG.
In connection with the plurality of wiring boards 10 and 11, different connection methods such as wire bonding, thermocompression bonding, or an adhesive, or bumps or conductive particles 35 having different sizes or elasticity as shown in FIG. , It is possible to make complex and diverse connections.
【００１４】[0014]
【実施例】図１は本発明の第１の実施例を示す図で、
（ａ）は平面図、（ｂ）は（ａ）図のｂ−ｂ線における
断面図である。本実施例は、同図に示すように、第１の
配線基板１０に対し、ＩＣチップ１２をダイボンディン
グし、この第１の配線基板１０上の配線３３とＩＣチッ
プ１２のパッド電極１３とをワイヤ１５によりワイヤボ
ンディングして接続する。この後さらに第２の配線基板
１１をＩＣチップ１２上に配置し、この第２の配線基板
１１上のリード端子３４と、ＩＣチップのパッド電極１
３とを直接接続する。FIG. 1 is a view showing a first embodiment of the present invention.
3A is a plan view, and FIG. 3B is a cross-sectional view taken along line bb in FIG. In this embodiment, as shown in the figure, an IC chip 12 is die-bonded to a first wiring board 10, and a wiring 33 on the first wiring board 10 and a pad electrode 13 of the IC chip 12 are connected. The wires 15 are connected by wire bonding. Thereafter, the second wiring board 11 is further arranged on the IC chip 12, and the lead terminals 34 on the second wiring board 11 and the pad electrodes 1 of the IC chip are formed.
3 is directly connected.
【００１５】直接接続する具体的な方法は、導電性接着
剤を用いて接着するか、バンプや導電性粒子の単体また
は複数の集合体を介在させて接続することができる。こ
のパンプや導電性粒子による接続は、熱圧着や接着剤に
より圧接接続か、あるいは導電性接着剤により行う。以
上の接続後、環境に対する保護を図るため、ＩＣチップ
近傍に防湿保護樹脂を塗布する。なお、前記導電性粒子
には導電性樹脂を用いることができる。このように構成
された本実施例は次に述べる本実施例の応用例の如き効
果を発揮する。As a specific method of direct connection, bonding can be performed using a conductive adhesive, or connection can be performed with a single bump or a plurality of aggregates of conductive particles interposed therebetween. The connection by the pump or the conductive particles is performed by pressure bonding by thermocompression bonding or an adhesive, or by a conductive adhesive. After the above connection, in order to protect the environment, a moisture-proof protective resin is applied near the IC chip. Note that a conductive resin can be used for the conductive particles. The present embodiment configured as described above has effects as in the following application examples of the present embodiment.
【００１６】図２は上記第１の実施例の応用例を示す図
で、（ａ）は斜視図、（ｂ）は（ａ）図のｂ−ｂ線にお
ける断面図である。本応用例は、第１の実施例を平板形
表示パネルに応用した例である。同図において、２８は
パネル基板、２９は配線基板、１２はドライバＩＣチッ
プであり、該ＩＣチップ１２はパネル基板２８上に搭載
され、配線基板２９はパネル基板２８の端部表面の所定
の場所に搭載接着されている。FIGS. 2A and 2B show an application of the first embodiment. FIG. 2A is a perspective view, and FIG. 2B is a sectional view taken along line bb in FIG. This application example is an example in which the first embodiment is applied to a flat panel display panel. In the figure, 28 is a panel substrate, 29 is a wiring substrate, and 12 is a driver IC chip. The IC chip 12 is mounted on the panel substrate 28, and the wiring substrate 29 is located at a predetermined position on the end surface of the panel substrate 28. Mounted and bonded.
【００１７】そしてドライバＩＣチップ１２の入力パッ
ド電極２３と配線基板２９との接続は、配線基板２９よ
り延長したリード端子３４と各パッド２３上あるいはリ
ード端子３４上に形成したバンプ３５を介した熱圧着に
より接続されている。また、熱圧着によらず、導電性接
着剤を用いて端子部分を固着させる方法をとることもで
きる。このようなギャングボンディングを用いれば、多
端子の接続時間を短縮することができる。パネルの表示
電極端子３０とＩＣチップ１２の出力パッド電極２５と
の接続はワイヤボンディングにより接続している。The connection between the input pad electrode 23 of the driver IC chip 12 and the wiring board 29 is performed by using the lead terminals 34 extending from the wiring board 29 and the bumps 35 formed on the pads 23 or on the lead terminals 34. They are connected by crimping. Further, instead of using thermocompression bonding, a method of fixing the terminal portion using a conductive adhesive can be adopted. By using such gang bonding, the connection time of multiple terminals can be reduced. The display electrode terminals 30 of the panel and the output pad electrodes 25 of the IC chip 12 are connected by wire bonding.
【００１８】このように構成された本応用例は次の様な
効果も有する。即ち、配線基板とＩＣチップの接続にお
いて、長尺の配線基板２９に対して複数のＩＣチップ１
２のリード端子３４を全てボンディングしておき、配線
基板２９と一体形に構成されたＩＣチップ１２の出力パ
ッド電極２５と表示電極端子３０との接続をワイヤボン
ディングで行えば、量産性を向上することができる。The application example thus configured also has the following effects. That is, in the connection between the wiring board and the IC chip, a plurality of IC chips 1
If the output pad electrodes 25 of the IC chip 12 formed integrally with the wiring board 29 and the display electrode terminals 30 are connected by wire bonding, the mass productivity is improved. be able to.
【００１９】図３は本発明の第２の実施例を示す図で、
（ａ）は平面図、（ｂ）は（ａ）図のｂ−ｂ線における
断面図である。本実施例は同図に示すように、第１の配
線基板１０の上に第２の配線基板１１を平行させて装着
し、第２の配線基板１１から導出させたリード端子３４
を第１の配線基板１０上に配置する。そして、第１の配
線基板１０上の配線端子１４と、前記第２の配線基板１
１からのリード端子３４に対して、ＩＣチップ１２をフ
ェースダウン状に搭載し、パッド電極との接続を行う。FIG. 3 is a diagram showing a second embodiment of the present invention.
3A is a plan view, and FIG. 3B is a cross-sectional view taken along line bb in FIG. In this embodiment, as shown in the figure, a second wiring board 11 is mounted on a first wiring board 10 in parallel, and lead terminals 34 led out from the second wiring board 11 are mounted.
Is arranged on the first wiring board 10. Then, the wiring terminals 14 on the first wiring board 10 and the second wiring board 1
The IC chip 12 is mounted face down on the lead terminals 34 from 1 and connected to the pad electrodes.
【００２０】この場合、導電性接着剤を用いて接着する
か、図の如くバンプまたは導電性粒子の単体または複数
の集合体３５を介在させて接続することができる。この
時、第１の配線基板１０上の配線端子１４の高さと第２
の配線基板１１のリード端子３４との高さが異なる場
合、図のように第１の配線基板１０とＩＣチップ１２と
が平行となるように配線端子１４側とリード端子３４側
のバンプまたは導電性粒子３５との高さや大きさを変え
ることにより、適切な接続を行うことができる。あるい
は、導電性粒子の場合には、大きさは同じであっても粒
子自体に弾力性を持たせることにより自在な変形力によ
り適切な接続を行うことができる。In this case, the connection can be made by using a conductive adhesive or by interposing a single or a plurality of aggregates 35 of bumps or conductive particles as shown in the figure. At this time, the height of the wiring terminal 14 on the first wiring board 10 and the second
When the height of the lead terminal 34 of the wiring board 11 is different from the height of the lead terminal 34, the bump or the conductive material on the wiring terminal 14 side and the lead terminal 34 side so that the first wiring board 10 and the IC chip 12 are parallel as shown in FIG. By changing the height and size of the conductive particles 35, an appropriate connection can be made. Alternatively, in the case of conductive particles, even if they are the same in size, appropriate connection can be made by freely deforming force by giving elasticity to the particles themselves.
【００２１】図４は本発明の第２の実施例の応用例を示
す図で、（ａ）は斜視図、（ｂ）は（ａ）図のｂ−ｂ線
における断面図である。本応用例は同図に示すように、
ドライバＩＣチップ１２をパネル基板２８の端面上にフ
ェースダウンにてフリップチップ形態により搭載したも
のであるが、予めＩＣチップ１２のパッド電極側にバン
プ３５を形成しておき、このバンプ３５をパネル基板２
８上の表示電極端子３０と配線基板２９上の各リード端
子３４部分に目合わせして載置し、その後熱圧着により
相互の電極間を一斉にボンディング（ギャングボンディ
ング）する。FIGS. 4A and 4B are views showing an application example of the second embodiment of the present invention. FIG. 4A is a perspective view, and FIG. 4B is a sectional view taken along line bb of FIG. In this application example, as shown in the figure,
The driver IC chip 12 is mounted face-down on the end surface of the panel substrate 28 in a flip-chip manner. A bump 35 is formed on the pad electrode side of the IC chip 12 in advance, and the bump 35 is attached to the panel substrate 28. 2
The display electrode terminals 30 on the substrate 8 and the respective lead terminals 34 on the wiring board 29 are aligned and mounted, and thereafter, the electrodes are simultaneously bonded (gang bonding) by thermocompression bonding.
【００２２】この場合、均一なボンディング品質を保つ
ため、表示電極端子３０部分の厚みと配線基板のリード
端子３４部分の厚みが異なる場合は、バンプ３５の高
さ、あるいはサイズによりこの電極の厚みの差を吸収す
るように設定することができる。また接続方法としては
以上の熱圧着によらず、導電性接着剤を用いて端子部分
を固着させる方法をとることもできる。さらに、ＩＣチ
ップ１２と基板２８との間に接着剤を塗布し、この接着
剤が乾燥する時の収縮力により固着する方法をとること
もできる。本方式は、全ての端子をギャングボンディン
グにより接続できるので、接続時間を極めて短縮するこ
とが可能となる。なお、以上の各応用例において、信号
線および電源線の一部は配線板を使わず、ガラス基板端
面上に形成することも可能である。In this case, in order to maintain uniform bonding quality, when the thickness of the display electrode terminal 30 and the thickness of the lead terminal 34 of the wiring board are different, the thickness of the electrode is changed depending on the height or size of the bump 35. It can be set to absorb the difference. As a connection method, a method of fixing the terminal portion by using a conductive adhesive instead of the above-mentioned thermocompression bonding can be adopted. Further, it is also possible to adopt a method in which an adhesive is applied between the IC chip 12 and the substrate 28 and the adhesive is fixed by a contraction force when the adhesive is dried. In this method, since all terminals can be connected by gang bonding, the connection time can be extremely reduced. In each of the above-described application examples, a part of the signal line and the power supply line can be formed on the end surface of the glass substrate without using the wiring board.
【００２３】[0023]
【発明の効果】本発明に依れば、液晶表示パネル等に用
いた場合、パネル表示部の製造工程と、ドライバＩＣへ
の複雑な配線部分の製造工程を完全に切り離すことがで
きるため、それぞれを製造した後、検査し、それらの良
品同士を合体する工程が可能となり、全体の製造歩留り
を高め、従って低価格化を達成することができる。According to the present invention, when used in a liquid crystal display panel or the like, the manufacturing process of the panel display section and the manufacturing process of the complicated wiring portion to the driver IC can be completely separated. After manufacturing, the process of inspecting and merging those non-defective products becomes possible, so that the overall manufacturing yield can be increased, and thus the cost can be reduced.
【００２４】また、制御信号や電源配線が施された配線
基板上にＩＣチップを搭載するとともに、パネル表示端
子とＩＣチップの電極パッド間はワイヤ配線により直接
接続するという実装構造により、この実装部（額縁部）
の面積を極めて小さくするこができる。さらに、パネ
ル、配線基板およびドライバＩＣチップの３素子間の接
続端子数が最も少なくなり、ユニット全体の接続工数を
少なくできるので低価格化が実現できると共に、信頼性
の向上も可能となる。In addition, an IC chip is mounted on a wiring board on which control signals and power supply wiring are provided, and a panel display terminal and an electrode pad of the IC chip are directly connected by wire wiring. (Frame)
Can be made extremely small. Further, the number of connection terminals between the three elements of the panel, the wiring board, and the driver IC chip is minimized, and the number of connection steps of the entire unit can be reduced, so that cost reduction can be realized and reliability can be improved.
【図１】本発明の第１の実施例を示す図で、（ａ）は平
面図、（ｂ）は（ａ）図のｂ−ｂ線における断面図であ
る。FIGS. 1A and 1B are diagrams showing a first embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line bb of FIG.
【図２】本発明の第１の実施例の応用例を示す図で、
（ａ）は斜視図、（ｂ）は（ａ）図のｂ−ｂ線における
断面図である。FIG. 2 is a diagram showing an application example of the first embodiment of the present invention;
(A) is a perspective view, (b) is sectional drawing in the bb line of (a) figure.
【図３】本発明の第２の実施例を示す図で、（ａ）は平
面図、（ｂ）は（ａ）図のｂ−ｂ線における断面図であ
る。FIGS. 3A and 3B are views showing a second embodiment of the present invention, wherein FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view taken along line bb in FIG.
【図４】本発明の第２の実施例の応用例を示す図で、
（ａ）は斜視部、（ｂ）は（ａ）図のｂ−ｂ線における
断面図である。FIG. 4 is a diagram showing an application example of the second embodiment of the present invention;
(A) is a perspective view, (b) is sectional drawing in the bb line of (a) figure.
【図５】従来のＩＣチップの実装構造を示す図である。FIG. 5 is a diagram showing a mounting structure of a conventional IC chip.
１０…第１の配線基板 １１…第２の配線基板 １２…ＩＣチップ １３…ＩＣチップのパッド電極 １４…配線端子 １５…ワイヤ ２３…入力パッド電極 ２５…出力パッド電極 ２８…パネル基板 ２９…配線基板 ３０…パネル表示電極端子 ３３…配線 ３４…リード端子 ３５…バンプ DESCRIPTION OF SYMBOLS 10 ... 1st wiring board 11 ... 2nd wiring board 12 ... IC chip 13 ... Pad electrode of IC chip 14 ... Wiring terminal 15 ... Wire 23 ... Input pad electrode 25 ... Output pad electrode 28 ... Panel board 29 ... Wiring board Reference numeral 30: panel display electrode terminal 33: wiring 34: lead terminal 35: bump
Claims (6)
接続を行うための複数の配線基板とを備えたＩＣチップ
の実装構造であって、 該ＩＣチップは、該ＩＣチップの一の主面に設けられた
複数のパッド電極について、該複数の配線に対してそれ
ぞれ異なる接続方式にて接続されてなることを特徴とす
るＩＣチップの実装構造。1. An IC chip mounting structure comprising an IC chip and a plurality of wiring boards for making an electrical connection with the IC chip, wherein the IC chip is one of the main components of the IC chip. An IC chip mounting structure, wherein a plurality of pad electrodes provided on a surface are connected to the plurality of wirings by different connection methods.
ング、バンプ接続、導電性接着剤による接続、および導
電性粒子の単体または複数の集合体による接続の中から
選ばれる接続方式を含むことを特徴とする請求項１に記
載のＩＣチップの実装構造。2. The different connection method includes a connection method selected from among wire bonding, bump connection, connection using a conductive adhesive, and connection using a single or a plurality of aggregates of conductive particles. The mounting structure of the IC chip according to claim 1.
接続を行うための複数の配線基板とを備えたＩＣチップ
の実装構造であって、 該ＩＣチップは、該複数の配線基板に対して、高さまた
は大きさが異なるバンプまたは導電性粒子の単体あるい
は複数の集合体を用いて接続されてなることを特徴とす
るＩＣチップの実装構造。3. A mounting structure of an IC chip comprising an IC chip and a plurality of wiring boards for electrically connecting to the IC chip, wherein the IC chip is mounted on the plurality of wiring boards. A bump or conductive particle having a different height or size and being connected using a single body or a plurality of aggregates.
接続を行うための複数の配線基板とを備えたＩＣチップ
の実装構造であって、 該ＩＣチップは、該複数の配線基板に対して、弾力性の
あるバンプまたは導電性粒子の単体あるいは複数の集合
体を用いて接続されてなることを特徴とするＩＣチップ
の実装構造。4. An IC chip mounting structure comprising an IC chip and a plurality of wiring boards for electrically connecting to the IC chip, wherein the IC chip is mounted on the plurality of wiring boards. And a connection structure using a single or a plurality of aggregates of elastic bumps or conductive particles.
接続を行うための複数の配線基板とを備えたＩＣチップ
の実装構造であって、 該複数の配線基板は、多層配線構造を有する該ＩＣチッ
プを搭載する第１の基板と、同一配線層に並行的に複数
の配線が設けられた単層配線構造を有するフレキシブル
基板からなる第２の基板とを含み、 該第２の基板は、該ＩＣチップが搭載される該第１の基
板上に貼りつけられてなり、 該第１、第２の基板上の端子は、該ＩＣチップの対応す
る端子にそれぞれ接続されてなることを特徴とするＩＣ
チップの実装構造。5. An IC chip mounting structure comprising an IC chip and a plurality of wiring boards for electrically connecting to the IC chip, wherein the plurality of wiring boards have a multilayer wiring structure. A first substrate on which the IC chip is mounted, and a second substrate made of a flexible substrate having a single-layer wiring structure in which a plurality of wirings are provided in parallel on the same wiring layer, wherein the second substrate is Affixed on the first substrate on which the IC chip is mounted, and terminals on the first and second substrates are respectively connected to corresponding terminals of the IC chip. IC
Chip mounting structure.
のパネル基板と、該表示電極端子と電気的に接触される
ＩＣチップとを備えたＩＣチップの実装構造であって、 複数の制御信号線または電源線を形成された少なくとも
１つの配線基板を有し、 該ＩＣチップは、該パネル基板または該配線基板上に搭
載され、 該パネル基板上の表示電極端子および、該配線基板上の
制御信号線または電源線端子は、該ＩＣチップの対応す
る端子近傍に設けられ、それぞれ対応する端子間を接続
されてなることを特徴とするＩＣチップの実装構造。6. An IC chip mounting structure comprising: a panel substrate of a display panel having a plurality of display electrode terminals; and an IC chip electrically connected to the display electrode terminals, wherein a plurality of control signal lines are provided. Or at least one wiring board on which a power supply line is formed, wherein the IC chip is mounted on the panel board or the wiring board, a display electrode terminal on the panel board, and a control signal on the wiring board. A mounting structure for an IC chip, wherein a wire or a power line terminal is provided near a corresponding terminal of the IC chip, and the corresponding terminals are connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10023462A JP2862081B2 (en) | 1998-02-04 | 1998-02-04 | IC chip mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10023462A JP2862081B2 (en) | 1998-02-04 | 1998-02-04 | IC chip mounting structure |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4008561A Division JP2803699B2 (en) | 1992-01-21 | 1992-01-21 | IC chip mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10229098A JPH10229098A (en) | 1998-08-25 |
| JP2862081B2 true JP2862081B2 (en) | 1999-02-24 |
Family
ID=12111198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10023462A Expired - Lifetime JP2862081B2 (en) | 1998-02-04 | 1998-02-04 | IC chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2862081B2 (en) |
-
1998
- 1998-02-04 JP JP10023462A patent/JP2862081B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10229098A (en) | 1998-08-25 |
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