JP2859267B2 - Still image recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a still image recording device such as an electronic still camera. (Prior Art) Currently widely used cameras use a silver halide film as a recording medium, and since the film is developed by chemical processing after photographing, an image photographed by the camera is instantly viewed. That was impossible. As a solution to such a problem, for example, as disclosed in Japanese Patent Application Laid-Open No. 49-52192, an electrophotographic system that converts an optical image into an electric signal and displays a video on a television receiver has been proposed. Developed and recently commercialized. In other words, this electrophotographic system uses a recording medium in the form of a cassette or cartridge made of a tape, disk, drum, or the like using a magnetic material, and mounts the recording medium on a camera to shoot an image. It is a method of removing the image and attaching it to a reproducing device to obtain a reproduced image by a television receiver connected to the reproducing device. However, in this method, since the recording medium is made of a magnetic material, a magnetic head for recording / reproducing and a mechanism for driving the magnetic head are required. There is a problem that power consumption is large. In addition, these recording media can store only a very small amount of information when storing digital data that requires a large capacity, considering the memory capacity of a normally used size. Therefore, analog data is stored, which causes deterioration of image quality. (Problems to be Solved by the Invention) As described above, the above-described electrophotographic system has problems such as an increase in size of a device, an increase in power consumption, and a deterioration in image quality. It is based on such circumstances of the present invention,
It is an object of the present invention to provide a still image recording apparatus capable of reducing the size of a device, reducing current consumption, and improving image quality. [Structure of the Invention] (Means for Solving the Problems) A still image recording apparatus of the present invention captures a subject image as a still image based on a predetermined timing, and converts the still image into an electric signal. A still image recording apparatus having a recording medium detachably attached to the main body and electrically storing data relating to the electric signal in a writable and readable manner, wherein image data of the still image is generated from the electric signal. Image data generating means, status generating means for designating an address at which writing or reading of the image data is started in a recording area of the recording medium, and generating a status designating start address information or data information; Means for switching between the address and the image data in accordance with the data transmission and reception to and from the recording medium via a common bus. And butterflies. The recording medium detachable from the main body unit includes an address counter that counts an address of a recording area for each writing and reading of the image data, and an address that is transferred by the common bus and identified by the status. Timing control means for controlling the timing of writing and reading of the image data using the address counted by the address counter. (Operation) In the present invention, an electric signal relating to a still image is converted into a digital signal, and this data is recorded in a recording means having a semiconductor memory element capable of electrically rewriting recording data in correspondence with a predetermined address. I have. (Example) Hereinafter, details of an example of the present invention will be described with reference to the drawings. FIG. 1 is a schematic perspective view of an electronic still camera according to one embodiment of the present invention. The electronic still camera shown in FIG. 1 includes a camera body 1 and a memory card 2 that is detachable from the body 1. The camera body 1 includes a lens barrel 3, a viewfinder 4, a shutter 5, and the like, as well as an ordinary camera, and includes an opening 6 into which the memory card 2 is inserted. The memory card 2 fulfills the function of a film used in a normal camera. FIG. 2 is a block diagram for explaining the configuration of the camera body 1. In the figure, a lens indicated by reference numeral 7 is disposed in the lens barrel 3, and the subject image is projected by this lens 7 onto a CCD 8 disposed on the back of the lens 7. The CCD 8 outputs an analog electric signal according to the brightness of the image projected in this manner, and this electric signal is
After being converted into a digital signal by the A / D converter 9, the band is compressed by the band compression circuit 10 and input to the memory card control circuit 11. Reference numeral 41 denotes a microphone arranged outside the main body 1, and an audio signal input from the microphone 41 is input to the memory card control circuit 11 via an A / D converter 42 and a digital audio circuit 43. You. The CPU indicated by reference numeral 12 performs overall control of the entire electronic still camera including the memory card 2, and performs, for example, drive control of the CCD 8 via the drive system 13 and control of the compression ratio of the band compression circuit 10. And also controls the memory card control circuit 11 and the memory card 2. FIG. 3 is a block diagram for explaining the configuration of the memory card control circuit 11 and its peripherals. In the figure, reference numeral 14 denotes the band compression circuit 10 or the CPU 1
This is an I / O control circuit that controls input and output between the memory card 2 and the memory card 2 in order to exchange data signals between them. That is, the data input terminal indicated by reference numeral 15 receives a data signal relating to an image from the band compression circuit 10, and the data input terminal indicated by reference numeral 44 receives a data signal relating to audio from the digital audio circuit 43. These data signals and the data signal generated by the CPU 12 are sent to the data input / output terminal 1 through the I / O control circuit 14.
6 to the memory card 2. On the other hand, a data signal from the memory card 2 input from the data input / output terminal 16 is sent to the CPU 12 via the I / O control circuit 14. Here, a memory 17 is interposed on a data line between the CPU 12 and the I / O control circuit 14, and an interface of a data transfer speed between them is provided. That is, CPU1
The data signals input and output at 2 are serial signals and are low-speed, while the data signals input and output at the I / O control circuit 14 are parallel signals and high-speed. Alternatively, the parallel signal is converted into a parallel signal or a serial signal, respectively. Reference numeral 18 denotes an address generation circuit which sequentially generates an address signal corresponding to an initial address value designated by the CPU 12 and an address value obtained by sequentially adding "1" to this value. This address signal is sent from the address output terminal 19 to the memory card 2. Reference numeral 20 denotes a timing signal generation circuit. The timing signal generation circuit 20 sends a signal from the I / O control circuit 14, the memory 17, the address generation circuit 18 or the timing output terminal 21 to the memory card 2 based on a designation from the CPU 12. ,
Generate a predetermined timing signal. FIG. 4 is a schematic view of the memory card 2. This memory card 2 has a large number of electrically rewritable memories 23, such as RAM or E ² ROM, mounted on a substrate 22 and a camera body at one end. The connection terminals 24 connected to 1 are arranged in a row. FIG. 5 is a block diagram for explaining the configuration of such a memory card 2. Reference numeral 24a denotes a data input / output terminal connected to the terminal 16 of the main body 1, and the data input / output terminal 24a is connected to each data input / output terminal of the memory 23 via the I / O control circuit 25. Reference numeral 24b denotes an address input terminal connected to the terminal 19 of the main body 1, and this address input terminal 24b is used for each address input terminal of the memory 23 and the chip select circuit.
Connected to 26. Further, 24c is a timing input terminal connected to the terminal 21 of the main body 1, and this timing input terminal 24c is connected to each timing input terminal of the memory 23. The chip select circuit 26 selects a predetermined memory 23 to be operated according to an address signal from the main unit 1. FIG. 6 is a memory map for explaining a memory area constituted by a large number of memories 23 mounted on the memory card 2. As shown in the figure, this memory area stores a card header area 27 in which data unique to the memory card 2 itself is recorded, and a start address 28a and an end address 28b of an area in which each image data is recorded. It is roughly divided into three areas: a director area 28 and an image data area 29 in which each image data is actually recorded. The card header area 27 includes a card number area 27a in which data unique to the memory card 2 itself is recorded, a residual memory capacity area 27b in which remaining data of an area where data can be written in the image data area 29, The memory card 2
Number of captured images area in which data of the number of captured images is recorded
27c, an image data final address area 27d where the data of the last use address of the image data in the image data area 29 is recorded. The data area 29 is recorded in one screen data areas 29a... Divided for each screen, and these one screen data areas 29a are respectively composed of an image header area 29b and an image data area 29c in which actual image data is recorded. Consists of The image header area 29b includes an information classification area 29d indicating what type of data, for example, data such as an image and a sound is recorded in the image data area 29c of the one-screen data area 29a. A method area 29e indicating whether data is recorded by such an image processing method such as NTSC or CCIR, a screen number area 29f in which screen number data is recorded, for example, set by a compression ratio of the band compression circuit 10. An image quality mode area 29g in which data of the image quality mode is recorded, time areas 29h to 29m in which data of the recorded time is recorded, a title area 29n in which data of a title of a recorded image is recorded, and the like. Next, the photographing operation of the electronic still camera configured as described above will be described. First, when a memory card is inserted into the camera body 1 through the opening 6, terminals 16, 19, and 21 of the memory card control circuit 11 in the body 1 and terminals in the memory card 2
24a, 24b and 24c are connected respectively. Thereafter, the CPU 12 causes the timing signal generation circuit 20 to generate a signal for reading data from the memory 23, and sends the signal to the address generation circuit 18 in the card header area 27.
Generate the address of As a result, a signal related to data in the card header area 27 of the memory 23 in the memory card 2 is transmitted to the I / O control circuit 2.
5, transferred to CPU 12 via I / O control circuit 14 and memory 17,
The PU 12 determines whether image data can be written from the data in the card header area 27 to the memory 23 of the memory card 2, from what address in the memory (start address) to what address (end address), the next image data Confirmation and calculation, etc. should be performed. If image data can be written, the CPU 12 sets the start address and the end address in the address generation circuit 18. Thereby, the camera enters a state of waiting for the user to turn on the shutter. When the user presses the shutter 5, the CPU 12 generates a signal for writing data to the memory 23 to the timing signal generating circuit 20, and also transmits the address signal set as described above to the address generating circuit 18 in a predetermined manner. At the timing of. Therefore, after this, the image data signal from the CCD 8
The data is transmitted to the memory card 2 via the D converter 9, the band compression circuit 10, and the I / O control circuit 14. At the same time, the address signal generated by the address generation circuit 18 is also sent to the memory card 2 side. As a result, in the memory card 2, the image data is sequentially written to the address corresponding to the address signal from the address generation circuit 18 in the image data area 29 of the memory 23. When such writing is completed, an updated card header data signal from the CPU 12 is input to the memory 23 via the memory 17, the I / O control circuit 14, and the I / O control circuit 25, and the card header area 27 At the same time as the updating is performed, data signals of the start address and the end address corresponding to the image data similarly written are also sent from the CPU 12 to the memory 23, and these data are written in the direct area 28. Thereafter, the CPU 12 sends a signal to the timing signal generation circuit 20.
A signal for stopping a series of write operations to the memory 23 is generated. Thus, in the electronic still camera of the present embodiment,
Since the means for recording image data is constituted by a recording medium capable of electrically rewriting data such as RAM and E ² ROM, the means for writing and the like on this recording medium is constituted by an electric element. This makes it possible to reduce the size of the device and the current consumption. Further, since such a recording medium has a tremendous recording capacity in a size in normal use, digital recording becomes possible, and the image quality is improved. On the other hand, as described above, the memory 23 of the memory card 2 has a memory area, a card header area 27 in which data unique to the memory card 2 itself is recorded, and a start address 28a of an area in which each image data is recorded. And a director area 28 in which an end address 28b is stored, and an image data area 29 in which each image data is actually recorded.
The areas are roughly divided into areas, and these areas are further finely divided according to functions, so that address management can be performed reliably and easily. As described above, since it is necessary to exchange image data, address data, and other signals at various timings between the main body 1 and the memory card 2 as described above, usually the number of input / output pins corresponding to these signals is the minimum. Required. In the following embodiment, the number of input / output pins is reduced and the attachment / detachment of the memory card 2 is improved. FIG. 7 shows a memory card control circuit 1 according to the second embodiment which is different from the above-described embodiment.
FIG. 2 is a diagram for explaining a configuration 1 ′ and its periphery. The memory card control circuit 11 'shown in FIG.
The difference from the memory card control circuit 11 shown in FIG. 3 is that the address generation circuit 18 is removed and a status generation circuit 30 is newly provided. FIG. 8 is a diagram showing the configuration of the memory card 2 'of the second embodiment. Reference numeral 24a denotes a data input / output terminal connected to the terminal 16 of the main body 1, and the data input / output terminal 24a is connected to each data input / output terminal of the memory 23 via the I / O control circuit 25. Reference numeral 24d denotes a status input terminal connected to the terminal 19 'on the main body 1 side.
d is connected to the status decoder 31. Further, reference numeral 24e is a timing input terminal connected to the terminal 21 of the main body 1, and this timing input terminal 24e is connected to the timing control circuit 32. Reference numeral 33 denotes an address counter for generating a predetermined address. In this embodiment, the data bus and the address bus are shared. That is, the image data signal and the address signal are transferred to the shared bus line indicated by reference numeral 34. As the address signal transferred in this manner, only the start address data for starting the reading or writing of the image data is transferred instead of the address data corresponding to each image data as in the first embodiment described above. The address data corresponding to each image data is generated by an address counter 33, which is
23 and chip select 26. By the way, since the data bus and the address bus are shared in this way, it is necessary to distinguish whether the signal being transferred is an image data signal or an address signal. Also, for image data, the transfer direction must be distinguished. For this purpose, a status generation circuit 30 is provided on the main body 1 side, and a status decoder 31 is provided on the memory card 2 side. The status signal shown in FIG. An enable signal is sent to the timing control circuit 32. In FIG. 9, “x” indicates don't care, “0” indicates a LOW level, and “1” indicates a HIGH level. Then, case 1 does not operate, that is, bus line 3
4 is in a high impedance state. Also, from case2 to ca
Up to se7, a mode for transferring read or write address data. The existence of the plurality of modes is based on the fact that the address data consists of a maximum of 24 bits, while the bus line 34 has 8 bits. That is, case 2 is a mode in which the lower byte start address for reading is transferred. case3 is a mode for transferring a lower byte start address for writing. case4 is a mode in which the middle byte start address for reading is transferred. case6 is a mode in which the upper start address for reading is transferred. case7 is a mode for transferring the upper start address for writing. However, by combining these modes, it is possible to transfer start address data for each of read and write. Case8 is a mode to output read data.
Is a mode for inputting write data. As described above, in the present embodiment, writing of data to the memory card 2 or reading of data from the memory card 2 is performed using these modes. That is, when reading arbitrary data from the memory card 2, the CPU 12 first loads the start address corresponding to the data to be read in the mode of case2, case4, and case6 from the status generation circuit 30 to the address counter 33, and then reads case8. The required mode is set to a state in which required data is to be read. The read operation is completed by the above operation. Then, the address counter 33 starts counting up from the loaded address, and supplies the value to the memory 23. Thus, data corresponding to these addresses is read from memory 23. On the other hand, when writing data to the memory card 2, the CPU 12
First, the start address corresponding to the data to be written in the mode of case 3, case 5, and case 7 is loaded from the status generation circuit 30 to the address counter 33, and then
According to the mode of case 9, data is written into the memory 23. With the above operation, the preparation for writing data is completed. Then, the address counter 33 starts counting up from the loaded address, and supplies the value to the memory 23. As a result, data is written in the memory 23 corresponding to these addresses. Next, a procedure for reproducing the image data recorded on the memory card 2 using a reproducing device (not shown) will be described. When the memory card 2 is inserted into the player, the player reads card header information and directory information from the memory card 2, and sets the number of screens recorded on the memory card 2, the start address and end address of each recorded image. Detect. When the user specifies a screen to be reproduced, the start address corresponding to the screen is transferred to the memory card 2, and the target image data is read and reproduced. [Effect of the Invention] As described above, in the still image recording apparatus of the present invention, the means for recording image data has a semiconductor memory element capable of electrically rewriting data such as RAM and E ² ROM. Since the recording medium is used, the size of the device is reduced and the current consumption is reduced. Further, since such a recording medium has a tremendous recording capacity in a size in normal use, digital recording becomes possible, and the image quality is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic perspective view of an electronic still camera according to one embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of FIG. 1,
FIG. 3 is a block diagram showing the configuration of the memory card control circuit shown in FIG. 2, FIG. 4 is a schematic perspective view showing the inside of the memory card shown in FIG. 1, and FIG. 4 is a block diagram showing the configuration of the memory card shown in FIG. 4, FIG. 6 is a diagram for explaining a memory area of a memory in the memory card shown in FIG. 5, and FIGS. FIG. 9 is a diagram for explaining Example 2; 1 camera body, 2 memory card, 7 lens, 8 CCD, 9 A / D converter, 11 memory card control circuit, 12 CPU, 14, 25 I / O control circuit, 17 memory, 18 address generation circuit, 20 timing signal generation circuit, 23 memory, 27 card header area, 28 directory area, 29 data area.

Claims (1)

(57) [Claims] A main body that captures a subject image as a still image based on a predetermined timing, converts the still image into an electric signal, and is detachably attached to the main body so that data relating to the electric signal can be electrically written and read. A still image recording apparatus having a recording medium for storing the image data, an image data generating means for generating image data of the still image from the electric signal, and writing or reading of the image data in a recording area of the recording medium is started. Status generating means for specifying an address and generating a status specifying start address information or data information; and means for switching between the address and the image data according to the status and transmitting and receiving the data to and from the recording medium via a common bus And a still image recording device. 2. The recording medium detachable from the main body unit includes: an address counter for counting an address of a recording area each time the image data is written and read; an address transferred by the common bus and identified by the status; 2. The still picture recording apparatus according to claim 1, further comprising timing control means for controlling timing of writing and reading of the image data using an address counted by a counter.