JP2856064B2 - Digital filter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter for performing a high-speed operation, and more particularly, to a digital filter for performing a multiplication in a filter operation.
The present invention relates to a digital filter using M (Ramdom Access Memory).

[0002]

2. Description of the Related Art Generally, when a multiplier is used as a constituent element of an operation part of a digital filter, (1) when a multiplier is used, (2) a ROM (Read Only Memory) is used.
y) and (3) RAM (Rando)
When using m Access Memory), the following three components are known.

A comparison of the characteristics of these three components with a focus on the operating speed of the digital filter and the area of the semiconductor chip on which the digital filter is formed on a semiconductor chip shows that each component has a lower operating speed. In terms of performance, it is possible to realize almost the same performance, but the area occupied by the digital filter on the semiconductor chip is the largest in the ROM configuration, then the multiplier configuration, and then the RAM configuration.

For example, when an (8.times.8) multiplier is constituted by a ROM, it is necessary to write and store all multiplication results, so that 2 @ 16 = 65,536-bit word data is required, and the output is 16 bits. Therefore, further multiply by 16 times, 65536 x 16 = 108,576 bits and about 1M
Bit memory is required.

When a RAM is used instead of a ROM, the output is the same 1 bit, but the content data can be rewritten according to the coefficient.
Power = 256 words, multiplying by 16 and 256 x 16 = 4096
Just a bit. Although the degree of integration of the ROM is generally four times or more that of the RAM, it is apparent that the ROM is much larger than the RAM because the number of bits is required to be 256 times.

A digital filter using a multiplier can be realized with a relatively small area in the case of a simple parallel adder in which adders are arranged on a matrix by the number of bits. Requires the adoption of the algorithm of Booth, carry save adder, pipeline operation, and the like, which tends to complicate the circuit, increase the number of elements, and increase the circuit area.

A 4-tap FIR using four RAMs
Referring to FIG. 7, which shows an example of a specific configuration example of a first conventional digital filter constituting a (finite impulse response) type filter, the first conventional digital filter using the RAM is provided with a first prior art digital filter. It is necessary to store the result of multiplying the input data and the coefficient in advance (hereinafter referred to as coefficient calculation data) at an address corresponding to the input data.

When setting the coefficient calculation data, the first
The data selector 79 of the conventional digital filter converts the coefficient operation data input from the coefficient operation data input 72 into a R signal in accordance with a control signal input from a control signal input terminal 74.
One of the four RAMs of the AM 75 is selected and supplied, and stored corresponding to the address supplied from the address decoder 78.

Next, at the time of the filter operation of the first digital filter, the address decoder 78 converts predetermined digital data inputted from the data input terminal 71 into an address and supplies it to a RAM 75 comprising four RAMs. . The RAM 75 outputs the already stored coefficient operation data corresponding to the input address, and outputs the delay circuit (22
a to 22c), the adder (2)
3a to 23c), perform a filter operation by addition, and output from the data output terminal 73.

With such a configuration, it is possible to provide a small and high-speed digital filter capable of easily changing the coefficients of the digital filter.

However, in the first conventional digital filter, it is possible to form a high-speed digital filter having a small circuit area by using a RAM as described above. There is a disadvantage that it takes time to change the coefficient because it needs to be stored in the RAM.

For example, when each of the coefficient and the input of the digital filter is 8 bits and the output is 16 bits, 4096 bits of coefficient operation data are required for each tap, and 16384 bits of data are required for 4 taps. Become. This is a system that requires a large number of taps, such as a ghost reducer system.
A filter of up to 640 taps is required, in this case 4
This is not negligible in a system requiring a large amount of data of 096 bits × 640 = 262,440 bits.

Further, if all the data is serially transferred, 262,440 clocks are required to change the coefficient, and 163,840 clocks are required even if the data is transferred in 16-bit parallel. Also, this transfer rate is highly dependent on the performance of the external CPU.

A second conventional digital filter in which this disadvantage is improved and the data transfer time is shortened is disclosed, for example, in Japanese Patent Laid-Open No. 4-222111. This second
FIG. 8 shows the configuration of a conventional digital filter.

The digital filter of the second prior art uses a four-tap RAM to constitute a 4-tap FIR filter similarly to the digital filter of the first conventional example shown in FIG.

The digital filter according to the second prior art has a multiplier 93 which internally generates coefficient operation data without externally loading the coefficient operation data.

Next, the operation of the second conventional digital filter will be described with reference to FIG.

Referring to FIG. 8, first, coefficient data input from coefficient data input terminal 82 and stored in register 91 is stored in an internal address generated by counter 92 and multiplier 9.
Multiplied by three. The multiplication signal is stored in the RAM selected from the RAM 85 by the data selector 86 in accordance with the control signal input from the control signal terminal 84 in accordance with the internal address given via the address decoder 88.

The operation relating to the filter operation is described first with reference to FIG.
The description is omitted because it is the same as the digital filter of the first conventional example shown in FIG.

As described above, the data stored in the RAM is internally stored.
In the first conventional example, it is 40
Although it was necessary to load 96 bits of data, the second
In the conventional example, only the coefficient data of each tap is
8 bits x 4 taps = 32 bits
Just load the data.

[0021]

[0005] However, this
The conventional digital filter uses data stored in RAM
Is calculated as 2 8 to the power = 256 times per tap.
Is required, 256 taps with 4 taps = 1024 performances
Calculation is required. One operation and one data load
Assuming that each operation is performed in one clock,
32 clocks for loading, 1024 for calculating data stored in RAM
Clock, a total of 1056 clocks is required for changing the coefficient.
It is important. Extend this further to 640 taps
640 × 8 = 5120 clocks for loading data and R
640 × 256 clocks = 16 for calculation of AM stored data
3840 clock times are required.

That is, although there is an effect in the sense of reducing the dependence on the external CPU, there still remains a problem that it takes time to change the coefficient as a whole.

Accordingly, an object of the present invention is to provide a digital filter capable of reducing the time for changing coefficients and operating at high speed.

[0024]

A digital filter according to the present invention has a storage means for storing a coefficient signal comprising a digital signal which is a coefficient of the digital filter in an internal address corresponding to an internal address signal corresponding to the coefficient signal; An internal address generating means for generating the internal address; and address selecting means for selecting the internal address signal at the time of setting the coefficient signal and selecting an input signal at the time of the filter operation and providing the input signal to the storage means. In a digital filter that uses the digital signal stored in a storage unit, a digital filter includes a coefficient signal holding unit that receives and holds the coefficient signal for each tap and a cumulative addition unit that sequentially cumulatively adds the coefficient signal. Means at the time of setting the coefficient signal, Is configured to store a cumulative addition signal without an address corresponding to the internal address signal of said memory means.

Further, the tap of the digital filter according to the present invention may be configured to receive a common signal of the coefficient signal.

[0026] In addition, the data generating means of the digital filter of the present invention includes the coefficient signal holding means for holding the coefficient signals by the first control signal, the coefficient signal
Delay means for controlling the output of the No. holding means by the second control signal may be configured to have said cumulative addition means for adding outputs of said delay means of said coefficient signal holding means.

Further, the coefficient signal holding means of the digital filter of the present invention includes a register circuit controlled by a system clock of the first control signal, and the delay means operates in accordance with the second control signal. , And the accumulative adding means may include an adder.

According to another aspect of the present invention, there is provided a digital filter comprising: a storage unit for storing a coefficient signal composed of a digital signal which is a coefficient of the digital filter at an internal address corresponding to an internal address signal corresponding to the coefficient signal; An internal address generating means for generating an address; and address selecting means for selecting the internal address signal when setting the coefficient signal and selecting an input signal for the filter operation and providing the input signal to the storage means. A digital filter that uses the digital signal stored in the digital signal generator; and a data generation unit that includes a coefficient signal holding unit that receives and holds the coefficient signal for each tap and a cumulative addition unit that sequentially cumulatively adds the coefficient signal. , A first controlled by the second control signal
And a second and a selection unit, wherein the coefficient signal set time, and stores the cumulative addition signal generated by said accumulating means to the address corresponding to the internal address signal of said memory means, when said filter operation, the The digital signal processing apparatus has a data adder for adding the digital signals stored in the storage means.

Further, each of the taps of another digital filter according to the present invention may receive a common signal of the coefficient signal.

Still further, the data adder of the digital filter according to the present invention includes a register which is controlled by a first control signal and holds the coefficient signal, and controls an output of the storage means or an output of the register by a second control. A first selector for selecting an external signal, a cascade input terminal for receiving an external signal, an output signal of an adder, and the second signal .
A second selector for selecting under the control signal, a delay circuit for delaying the output of the second selector, and said adder for adding the outputs of said first selector of the delay circuit, the adder And a cascade output terminal for outputting the output of the vessel to the outside.

[0031]

Next, a digital filter according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital filter according to a first embodiment of the present invention. The same components as those of the conventional digital filter shown in FIGS. 3 and 4 are denoted by the same reference numerals.

Referring to FIG. 1, a digital filter according to a first embodiment of the present invention includes an input terminal 1 for receiving an input signal comprising a digital signal, and a supply of coefficient data comprising a digital signal which is a coefficient of the digital filter. Input terminals (2a to 2d), control signal terminals 4A and 4B for supplying and receiving control signals, and coefficient data input from input terminal 2 are held by a system clock input from control signal terminal 4A. Control signal terminal 4
Four data generators (10a to 10a) which accumulatively add coefficient data held by a control signal input to B as the address increases to one in synchronization with the system clock
d), a counter 12 for generating an address which increases the address by one in synchronization with the system clock, and four RAMs (5a to 5d) for storing the cumulatively added coefficient data of the data generators (10a to 10d). When receiving the signal of the counter 12 at the time of setting the coefficient data, an arbitrary storage address of the RAM (5a to 5d) for storing the coefficient signal data is generated, or the input signal is received at the time of the filter operation to store the coefficient signal data. An address decoder 8 for generating an arbitrary storage address of each of the RAMs (5a to 5d); a delay circuit (22a to 22c) for delaying an output of each of the RAMs (5a to 5d) for storing an input signal and coefficient data for a predetermined period;
An adder (23a) for adding the signal delayed by the delay circuits (22a to 22c) and the signals read from each of the RAMs 5b, 5c and 5d.
To 23c), and an output terminal 3 receiving the output of the adder 23c.

Further, a data generator (10a to 10d)
Referring to FIG. 2 showing a specific configuration example of the first embodiment of the present invention,
The data generator 10 of the digital filter of the embodiment
A coefficient register 11 for holding coefficient data input from a coefficient signal input terminal 2; a delay circuit 14 for delaying the coefficient data held in the coefficient register 11; An adder 15 for accumulating the coefficient data held in the register 11,
An output terminal 17 for outputting the output of the adder 15 is provided.

The digital filter according to the first embodiment basically has a data generator consisting of an adder and a delay circuit at each tap to shorten the coefficient change time.

Next, the operation of the digital filter of this embodiment will be described.

Referring again to FIG. 1, when setting the coefficient data of the digital filter according to the first embodiment of the present invention, the coefficient data input from the coefficient data input terminals (2a to 2d) is input from the control signal terminal 4A. The data is stored in a coefficient register inside the data generator 10 in accordance with the control signal.
The data generators (10a to 10d) for each tap of the digital filter of the first embodiment generate coefficient operation data. The coefficient operation data is stored in the RAM (5a to 5d) in accordance with the internal address generated by the counter 12. ).

Next, referring to FIG. 2 again showing a specific configuration example of the data generator 10, the coefficient data input from the coefficient signal input terminal 2 of the data generator 10 is stored in the coefficient register 11, and the system As the address increases by one by the adder 15 in synchronization with the clock, the data is cumulatively added to become coefficient operation data.

For example, when the coefficient is 5 and the input is 1, the coefficient operation data is 5, and when the input is 2, the coefficient operation data is 10. Therefore, when the input x is increased by one, At the same time, the necessary coefficient operation data can be obtained by adding the coefficient to the coefficient operation data K (x-1) immediately before the input x for the coefficient operation data Kx corresponding to the input x. The coefficient operation data thus obtained is stored in the RAM corresponding to the address generated by the address decoder 8 in synchronization with the counter 12.
(5a to 5d).

The filter operation of the digital filter of the first embodiment is the same as the filter operation of the digital filter of the prior art, so that the detailed description is omitted.

The digital filter according to the first embodiment of the present invention requires the same number of clocks as the conventional digital filter to generate coefficient data for each tap, but can perform data operations in parallel. Data can be loaded to all taps with 256 clocks, and the speed can be dramatically increased.

Further, since the data generator 10 can be constituted by an adder, a register and a delay circuit, it is possible to suppress an increase in circuit scale.

Next, a digital filter according to a second embodiment of the present invention will be described.

Referring to FIG. 3, the digital filter according to the second embodiment has coefficient data which is a coefficient of the digital filter instead of the four input terminals (2a to 2d) of the digital filter according to the first embodiment. A data generator (20a to 20d) having one input terminal 2 for receiving the supply and connecting the input terminals 2 in common and inputting coefficient data is a data generator (20a to 20d) for the digital filter of the first embodiment. 10
The components are the same as those of the digital filter of the first embodiment except that the components are replaced with the components a to 10d), and the same components are denoted by the same reference numerals.

When setting the coefficient data of the digital filter of the second embodiment, the coefficient data Ka input from the input terminal 2 is first held in the coefficient register 11a of the data generator 20a, and then the coefficient of the data generator 20b is set. The system clock is four clocks so as to hold the coefficient data Kb in the register 11b, further hold the coefficient data Kc in the coefficient register 11c of the data generator 20c, and finally hold the coefficient data Kd in the coefficient register 11d of the data generator 20d. The coefficient data can be held by the minute operation.

Other operations are the same as those of the digital filter according to the first embodiment, and thus detailed description is omitted.

In the digital filter of the second embodiment, four input terminals (2a to 2d) are reduced to one input terminal 2, and four connection lines to the data generators (20a to 20d) are further reduced. Since the number can be reduced to one, the structure can be simplified.

Next, a digital filter according to a third embodiment of the present invention will be described.

Referring to FIG. 4, the digital filter of the third embodiment has an input terminal (2a) which receives supply of coefficient data which is a digital filter coefficient when setting a coefficient.
2d), coefficient data is cumulatively added according to control signals from control signal terminals 4A and 4B, and the cumulative addition coefficient data is stored in a RAM (5a to 5d).
d), and at the time of filter operation, RAM (5
a to 5d), the accumulated addition coefficient data stored in the RAMs 5b and 5
c and the data adders (24a to 24d) for adding the signals read from the RAM 5d to the data generators (10a to 10d) of the digital filter of the first embodiment.
d) and the same components as those of the digital filter according to the first embodiment except for the configuration of each of the delay circuits (22a to 22c) and the adders (23a to 23c). Is shown.

Referring to FIG. 5, the data adder 24 of the digital filter according to the third embodiment includes selectors 35 and 36, a RAM data input terminal 32, a cascade input terminal 31, and a cascade output provided in the data generator 10 shown in FIG. Each of the terminals 33 is added. By controlling each of the selectors 35 and 36 with a control signal input from the control signal terminal 4B, the adder 15 is controlled.
Of the delay circuit 14 can be selected between a cascade input and an adder output data, so that the digital filter of the first embodiment can be selected. Data generator 10
And delay circuits (22a to 22c ) and adders (23
a to 23c ), thereby reducing the circuit size.

Next, the operation of the digital filter according to the third embodiment of the present invention will be described.

When setting the coefficients, the coefficient data input from the coefficient data input terminal 2 is stored in the coefficient register in accordance with the control signal input from the control signal terminal 4A, as in the digital filter of the first embodiment. The data adders (24a to 24d) perform cumulative addition of coefficients for each tap and store the added signals in the RAMs (5a to 5d) according to the internal address generated by the counter 12.

At the time of the filter operation, the RAM (5a to 5a)
The data output from d) is added to the data (24a to 24a).
The calculation is performed in d) and the result is output from the data output terminal 3.

Next, a digital filter according to a fourth embodiment of the present invention will be described.

Referring to FIG. 6, the digital filter of the fourth embodiment has coefficient data which are coefficients of the digital filter instead of the four input terminals (2a to 2d) of the digital filter of the third embodiment. Of the third embodiment, except that the input terminal 2 is connected to the input terminal 2 and the input terminal 2 is connected in common to input coefficient data to the data generators (24a to 24d). The same components as those of the filter are denoted by the same reference numerals.

When setting the coefficient data of the digital filter according to the fourth embodiment, the coefficient data Ka inputted from the input terminal 2 is first held in the coefficient register 11a of the data generator 24a, and then the coefficient data of the data generator 24b is stored. The system clock is four clocks so that the coefficient data Kb is held in the register 11b, the coefficient data Kc is held in the coefficient register 11c of the data generator 24c, and finally the coefficient data Kd is held in the coefficient register 11d of the data generator 24d. Perform coefficient operation and hold coefficient data.

Other operations are the same as those of the digital filter according to the third embodiment, so that detailed description will be omitted.

In the digital filter of the fourth embodiment, four input terminals (2a to 2d) are reduced to one input terminal 2, and four connection lines to the data generators (24a to 24d) are further reduced. Since the number of filters can be reduced to one, the simplified configuration of the digital filter according to the second embodiment has an effect that the configuration can be simplified.

[0059]

As described above, the present invention employs multiplication by R
Regarding a digital filter using AM (Ramdom Access Memory), each tap is provided with a data generator composed of an adder, a delay circuit and a coefficient register, thereby suppressing an increase in circuit scale and dramatically shortening a coefficient change time. Thus, a digital filter that can perform this operation can be realized.

According to the present invention, the time until filter operation becomes possible is about 1/4, 640 in the case of a 4-tap filter.
In the case of a tap filter, there is an effect that each can be reduced to about 1/180.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital filter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a data generator of the digital filter shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of a digital filter according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a digital filter according to a third embodiment of the present invention.

5 is a block diagram showing a specific configuration of a data adder of the digital filter shown in FIG.

FIG. 6 is a block diagram illustrating a configuration of a digital filter according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a first conventional digital filter.

FIG. 8 is a block diagram showing a configuration of a second conventional digital filter.

[Explanation of symbols]

 Reference Signs List 1 data input terminal 2 coefficient data input 3 data output 4, 4A, 4B control signal input terminal 5 coefficient RAM 6, 9 data selector 7, 10 data generator 8, 78 address decoder 11 coefficient register 12 counter 13 multiplier 14, 22a-22c Delay circuit 15, 23a-23c Adder 17 Coefficient operation data output terminal 18 Coefficient operation data input terminal 24, 24a-24d Data adder 31 Cascade input terminal 32 RAM data input terminal 33 Cascade output terminal 35, 36 Selector

Claims (7)

(57) [Claims] 1. A storage means for storing a coefficient signal composed of a digital signal which is a coefficient of a digital filter in an internal address corresponding to an internal address signal corresponding to the coefficient signal, and an internal address generating means for generating the internal address. Address selection means for selecting the internal address signal at the time of setting the coefficient signal, selecting an input signal at the time of filter operation and supplying the input signal to the storage means, and using the digital signal stored in the storage means for the filter operation. The digital filter includes a coefficient signal holding means for receiving and holding the coefficient signal for each tap, and a data generating means including a cumulative addition means for sequentially and cumulatively adding the coefficient signal. The cumulative addition signal generated by the cumulative addition means is stored in the internal address of the storage means. A digital filter characterized by storing at an address corresponding to a dress signal. 2. The digital filter according to claim 1, wherein each of said taps receives a common signal of said coefficient signal. 3. The data generating means outputs the coefficient signal.
Holding the first control signalCoefficient signal holding means
And the saidCoefficient signal holding meansIs output by the second control signal.
Delay means for controllingCoefficient signal holding meansOutput and
The accumulating means for adding the output of the delay means.
The digitizer according to claim 1 or 2, wherein
Filter. The method according to claim 4, wherein said coefficient signal holding means includes a register circuit that is controlled by the system clock of the first control signal, the delay circuit the delay means for delaying the output of the register circuit by said second control signal And the accumulating means includes an adder.
A digital filter according to 2, 3, or 4. 5. A storage means for storing a coefficient signal comprising a digital signal which is a coefficient of a digital filter in an internal address corresponding to an internal address signal corresponding to the coefficient signal, and an internal address generating means for generating the internal address. Address selection means for selecting the internal address signal at the time of setting the coefficient signal, selecting an input signal at the time of filter operation and supplying the input signal to the storage means, and using the digital signal stored in the storage means for the filter operation. A digital filter including a coefficient signal holding means for receiving and holding the coefficient signal for each tap, a data generating means including a cumulative addition means for sequentially and cumulatively adding the coefficient signal, and a digital control circuit controlled by the second control signal. And first and second selecting means, which are set when the coefficient signal is set. A data adder for storing the cumulative addition signal generated by the cumulative addition means at an address corresponding to the internal address signal in the storage means, and for performing the filter operation, adding a digital signal stored in the storage means; A digital filter, comprising: 6. The digital filter according to claim 5, wherein each of said taps receives a common signal of said coefficient signal. 7. The data adder includes a register controlled by a first control signal and holding the coefficient signal, and a first control for selecting an output of the storage means or an output of the register by a second control signal. A selector, a cascade input terminal receiving an external signal, an output signal of an adder, and the external signal.
A second selector for selecting a signal by the second control signal;
A delay circuit for delaying the output of the second selector, and said adder for adding the outputs of said first selector of the delay circuit, the cascade output terminal for outputting an output of said adder to an external 6. The method according to claim 5, wherein
Or the digital filter according to 6.