JP2856037B2 - Memory controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory controller for controlling data transfer between a memory and a processor.

[0002]

2. Description of the Related Art Japanese Patent Application Laid-Open No. Sho 60-136793 discloses a graphic processing apparatus which generates character and graphic data in a display memory (frame buffer) and outputs it to an output device such as a display device or a printer. There is. In this conventional example, speeding up of graphic drawing is achieved by a method of packing and storing data constituting a pixel in the same word. Whereas pixel information is spread over a plurality of words in the previous method, the memory is accessed in units of one word (16 bits). Therefore, if pixel information is packed in the same word, one access will be required. Pixels can be updated and speed is increased.

[0003]

In the above conventional example, 16
Although a memory is connected to the data bus of bits, a DRAM (Dynamic Random Access) usually used for a frame buffer is used.
Access memories generally have a 1-bit or 4-bit data bus, and at least 4 to 16 memory elements are required. This has been a problem that hinders downsizing of the device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory controller for enabling a transfer via a data bus having a small bit width, thereby reducing the number of memory elements used and reducing the size of the entire device. It is in.

[0005]

According to the present invention, there is provided an image data processing apparatus.
Data between memory and processor , memory and display
A memory controller that controls data transfer between devices
An m-bit terminal for sequentially transferring time-division m-bit (m is a natural number) data between the memory and the memory controller, and n-bit (n is a natural number n> m) data in parallel between the processor and the memory controller. An n-bit interface for transferring and a plurality of m via an m-bit terminal
First conversion means for converting between bit data and n-bit data via an n-bit interface , and a display device
Transfer serial data between memory and memory controller
At least one bit terminal and an m bit terminal
Multiple m-bit data passing through the serial data
And second conversion means for converting the data into

According to a preferred embodiment of the first and second conversion means, a latch for temporarily storing read data and a multiplexer for write data are incorporated.

[0007]

According to the memory controller of the present invention, the memory is accessed in a time-division manner and is converted into parallel data by the first conversion means. That is, at the time of data reading, data sequentially read in a time-division manner is temporarily stored in a latch, and then provided to the processor as parallel data. At the time of writing data, the parallel data supplied from the processor is sequentially and time-divisionally written to the memory via the multiplexer. Furthermore, for display devices
When outputting data, read data sequentially from memory
The output data is converted to serial data by the second conversion means.
After converting the data into data, it is output to the display device.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a graphic processing apparatus using the present invention. The graphic processing device includes a graphic processing processor ACRTC (Additional CRT Controller) 10, MIVA
C (Memory Interface and Video Attribute Controlle
r) 20, a frame buffer 30, a CPLT (DAC with built-in color palette) 40, and a CRT 50. The MIVAC 20 includes various control signals necessary for the ACRTC 10 to access the frame buffer 30,
And generate an address. Further, it generates 2CLK which is a reference signal of the ACRTC10. Further, it has a function of converting parallel data from the frame buffer 30 into serial data for a video signal. MIVAC20
Are the control signals (AS, MCYC, D
RAW, MRD, etc.), and reads and writes the frame buffer 30. At that time, frame buffer 3
0 (Dynamic RAM) control signal (RA
S, CS, OE, WE).
Multiplexed into the row / column address for the frame buffer 30 and received from the frame buffer 30. To the frame buffer 30, a plurality of column addresses are output following the one row address using the static column mode. In the present embodiment, the static column mode is used, but it may be combined with another continuous reading method (for example, page mode, nibble mode, etc.).

The read and write data are MIVAC
20, the ACRTC 10 and the frame buffer 30
Data is transferred between them.

In the display operation, the parallel data read from the frame buffer 30 is taken into the MIVAC 20, converted into serial data by a built-in parallel / serial converter, and output as a digital video signal. This digital video signal is converted into an analog video signal by the CPLT 40 and displayed on the CRT 50. In the present embodiment, the CRT 50 is used as an output device, but another output device such as a printer may be used.

FIG. 2 shows the pin arrangement of the MIVAC 20. The MIVAC 20 of the present embodiment has a combination of a high-speed bipolar technology and a low-power-consumption CMOS technology.
-Uses BiCMOS (High performance Bipoler CMOS) technology to realize logic circuits with high speed and high drive capability with relatively low power consumption. MIVAC20 is PLCC (Plas
Since a 68-pin package (tic Leaded Chip Carrier) is used, surface mounting is possible, and the mounting substrate of the graphic processing apparatus can be reduced in size.

FIG. 3 and FIG. 4 show various interface signals of the MIVAC.

The input / output signals of the MIVAC can be roughly divided into an operation control signal for controlling the operation of the MIVAC and an ACR signal.
An interface signal with the TC, an interface signal with the frame buffer, an interface signal with the display, and the like.

[0015] Among the operation control signals, INCLK is MIVA.
A clock serving as a reference for C is input. The interface signal to the ACRTC includes 2CLK serving as a reference clock of the ACRTC, and MR for controlling read and write operations.
Control signals such as D and DRAW, and MAD0 to MAD
15 address / data buses, MA16 to MA19 address buses, and the like. The interface signal to the frame buffer includes RA control signal for DRAM.
S, CS, OE, and WE, and row / column addresses of FA0 to FA9 are included. The interface signal with the display includes a digital video signal obtained by converting display data from parallel to serial, a DOTCK generated by dividing INCLK, and the like.

FIG. 4 shows the internal configuration of the MIVAC. In the MIVAC, various operation modes are possible by latching a user-definable attribute code stored in the ACRTC with an attribute code latch 2011 and using a signal decoded by a VCF decoder 2012.

INCLK serving as a reference for the operation of MIVAC
Are the INCLK 2006 and INCLK frequency divider 20
09 is divided by 2, 4, 8, 16, and 32. By combining these in the state decoder 2007, an operation timing signal is generated. This timing signal
Used in each logic.

2CLK which is a reference of ACRTC is 2C
It is generated by the LK generator 2008. 2CLK is
Since the read / write operation is performed a plurality of times in one memory cycle, the first half cycle is shortened and the second half cycle is lengthened.

DOTCLK is 1, 2, 4 of INCLK.
The divided signal is multiplexed by the multiplexer 2010 and output. Which frequency-divided signal is output is automatically selected according to the operation mode of the MIVAC.

MAD0-MA input from ACRTC
The frame buffer addresses of D15, MAD16 to MAD19 are temporarily latched by the latch 2001, and are multiplexed into row / column addresses by the multiplexer 2003, and the frame buffer addresses FA0 to FA
Generate a 10-bit address of A9. A column address counter 2002 is built in, and the value of this counter is multiplexed with an address latched by a multiplexer 2003 and used as a part of a column address, so that reading / writing can be performed several times in one memory cycle. It becomes possible. The control signal from the ACRTC is temporarily latched by the latch 2004. According to DRAW and MRD, a drawing read cycle, a drawing write cycle, or
It is determined whether the cycle is a display cycle. DRAW is low level, M
In the drawing read cycle in which RD is at a high level, RAS, CS,
OE is output, and the drawing data is read from the memory. The data read several times during one cycle is temporarily latched by the input data latch
16 and latched again. This data is
A output control 2000 allows MAD0 to MAD1 to be synchronized with data acquisition timing of ACRTC.
5 is output to the data bus.

In a drawing write cycle in which DRAW is at a low level and MRD is at a low level, RAS, CS, and WE generated by the memory control 2005 are output, and writing data is written to the memory. The drawing data for writing is synchronized with the address counted up by the column address counter 2002, and is written in FD0 to FD7.
Are multiplexed by the multiplexer 2014 at the output stage, and divided and written into the memory several times at the timing created by the FD output control 2013.

When DRAW is at a high level and MRD is at a high level, a display read cycle is determined. The data read several times in one cycle is temporarily latched by the input data latch 2015 used in the drawing read cycle. Thereafter, the data is transferred to and latched in the display data latch 2019. For a 4-chip memory configuration, MAD8 ~
Since data is also input from the MAD 15, the data is multiplexed by the multiplexer 2017 and transferred to the display data latch 2019. This data is stored in Shifter 2
020, and are latched by the latch 20202 in the shifter by the latch control 20201. The latched data is transferred to the shifter clock generation unit 20203.
Multiplexer 202 using the clock generated by
By multiplexing at 04, serial data is converted to parallel data to generate a 4-bit video signal.

The video signal is skewed by a skew circuit 2022 and synchronized with a control signal from the ACRTC. In response to this video signal, cursor blink 2023
It is possible to multiplex each video signal with the multiplexer 2024 by using a cursor superposition and a signal obtained by dividing VSYNC by 2. The video signal that has been subjected to these processes is finally converted to a DI signal from the ACRTC.
The signal is masked by the mask circuit 2025 by the SP signal, and output as a 4-bit digital video signal. The signal used for the video mask is output as SHFTTEN. Also, VSYNC used for multiplexing video signals
Is output as VSYNC / 2.

The BL2IRQ is generated by the BL2IRQ output unit 2021 using BLINK2 in the attribute code.

FIG. 6 shows a method of connecting frame buffers depending on the number of used memories. FIG.
In the case of the one-chip memory configuration shown in FIG.
FD0 to FD3 are connected to the data terminals of the frame buffer 300. FD4 ~
Do not use the terminal of FD7. In this case, MIVAC20
And the frame buffer 300 transfer 4-bit data at a time. In the drawing read cycle, MIVAC
Reference numeral 20 reads the 4-bit data four times, aligns it with 16 bits, and transfers it to the ACRTC 10. In the drawing write cycle, 16-bit data from ACRTC10 is
The data is transferred to the frame buffer 300 four times in a time-division manner. In the display read cycle, 4-bit data is transferred four times in one memory cycle or 16 times in two memory cycles.
And read in 16-bit and 64-bit display data, respectively.

In the case of the two-chip memory configuration shown in FIG. 6B, eight data terminals FD0 to FD7 of the MIVAC 20 are used. The data terminals of the frame buffer 300 are connected to FD0 to FD3, and the data terminals of the frame buffer 301 are connected to FD4 to FD7 for use. MIV
Between the AC 20 and the frame buffers 300 and 301, 8-bit data is transferred at a time. In the drawing read cycle, the MIVAC 20 reads the 8-bit data twice, aligns the data with 16 bits, and sets the ACRTC to 16 bits.
Transfer to 10. In the drawing light cycle, the ACRTC
The 16-bit data from 10 is transferred to the frame buffer 300 and the frame buffer 301 twice in time division. In the display read cycle, 8-bit data can be read four times in one memory cycle or 16 times in two memory cycles, and can be taken in as 32-bit and 128-bit display data, respectively. Therefore, application to a CRT at a higher speed than in the case of FIG.

In the case of the four-chip memory configuration shown in FIG.
The connection between the frame buffer 300 and the frame buffer 301 is the same as in the case of the two chips in FIG. 6B, but the frame buffer 302 and the frame buffer 303 of the remaining two chips are a data bus between the ACRTC 10 and the MIVAC 20. Of MAD0 to MAD15, MAD8 to
Connect to upper 8 bits of MAD15. In the drawing read cycle, the MIVAC 20 reads 16-bit data at one time. The 8-bit data read from the frame buffers 300 and 301 is the MIV
It is output to MAD0 to MAD7 via AC20.
The upper 8 bits of data read from the frame buffer 302 and the frame buffer 303 are stored in the MIVAC 20
, And is directly transferred to the ARCTC 10 through the buses of the MAD8 to MAD15. In the drawing write cycle, the lower 8 bits of data from the ACRTC 10
FD0 via MIVAC20 through D0-MAD7
To FD7. The upper 8 bits of data are
Directly through the frame buffer 30 without going through the VAC 20
2. Transferred to the frame buffer 303. In the display read cycle, the lower 8 bits of data are FD0 to FD
7 and the upper 8 bits of data are
Read four times in one memory cycle through MAD15,
The data is taken into the MIVAC 20 as 64-bit display data.

In this mode, since the data bus is used for inputting display data, the read function cannot be performed 16 times in two memory cycles. However, when compared in four read modes in one memory cycle, FIG. ), And can be applied to a CRT at a higher speed than in the case of FIG.

FIG. 7 shows the video output timing in each cycle mode.

The ACRTC 10 has a memory access mode including a single access mode in which display cycles are continuous and a dual access mode in which high-speed drawing is possible.

In MIVAC 20, in addition to these access modes, display cycle 2 in single access mode
A 2MCYC mode is provided in which the number of cycles is treated as one cycle and 16 memory reads are performed. In the single access mode, data fetched in the first display cycle is displayed in the next cycle. The data acquired in the second cycle is displayed in the third cycle. Thereafter, this is repeated. The data read in the last display cycle will be output in the next drawing cycle,
Since the DISC signal of ACRTC is output only during the display cycle period, one cycle behind the DISP is extended inside MIVAC and used as a mask signal. In the dual access mode, the data of the first display cycle is output over the next two cycles. Therefore, the part after the DISP is extended by two cycles and used as a mask signal. 2MCYC
In the mode, 16 times of data reading are performed in two cycles, so that the video output is also output over two cycles.

FIG. 8 shows the output timing of the attribute code output by the ACRTC. The attribute code is information that can be freely defined by the user. The attribute codes are MAD0 to MAD15, MAD16 to MAD16 to ACRTC while 2CLK and MCYC in the last refresh period are both at the high level.
Output to MAD19. By taking in and decoding this attribute code, the operation mode of MIVAC is set.

FIG. 9 shows the setting of an attribute code in MIVAC. MIVAC consists of MAD0 to MAD7, which can be freely defined by the user, and ACRT
MAD18 and MAD19, whose usage is determined in C, are used. 4 bits of MAD0 to MAD3, display color,
The shift amount of the shift register, the access mode, the number of memories used, and the division ratio of DOTCLK are set. MAD
4, the display color of the cursor is set by MAD5. MAD6
Sets the depth of memory to use. The MAD 7 sets whether to multiplex the video output.
The MAD 18 sets blink of the cursor. MAD
19 sets the BL2IRQ output.

FIG. 10 shows MAD0-MAD shown in FIG.
It shows 16 operation modes defined by 3 4 bits. The display color, the shift amount of the shift register, the access mode, the number of memories used, and the division ratio of DOTCLK are automatically determined by setting the 16 operation modes.

(1) Display colors (color / gradation) are monochrome display represented by 1 bit / pixel, 4 color display represented by 2 bits / pixel, and 16 color display represented by 4 bits / pixel. Is possible. In the case of 1 bit / pixel, information of 16 pixels continuous in the horizontal direction is stored in one word of the memory. In the case of 2 bits / pixel, information of eight pixels continuous in the horizontal direction is stored in one word of the memory. In the case of 4 bits / pixel, four words of information continuous in the horizontal direction are stored in one word of the memory.
Information for each pixel is stored.

(2) The shift length of the shift register is 4,
8, 16, and 32 bit shifts are possible.

(3) The access mode is a single access mode, a dual access mode capable of high-speed drawing,
2MCYC that performs display access 16 times in 2 memory cycles
Support mode. The single access mode is used for modes 0 to 5, and the dual access mode is used for modes 6 to C. Modes D to F use the 2MCYC mode.

(4) The number of memories used is 1, 2 or 4. As this memory, a memory such as a static column mode which can be read / written a plurality of times in one cycle is used.

(5) DOTCLK sets INCLK to 1,
Generated by dividing the frequency by 2 or 4. This division ratio is determined in each operation mode. The screen configuration of the CRT that can be used in each operation mode is determined from the frequency.

FIG. 11 shows the applicable D in each operation mode.
This shows the frequency of OTCLK. Mode 0,
3, 5, 8, B, D and F have a division ratio of 1, that is, IN
CLK is output as DOTCLK. In modes 1, 4, 6, 9, C, and E, the division ratio is 2, and in modes 2, 7, and A, DOTCLK having a division ratio of 4 is output. FIG. 12 shows MAD4 (CUR0) and MAD5 (CU
The display color of the cursor set in R1) is shown.

(1) When both CUR1 and CUR0 are 0: 4-bit video output, that is, VIDEOA to VIDEO
OD is all 0, and black is displayed.

(2) When CUR1 is 0 and CUR0 is 1 4-bit video output, that is, VIDEOA to VIDEO
The ODs are all 1 and white is displayed.

(3) When CUR1 is 1 and CUR0 is 0: 4-bit video output, that is, VIDEOA to VIDEO
Color inversion display is performed for each bit of OD.

(4) When both CUR1 and CUR0 are 1 The color inversion display is performed for each bit of the 3-bit video output VIDEOA to VIDEOC, but VIDEOD is displayed as it is.

FIG. 13 shows the depth of the used memory element set by the MAD6 (VMD). VMD
Is 0, a memory of 256 k × 4 bits is used, and V
When the MD is 1, a 1M × 4 bit memory is used.

FIG. 14 shows whether video output is multiplexed or not, which is set by MAD7 (MUXEN). If MUXEN is 0, no multiplexing is performed. When MUXEN is 1 and VSYNC / 2 is 0, no multiplexing is performed. MUXEN is 1 and VSY
When NC / 2 is 1, VIDEOC data is output to VIDEOA, and VIDEOD data is output to VIDEOB. This function is mainly used for a display device using a color shutter.

FIG. 15 shows the display of a graphic cursor set by the MA 18 (BLINK 1). When BLINK1 is 0, no cursor is displayed,
When BLINK1 is 1, a cursor is displayed.

FIG. 16 shows in detail the timing of a drawing read cycle when one memory is used.

FIG. 17 shows in detail the timing of the drawing read cycle when two memories are used.

FIG. 18 shows in detail the timing of the drawing read cycle when four memories are used.

FIG. 19 shows in detail the timing of the writing write cycle when one memory is used.

FIG. 20 shows the timing of the drawing write cycle when two memories are used.

FIG. 21 shows the timing of a drawing write cycle when four memories are used.

FIG. 22 shows in detail the timing of the display read cycle when one or two memories are used.

FIG. 23 shows in detail the timing of the display read cycle when four memories are used.

FIG. 24 shows in detail the timing of the display read cycle in the 2MCYC mode when one or two memories are used.

FIG. 25 shows the CS before RAS of the DRAM.
The timing of the refresh cycle is shown in detail. Refresh is performed during a period when the horizontal synchronization signal HSYNC is at a low level.

FIG. 26 shows the DOTCL in the frequency division of 1, 2, 4
K output timing, VSYNC / 2 output timing, VIDEOA to VIDEOD output timing, SH
The output timing of FTEN is shown in detail.

FIG. 27 shows the output timing of BL2IRQ in detail.

FIG. 28 shows ACRTC10, MIVAC2
1 shows an example of the configuration of a graphic processing apparatus configured by using DRAMs 300 to 303. Clock oscillator 80
Is used as INCLK of MIVAC 20. An external circuit 70 is provided at an interface with a microprocessor (not shown in FIG. 28), and a CRT interface circuit 60 is provided for HSYNC and VSYNC. FIG. 29 shows a circuit example using a NAND gate as an example. It is configured using bipolar transistors and N-channel MOS and P-channel MOS transistors. A low-power-consumption CMOS is used for the portion reflecting the logic of the preceding stage, and a bipolar transistor is used for the output side of the subsequent stage.

FIGS. 30 to 32 show the details of the address output from the MIVAC 20 to the FA terminal. FIG.
0 shows the case of a one-chip memory, FIG. 31 shows the case of a two-chip memory, and FIG. 32 shows the case of a four-chip memory. The signals (NC0 to NC2 and WC0 to WC2) surrounded by broken lines in FIGS. 29A to 29C are generated by the column address counter 2002. NC0 to NC2 are counters within one word, and one to two bits are used in each operation mode. WC0 to WC2 are word counters used for generating display addresses.
The reason that the bit numbers of the address are not always
This is because a common bit is used in each operation mode so that the circuit configuration of the multiplexer 2003 is made as simple as possible.

[0062]

As described above in detail, according to the present invention, the data bus width of the memory can be reduced, so that the data processing device can be downsized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a graphic processing apparatus using the present invention.

FIG. 2 is a diagram showing a pin arrangement of the MIVAC shown in FIG. 1;

FIG. 3 is a diagram showing MIVAC interface signals.

FIG. 4 is a diagram showing another interface signal of MIVAC.

FIG. 5 is a diagram showing an internal configuration of MIVAC.

FIG. 6 illustrates connection of a frame buffer depending on a difference in the number of used memories.

FIG. 7 is a diagram showing video output timing in each cycle mode.

FIG. 8 is a diagram showing the output timing of an attribute code output by ACRTC.

FIG. 9 is a diagram showing setting of an attribute code in MIVAC.

FIG. 10 is a diagram showing an operation mode defined by four bits of MAD0 to MAD3 shown in FIG.

FIG. 11 is a diagram showing applicable DOTCLK frequencies in each operation mode.

FIG. 12 is a diagram showing display colors of cursors set by MAD4 and MAD5.

FIG. 13 is a diagram showing a depth of a used memory element set by MAD6.

FIG. 14 is a diagram showing whether to multiplex a video output set by the MAD.

FIG. 15 is a diagram showing a display of a graphic cursor set by the MAD 18;

FIG. 16 is a diagram showing the timing of a drawing read cycle when one memory is used.

FIG. 17 is a diagram showing the timing of a drawing read cycle when two memories are used.

FIG. 18 is a diagram showing the timing of a drawing read cycle when four memories are used.

FIG. 19 is a diagram showing the timing of a drawing write cycle when one memory is used.

FIG. 20 is a diagram showing the timing of a drawing write cycle when two memories are used.

FIG. 21 is a diagram showing the timing of a drawing write cycle when four memories are used.

FIG. 22 is a diagram showing the timing of a display read cycle when one or two memories are used.

FIG. 23 is a diagram showing the timing of a display read cycle when four memories are used.

FIG. 24 shows a case where one or two memories are used.
FIG. 9 is a diagram showing a timing of a display read cycle in the MCYC mode.

FIG. 25 is a diagram showing the timing of a CS before RAS refresh cycle of a DRAM.

FIG. 26 is a diagram showing output timing of each signal in frequency division of 1, 2, and 4;

FIG. 27 is a diagram showing the output timing of BL2IRQ.

FIG. 28: ACRTC10, MIVAC20, DRAM
FIG. 3 is a diagram illustrating a configuration example of a graphic processing apparatus configured using 300 to 303.

FIG. 29 is a diagram illustrating a circuit example of a NAND gate.

FIG. 30 is a diagram illustrating details of an address output from the MIVAC to the FA terminal in the case of a one-chip memory.

FIG. 31 is a diagram illustrating details of an address output from the MIVAC to the FA terminal in the case of a two-chip memory.

FIG. 32 is a diagram showing details of an address output by the MIVAC to the FA terminal in the case of a 4-chip memory.

[Explanation of symbols]

10 ... graphic processor, 20 ... MIVAC, 30 ...
Frame buffer, 2014... Multiplexer, 201
5: input data latch, 2016: read data latch.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-188962 (JP, A) JP-A-63-83844 (JP, A) JP-A-59-55525 (JP, A) JP-A-63-83 6681 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 12/00-12/06

Claims (4)

(57) [Claims] 1. A memory controller for controlling data transfer between a memory for storing image data and a processor and between the memory and a display device , wherein the memory controller is connected to the memory, and the memory and the memory An m-bit terminal for sequentially transferring time-division m-bit (m is a natural number) data to and from the controller; n-bit terminals connected to the processor; n is a natural number n
> M) an n-bit interface for transferring data , connected to the display device, wherein the display device and the memory controller
To transfer serial data to and from the controller.
At least a 1-bit terminal, first conversion means for converting between a plurality of m-bit data via the m-bit terminal and n-bit data via the n-bit interface, and via the m-bit terminal Up multiple m-bit data
A memory controller comprising second conversion means for converting the serial data into serial data . 2. The method according to claim 1, wherein the data transmitted through the m-bit terminal and to be converted by the first conversion means is within a transfer time unit based on an address specified by the processor. A memory controller which is sequentially read from the memory a plurality of times by time division. 3. The method according to claim 1, wherein the first converting means includes:
From the memory sent via the m-bit terminal
A memory controller having storage means for temporarily storing image data . 4. The memory controller according to claim 1, wherein said second conversion means has a storage means for temporarily storing image data sent from said memory via said m-bit terminal. .