JP2853985B2 - Clock phase adjustment circuit and clock phase adjustment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device and a method for executing high-speed writing and reading (hereinafter referred to as "access") of data to and from a memory, wherein the phase of a clock signal for timing the access is adjusted. And a method for adjusting the clock phase.

[0002]

2. Description of the Related Art For example, as shown in FIG. 23, when data access is performed to a conventional synchronous dynamic random access memory (hereinafter, referred to as SDRAM) 2000, a memory interface device 1000 determines the data access timing. The clock signal to be taken is converted or rectified by a PLL 1010 into an internal clock signal and an external clock signal of a frequency used in the memory interface device 1000 and the SDRAM 2000 by using a clock signal input from the outside. Data access between the memory interface device 1000 and the SDRAM 2000 is executed in synchronization with the frequency.

The internal clock signal output from the PLL 1010 is temporarily buffered by an input buffer 1020, and is input to a flip-flop 1030, a flip-flop 1040 and a flip-flop 1050, respectively. At this time, the internal clock signal is temporarily buffered by the buffer 1060 and output to the SDRAM 2000, and the SDRAM 2000 operates in synchronization with the external clock signal.

In the flip-flop 1030, an address
An information signal for controlling the SDRAM 2000 (hereinafter, referred to as an SDRAM command) is latched and transmitted in synchronization with the internal clock signal. The SDRAM command is temporarily buffered in the output buffer 1070 and output to the SDRAM 2000. In the flip-flop 1040, write data input from the outside is latched and transmitted in synchronization with the internal clock signal. The write data is temporarily buffered in the output buffer 1080 and output to the SDRAM 2000.

The SDRAM 2000 reads out data stored in the SDRAM 2000 in synchronization with the external clock signal based on the SDRAM command. When the read data is input to the memory interface device 1000, it is first buffered once by the input buffer 1090, then latched by the flip-flop 1050, and transmitted to the outside of the memory interface device 1000 in synchronization with the internal clock signal. Is done.

As described above, data access to a series of memories is executed in synchronization with the external clock signal. When the interface shown in FIG. 23 and a clock frequency close to the performance limit of the SDRAM 2000 is used, the SDRAM 2
Since the access time of 000 is substantially equal to the time of one cycle of the clock signal, the timing chart of the SDRAM command and the read data synchronized with the internal clock signal is as shown in FIG.

The internal clock signal used in the memory interface device 1000 is temporarily buffered by the input buffer 1020 to have the phase timing shown in FIG. 24, temporarily buffered by the output buffer 1070 and shifted to the phase timing of the external clock signal shown in FIG. Input to the SDRAM2000, the SDRAM2000 operates in synchronization with an external clock signal.

The internal clock signal is input to flip-flops 1030, 1040 and 1050, respectively. The flip-flop 1030 latches the SDRAM command input from outside the memory interface, and synchronizes with the internal clock signal to output buffer 1070. The data is temporarily buffered and output to the SDRAM 2000 at the timing shown in FIG. Similarly, the flip-flop 1040 latches the write data input from outside the memory interface device and transmits it to the third output buffer 1080 in synchronization with the internal clock signal.
The data is temporarily buffered and output to the SDRAM 2000 at the timing shown in FIG.

The external clock signal is a delay due to the buffer in the output buffer 1060, and the phase is delayed by an amount corresponding to the internal clock signal. In the SDRAM command, the delay due to the latch in the flip-flop 1040 and the delay due to the buffer in the output buffer 1080 are combined. For read data, delay of external clock due to buffer of output buffer 1060, SD
The access delay required for data access of the RAM 2000 and the delay due to the buffer of the second input buffer 1090 are combined.

As described above, even in the interface at the clock frequency close to the performance limit of the SDRAM 2000, each delay time and the memory interface 1000
And the SDRAM 2000, the configuration is indispensable. Therefore, when viewed from the input terminal of the SDRAM 2000, it is difficult to secure the hold time by the external clock signal of the SDRAM command output from the memory interface device 1000.
Further, it is difficult to latch read data read from the SDRAM 2000 by the flip-flop 1050 in the memory interface device 1000 by the internal clock signal.

[0011] in FIG. 25 for example (a) and (b) are those respectively showing a read phase and a write phase of the AC specifications of the SDRAM frequency 83MH _Z. Each of and is a setup time that is the minimum value of the validity period of read and write data that must be maintained for data access before the rising of the external clock signal, and Is the hold time, which is the minimum value of the valid period of read and write data that must be maintained for data access after the rise.

Referring again to FIGS. 23 and 24,
When viewed from the input terminal of the SDRAM 2000, it is difficult to secure the hold time for the write data output from the memory interface device 1000, the SDRAM command and the external clock signal, and the data read from the SDRAM 2000 It is also difficult for the flip-flop 1050 to latch using the internal clock signal.

In order to solve the above problem, in the conventional technique, the setup time and the hold time are secured by outputting the internal clock signal and the external clock signal in FIG.

[0014]

SUMMARY OF THE INVENTION However, CPU
As the operating frequency increases, and the data processing capacity increases, the performance of the CPU and the like cannot be fully utilized by suppressing the frequency of the above-mentioned external clock signal. It has become difficult to meet the demand for increasing the frequency of the external clock signal to increase the data transfer rate.

Further, as described above, as the frequency of the external clock signal rises, the timing margin for data access becomes shorter, so that there is a slight performance difference as a quality problem of each component constituting the circuit. In addition, it has become difficult to secure a stable data access timing margin due to differences and fluctuations in electrical conductivity due to temperature differences and variations in position and time in a circuit.

[0016]

According to the first aspect of the present invention,
In order to solve the above problems, in a clock phase adjustment circuit that adjusts the phase of a clock signal to execute appropriate data access to an access target, the phase of the clock signal serving as a reference for operation is inverted by 180 degrees. Phase shifting means for shifting and outputting to the access target.
The clock is used as a reference for the operation.
A phase inverting section that inverts the phase of the signal by 180 degrees and outputs the inverted signal;
From the clock signal input from the phase inverter, a plurality of different
Multiple clocks that generate and output clock signals with different phases
Clock generator, and the plurality of clocks input from the plurality of clock generators.
Select one of the clock signals with different phases and
A phase selection unit for outputting to an access target;
Controlling the plurality of clock signals having different phases in order.
Next, output to the access target with the clock signal of each phase.
Attempts whether or not normal data access is possible.
Based on the result, the plurality of phase
One of the lock signals used for data access
A phase test control unit for selecting a clock signal.
It is characterized by the following.

[0017]

According to a second aspect of the present invention, in order to solve the above-mentioned problem, an appropriate data access to an access target is provided.
Clock to adjust the phase of the clock signal to perform
In the clock phase adjustment circuit, the clock signal
The phase of the signal is inverted by 180 degrees and shifted to
Phase conversion means for outputting to an access target;
Outputting a control signal for controlling the access to the access target
A signal output unit and a clock input from the phase conversion unit.
While maintaining a phase difference with the control signal and the control signal.
A sub-device that accesses an access target according to the control signal
Shift the clock signal and the control signal into a circuit
And sub-phase conversion means for outputting
Is what you do.

According to a third aspect of the present invention, there is provided a clock phase adjusting circuit according to the second aspect , wherein the plurality of clock signals having different phases are sequentially transmitted to the clock phase adjusting circuit.
Output to the access target and the normal
Data access is possible, and based on the results of the trial,
Then, from among the plurality of phase clock signals,
Phase test to select one clock signal for access
A sub-multiple clock generation unit , wherein the sub-phase conversion unit generates and outputs a plurality of clock signals having different phases from the clock signal input from the phase conversion unit; and One of the input clock signals having different phases is selected and the sub clock is selected.
A sub-phase selection unit that outputs to the circuit , the phase test control unit controls the sub-phase selection unit to sequentially output the plurality of different-phase clock signals to the sub-circuit, and outputs a clock of each phase. Signal to determine whether normal data access is possible, and selecting one clock signal to be used for data access from among the plurality of phase clock signals in the sub-phase selection unit based on the result of the trial. It is a feature.

According to a fourth aspect of the present invention, there is provided a data interface for generating a clock signal serving as a reference for timing of accessing an access target, and inputting / outputting data to / from the access target based on the clock signal. A clock phase adjustment method included in an ace and adjusting a phase of the clock signal to execute proper data access, wherein a phase test instruction step instructing the access target to execute a phase test, and the phase test instruction step A phase test sequence step of trially executing data access using a plurality of clock signals having different phases to the access target, and a clock signal having different phases based on a result of the trial in the phase test sequence step. For future data access from within A clock signal selection step of selecting the clock signal of the proper phase using Te is characterized in that it has a.

According to a fifth aspect of the present invention, there is provided a clock phase adjusting method according to the fourth aspect , wherein the phase test sequence step comprises the step of selecting one clock from the plurality of clock signals having different phases. A clock signal selecting step of selecting a signal; a test data writing step of writing predetermined test data to the access target based on the clock signal selected in the clock signal selecting step; A test data reading step of reading the written predetermined test data; a test data comparing step of comparing the predetermined test data with data read in the test data reading step; And a comparison result recording step of recording the compare results, is characterized in that to perform said plurality of different phases in the clock signal to the phase test sequence, respectively.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 9 of the accompanying drawings. In FIG. 1, reference numeral 1 denotes an interface device to which a clock phase adjusting circuit according to the present invention is applied.
Receives the clock signal of a frequency of 27MH _Z, it converts the frequency of the clock signal to the internal clock signal 81MH _Z, as well as operate in synchronization with the internal clock signal, and outputs to the memory to be accessed . 2 is operable SDRAM at 83MH _Z (Synchronous Dynamic Random Access Memory). The memory interface device 1 is composed of components indicated by reference numerals 10 to 21.

Reference numeral 10 denotes a clock signal having a frequency of 27 MHz input from the outside, and an 81 MHz clock serving as a reference for operation of each device described below.
a clock frequency converter 11 which converts the internal clock signal into an internal clock signal and outputs the internal clock signal.
Input buffer. Reference numeral 12 denotes a clock phase adjustment circuit according to an embodiment to which the clock phase adjustment circuit according to claim 1 is applied. An inverter 14 is a phase converter that shifts and outputs the phase of the internal clock signal input from the inverter 13, and the clock phase adjustment circuit 12 is configured by the inverter 13, the phase converter 14, and the selector 144. It is.

A first output buffer 15 temporarily buffers the internal clock signal input from the phase converter 14 and outputs the buffered signal to the SDRAM 2. The first output buffer 15 includes a clock phase adjusting circuit 12 and a first output buffer.
The output buffer 15 constitutes the phase adjusting means. Reference numeral 16 denotes a first flip-flop which latches the SDRAM command input from the outside and outputs the same in synchronization with the internal clock signal input from the first input buffer 11,
Reference numeral 17 denotes a second output buffer for temporarily buffering and outputting the SDRAM command input from the first flip-flop 16.

Reference numeral 18 denotes a second latch for latching write data input from the outside and outputting the latched data in synchronization with the internal clock signal.
A flip-flop 19 is a second flip-flop 18
A third output buffer for temporarily buffering the write data input from the SDRAM 2 and outputting the buffered data to the SDRAM 2. Reference numeral 20 denotes a second input buffer for temporarily buffering and outputting read data input from the SDRAM 2, and 21 latches the read data input from the second input buffer and outputs the latched data to the outside in synchronization with the internal clock signal. This is the third flip-flop.

The first flip-flop 16, the second output buffer 17, the second flip-flop 18, the third output buffer 19,
The second input buffer 20 and the third flip-flop 21 constitute the data input / output means, and data access in the SDRAM 2 is performed based on the SDRAM command. Here, a timing chart of data access in the SDRAM 2 is shown in FIG. However, all the timing charts shown below should be considered equally for all buffers.
Assuming 20pF capacitance, all flip-flops have 1.5ns setup time and 0.8ns hold time
Is assumed.

Is a phase adjuster 14 for the external clock signal.
And a delay time of the first output buffer 15 with respect to the internal clock signal. Is the first flip-flop 16
Delay time of 0.415 ns and the second output buffer 17
1.655ns total delay time of 1.240ns
Is a total delay time 4.754 ns obtained by adding the maximum delay time 1.143 ns by the first flip-flop 16 and the maximum delay time 3.611 ns by the second output buffer 17, and (A) on the SDRAM command is 3.099 ns, and the above (A) is an invalid period. (B) is the same as (A) 3.099
ns invalid period.

Alternatively, the access delay time 11 ns in the SDRAM 2 and the maximum delay time 0.
The total delay time of 337 ns is 11.337 ns, and the frequency is 8
The 1/2 cycle time 12.3ns of 1 MH _Z time obtained by subtracting the a time obtained by subtracting from the. Period after the rise of the external clock signal in the data access in SDRAM, hold time must be held 4ns and delay time obtained by adding the delay time 0.158ns by the second input buffer 20 is 4.158Ns, it is at a clock frequency 81MH _Z It is the time obtained by subtracting the above from the time 12.3 ns and adding it, that is, the valid time of the read data 5.12.
ns.

As described above, in the circuit configuration shown in FIG. 1 as shown in FIG. 2, the SDRAM command output from the memory interface device 1 as seen from the input terminal of the SDRAM 2 must have a setup time and a hold time for an external clock signal. Further, in the memory interface device 1, a setup time and a hold time for latching the read data read from the SDRAM 2 by the third flip-flop 21 by the internal clock signal can be secured.

FIG. 5 is a diagram showing the clock phase adjusting circuit 12 shown in FIG. 1. As shown in FIG. 5, the clock phase adjusting circuit 12 includes an inverter 13, a delay unit (a plurality of clock generators). (Unit) 140 to 143 and a selector 144. The inverter 13 is the first input buffer 11 of FIG.
A phase inversion section for phase 180 degrees inversion and outputs the internal clock signal 81MH _Z input from. Delay device 140, 141, 14
Reference numerals 2 and 143 each output a phase of the internal clock signal input from the inverter 13 by shifting each predetermined phase, and constitute a plurality of clock generation units as a whole. The selector 144 includes delay units 140, 141, 142, and 143.
And selects and outputs one of the internal clock signals having different phases, respectively, which is input from the controller, and constitutes a phase selector.

In this embodiment, the operation units 140, 141, and 14
Although four of 2 and 143 are provided, the number of the arithmetic units may be set arbitrarily by the designer without any problem.
However, as described later, in order to trace an appropriate clock phase even during operation, it is preferable to operate normally at three or more adjacent phases. Figure 2 shows SDRAM
2 is a timing chart of a read phase when data is read from the SDRAM 2 as shown in FIG.
Valid period of read data read from is 5.121n
s, and since the third flip-flop 21 in the memory interface device 1 latches in synchronization with the internal clock signal, the setup time and the hold time of the third flip-flop 21 are 1.5 ns and 0.8 ns as described above.
When ns is secured, the phase adjustment range in which data can be read and written normally is 5.121 ns-1.5 ns-0.8 ns = 2.821 ns.

As described above, the step width of the plurality of clock generators in the phase converter 14 is determined to be 1.00 ns so that three types of phases can always exist within this range. Next, the phases of the inverted internal clock signals whose phases are inverted by 180 degrees by the inverter 13 are calculated by the arithmetic units 140 to 143 and the selector.
The following describes how much the phase of the external clock signal shifted through 144 and output to the SDRAM 2 can be adjusted.

First, FIG. 3 is a timing chart showing the delay time of the external clock signal output to the SDRAM 2 when the read data read from the SDRAM 2 just secures the setup time 1.5 ns of the third flip-flop 21 of FIG. Similarly, FIG. 4 is a chart showing the delay time of the external clock signal output to the SDRAM 2 when the read data read from the SDRAM 2 just secures the hold time 0.8 ns of the third flip-flop 21 of FIG. It is a timing chart.

3 and 4 mean the same period as in FIG. 2, the setup time of the third flip-flop 21 in FIG. 3 is 1.5 ns, and the hold time of the third flip-flop 21 in FIG. To 0.
Assuming 8 ns, the delay time of the external clock signal with respect to the internal clock signal whose phase is inverted by 180 degrees in FIGS. 3 and 4 is calculated by the following equation (1) for FIG. 3 and by the following equation (2) for FIG. can do.

Delay time = 12.3 / 2 − + (− 1.5) Equation (1) Delay time = 12.3 / 2 − (− 0.8) Equation (2) Calculation results of the above equations (1) and (2) By outputting a clock signal whose phase is shifted from 2.792 ns to 5.713 ns from a clock signal having a phase opposite to that of the internal clock signal of the memory interface device 1 to the SDRAM 2, the read data from the SDRAM 2 is normally output by the third flip-flop 21. You can see that you can latch.

Next, the writing phase to the SDRAM 2 will be examined. FIG. 6 shows the SDRA when the write data and the SDRAM command have just secured the setup time with the external clock signal when viewed from the input terminal of the SDRAM2.
This is the delay time of the external clock signal output to M2. Similarly, in FIG. 7, the write data and the SDRAM command are output to the SDRAM 2 when the hold time with the external clock signal is just secured.
4 shows a delay time of the external clock signal with respect to the internal clock signal whose phase has been inverted.

As in the case of the read phase, the setup time of the SDRAM 2 in FIG. 6 is set to 3.5 ns, the hold time of the SDRAM 2 in FIG.
6 and 7, the delay time of the external clock signal with respect to the 180 ° phase-inverted internal clock signal can be calculated by the following equation (3), and FIG. 7 can be calculated by the following equation (4).

Delay time = + 3.5-12.3 / 2 Equation (3)-+ 1.5 +-= 12.3 Equation (4) From the above calculation result, the phase from the clock signal having the opposite phase to the internal clock signal of the memory interface device 1 is obtained. 2.104ns
By outputting the clock signal shifted by 6.306 ns from the SDRAM 2 to the SDRAM 2, the SDRAM 2 can normally write the data output from the memory interface device 1.

As described above, from the calculation results of the read phase and the write phase, the phase of the external clock signal that can be normally interfaced with the SDRAM 2 is 2.792 ns from the clock signal opposite in phase to the internal clock signal of the SDRAM 2 in the read phase. It can be seen that this is the case of an external clock signal shifted within a range of 5.613 ns from. Considering the clock phase adjustment circuit 12 in FIG.
For example, as shown in FIG.

As described above, in this embodiment, the internal clock signal for the internal operation of the memory interface device 1 is
By generating an external clock signal to be output to the SDRAM 2 by inverting the phase by 180 degrees and then shifting the phase, the amount of the phase shift can be reduced, and the phase shift is stable with respect to temperature change and voltage fluctuation. Thus, it is possible to realize stable reading and writing of data in a high-speed memory interface.

(Embodiment 2) A second embodiment of the present invention will be described below with reference to FIGS. 10, reference numeral 3 denotes a memory interface device to which the clock phase adjusting device according to the present invention is applied, and reference numeral 4 denotes a memory interface device shown in FIG.
Reference numeral 5 denotes an SDRAM equivalent to the SDRAM 2. Reference numeral 5 denotes a slave chip which inputs a sub external clock signal for setting operation timing and a control signal for instructing the operation from the memory interface device 3, and executes data access with the SDRAM 4.

The memory interface device 3 is composed of components indicated by reference numerals 30 to 45 in FIG. 30 is a clock frequency converter equivalent to the clock frequency converter 10 shown in FIG. 1, and 31 is a first input buffer equivalent to the first input buffer 11 shown in FIG. 32 is a clock phase adjustment circuit equivalent to the clock phase adjustment circuit 12 shown in FIG. 1, 33 is an inverter equivalent to the inverter 13 shown in FIG. 1, and 34 is a phase conversion circuit shown in FIG. 1, a first output buffer 35 equivalent to the first output buffer 15 shown in FIG. 1, and the inverter 33 and the phase converter 34 control the clock phase adjusting circuit 32. Make up.

36 is the first flip-flop shown in FIG.
A first flip-flop 16 is equivalent to 16 and a second output buffer 37 is equivalent to the second output buffer 17 shown in FIG. Reference numeral 38 denotes a second flip-flop equivalent to the second flip-flop 18 shown in FIG. 1, and reference numeral 39 denotes a third output buffer equivalent to the third output buffer 19 shown in FIG. 40 is a second input buffer equivalent to the second input buffer 20 shown in FIG. 1, and 41 is a third flip-flop equivalent to the third flip-flop 21 shown in FIG.
Next, the configuration of the sub-phase adjusting means, which is a feature of the present embodiment, will be described. Reference numeral 42 denotes a fourth flip-flop which latches the control signal input from the outside and transmits the same in synchronization with the internal clock signal input from the first input buffer. Reference numeral 43 denotes a fourth flip-flop which controls the clock signal input from the phase adjusting means. A clock signal whose phase is shifted based on a phase selection signal input from a phase test control unit that executes a phase test sequence (not shown) is output, and the control signal input from the fourth flip-flop 42 is input and output. This is a sub clock phase adjustment circuit.

Reference numeral 44 denotes a fourth output buffer for temporarily buffering the clock signal input from the sub clock phase adjustment circuit 43 and outputting a sub external clock signal to the slave chip 5, and reference numeral 45 denotes a sub clock phase adjustment circuit 43. Buffering the control signal input from the
And a fifth output buffer for outputting to the
The sub-phase adjusting means is constituted by (45).

Next, the range in which the phase can be adjusted by the sub clock phase adjusting circuit 43 in FIG. 10 will be examined. The sub-clock phase adjusting circuit 43 uses the external clock signal so that the read data input from the SDRAM 4 can be latched by a flip-flop (not shown) in the slave chip 5 in synchronization with the sub-external clock signal input from the fourth output buffer 44. Is shifted and output.

The timing of the read data output from the SDRAM 4 is determined by the memory interface device 3
To output the external clock signal. Therefore, as shown in FIG.
The sub clock adjustment circuit 43 further shifts the phase of the external clock signal output to the SDRAM 4 to adjust the phase of the sub external clock signal output to the slave chip 5.

FIG. 11 shows the timings of the internal clock signal in the memory interface device 3, the external clock signal output from the memory interface device 3, the sub-external clock signal and the SDRAM command, and the read data read from the SDRAM 4. It is a timing chart shown. Each from in FIG.
The symbols in FIG. 2 correspond to the delay times due to the phase shift of the sub external clock signal with respect to the external clock signal.

As shown in FIG. 11, the valid period of the read data read from the SDRAM 4 based on the external clock signal is only about 5.121 ns, and the flip-flop (not shown) in the slave chip 5 uses the memory interface device 3. Since the latch time is latched in synchronization with the sub-external clock signal input from, the setup time and hold time of the flip-flop are secured, and the phase adjustment range in which data can be normally accessed is 5.12.
1 ns-1.5 ns-0.8 ns = 2.821 ns. A clock phase adjusting circuit that can always have three types of phases within the range
The step width of the phase shift at 32 is 1.00 ns.

Next, the SDRA is sent from the memory interface device 3.
The range in which the phase of the sub-external clock signal output to the slave chip 5 after being shifted in phase with respect to the external clock signal output to the M4 can be adjusted will be described below. First, as shown in FIG. 12 and FIG.
Then, the delay time of the sub-external clock signal when the read data read out in synchronization with the external clock signal just secures the setup time of the flip-flop (not shown) in the slave chip 5 is determined.
Similarly, as shown in FIGS. 14 and 15, when the read data read from the SDRAM 4 has just secured the hold time of the flip-flop (not shown) in the slave chip 5, the memory interface device 3 A delay time of the sub-external clock signal to be output is obtained. 12, 13, 14, and 15 correspond to those in FIG. 11.

As a result, the memory interface device 3
Calculates the phase from the external clock signal output to the SDRAM 4.
When the sub-external clock signal shifted from 0.537 ns to 3.358 ns is output to the slave chip 5, it is understood that the read data read from the SDRAM 4 can be normally latched by the flip-flop in the slave chip 5. Also,
10, 11, 12, 13, 14, and 15
Is a control signal input directly from the memory interface device 3 to the slave chip 5, and the control signal is read out from the SDRAM 4 because the control signal is output after being delayed by the delay time in the memory interface device 3. If the phase of the clock signal is such that the read data can be latched, the slave chip 5 can latch without any problem.

From this result, as shown in FIG. 16, for example, the sub-clock phase adjustment circuit 43 in FIG. 10 has a phase delay amount of four steps with a step width of 1.00 ns every 0.2 ns of the basic delay time. As described above, in the present embodiment, since the clock phase adjustment circuit 32 and the sub clock phase adjustment circuit 43 are independent, control for outputting clock signals having different phases to the SDRAM 4 and the slave chip 5 is easy. is there.

The memory interface device 3 and the SDRA
If the clock phase adjustment between M4 is performed correctly, the data access placed between SDRAM 4 and slave chip 5 is adjusted at the same time even if the amount of phase shift by sub clock phase adjustment circuit 43 is constant. Things. Further, the clock phase adjusting circuit 32 and the sub-clock phase adjusting circuit 43 are provided with the memory interface device 3 having almost uniform conditions.
With the arrangement above, the clock phase adjustment circuit 32 and the sub-clock phase adjustment circuit 43 can be used under substantially the same conditions with respect to fluctuations in use conditions due to temperature changes and the like.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to FIGS. FIG.
Reference numeral 100 denotes a memory interface device which executes input / output of a clock signal and data serving as a reference for operation with respect to a data access target which is an asynchronous DRAM, in particular.
Is an EDO (extended data) as an access target for performing data access through the memory interface device 100.
ata out) mode and is an asynchronous dynamic RAM (hereinafter simply referred to as DRAM).

Reference numeral 110 denotes a clock frequency converter equivalent to the clock frequency converter 30 shown in FIG. 10, and reference numeral 111 denotes a first input buffer equivalent to the first input buffer 31 shown in FIG. Reference numeral 112 denotes the point of this embodiment.
Reference numeral 113 denotes an address strobe phase adjustment circuit for adjusting the phase of the internal clock signal input from the input buffer 111. Reference numeral 113 denotes an externally input RAS (ROWADDRESS STROBE) or CAS (CAS) input in synchronization with the rise of the internal clock signal. COLUMN ADDRESS STROBE), and 114 is an inverter equivalent to the inverter 33 shown in FIG. 10, and 115 is a phase converter equivalent to the phase converter 34 shown in FIG. The reference numeral 116 denotes a first output buffer equivalent to the first output buffer 35 shown in FIG.

The logical AND circuit 113, the inverter 114, and the phase converter 115 constitute an address strobe phase adjusting circuit 112. Reference numeral 117 denotes a first flip-flop equivalent to the first flip-flop 36, and reference numeral 118 denotes a second output buffer equivalent to the second output buffer 37. 119 is a second flip-flop equivalent to the second flip-flop 38,
Reference numeral 120 denotes a third output buffer equivalent to the third output buffer 39.

Reference numeral 121 denotes a second input buffer equivalent to the second input buffer 40, and reference numeral 122 denotes a third flip-flop equivalent to the third flip-flop 41. FIG. 19 shows the internal clock signal in the memory interface device 100, the RAS (or the CAS) output from the memory interface device 100, the sub-external clock signal and the DRAM command, and the timing of read data read from the DRAM 200. It is a timing chart shown. Figure 1 below
9 will be described.

Is a delay time by the phase converter 115 and the first output buffer 116 at the fall of the RAS (or the CAS) with respect to the fall of the internal clock signal, and is the delay time with respect to the rise of the internal clock signal. First flip-flop 11 in DRAM command
7, the minimum delay time of 0.415 ns and the second output buffer 11
1.655n delay time which is the sum of 1.240ns minimum delay time by 8
s is the first flip-flop 11 in the DRAM command with respect to the rise of the internal clock signal.
7 and the second output buffer 11
Delay time of 4.754n, which is the sum of 3.611ns maximum delay time by 8
s.

Alternatively, the RAS (or the CAS) is established.
Frequency 81 in the read data for falling
MH_ZWhen the above is subtracted from 1/2 of 12.3 ns cycle time of
This is the delay time obtained by subtracting the interval from the above. Is the above
The read data with respect to the rise of the external clock signal
13ns access delay time in the DRAM 200 and the second
Summed the maximum delay time 0.337ns by input buffer 121
The delay time is 13.337 ns, and the RAS (or the C
From the fall of AS) to data access in DRAM
In which the read data must be held
5 ns and delay by the second input buffer 121
The delay time is 5.158 ns, which is the sum of the time 0.158 ns.
Clock frequency 50MHZ _ZThe cycle time from 20 ns to
Is the time obtained by subtracting and adding
The valid period is 10 ns, which is the period during which data can be read.
You.

As described above with reference to FIG. 19, the RAS (or the CAS) and the D
The valid period of the read data read based on the RAM command is only about 10 ns, ensuring a setup time and a hold time of the flip-flop,
The phase adjustment range for normal data access is 10
ns−1.5 ns−0.8 ns = 7.7 ns. Always within the range 3
The step width of the phase shift in the address strobe phase adjustment circuit 112 in which various types of phases can exist is, for example, 2.5 ns.

As described above, in this embodiment, the address strobe phase adjustment circuit 112 inverts the phase of the internal clock signal for the internal operation of the memory interface device 180 by 180 degrees, shifts the phase, and outputs the inverted signal to the DRAM 200. Since an external clock signal is generated, the amount of the phase shift can be reduced, and a stable phase shift can be realized in response to a change in temperature or a change in voltage. This realizes stable reading and writing of data.

(Embodiment 4) A fourth embodiment of the present invention will be described below with reference to FIGS. FIG. 20 is a circuit diagram showing a clock phase adjusting circuit in which the clock phase adjusting method of the present invention is applied to the memory interface device 3 of FIG. Reference numeral 52 denotes a phase test control circuit that inputs and outputs various signals to and from a CPU (not shown) and executes the phase test.
The phase test control circuit 52 and a monitoring circuit (not shown)
Table 1 shows a list of registers for handshaking by U).

(Hereinafter, blank)

[Table 1]

Reference numeral 50 denotes a clock frequency converter equivalent to the clock frequency converter 30; 51, a first input buffer equivalent to the first input buffer 31;
The first input buffer 51 constitutes the clock signal generating means. 53 is a clock phase adjustment circuit equivalent to the clock phase adjustment circuit 32 shown in FIG.
54 is an inverter equivalent to the inverter 33 shown in FIG. 10, 55 is a phase converter equivalent to the phase converter 34 shown in FIG. 10, and the clock phase adjusting circuit 53 is shown in FIG. It is configured by an inverter 54 and a phase converter 55.

Reference numeral 56 denotes the first output buffer 35 shown in FIG.
Is a first output buffer equivalent to the first flip-flop 36 shown in FIG. 10, and 58 is a first output buffer equivalent to the second output buffer 37 shown in FIG. Two output buffers. 59 is a second flip-flop equivalent to the second flip-flop 38 shown in FIG. 10, and 60 is a third output buffer equivalent to the third output buffer 39 shown in FIG.

Reference numeral 61 denotes the second input buffer 40 shown in FIG.
Is a second input buffer equivalent to, and 62 is a third flip-flop equivalent to the third flip-flop 41 shown in FIG. 63 is the fourth flip-flop shown in FIG.
42 is a fourth flip-flop equivalent to 42, 64 is a sub-clock phase adjustment circuit equivalent to the sub-clock phase adjustment circuit 43 shown in FIG. 10, and 65 is the fourth output buffer 44 shown in FIG. An equivalent fourth output buffer 66 is shown in FIG.
Is a fifth output buffer equivalent to the fifth output buffer 45 shown in FIG.

The fourth flip-flop 63, the sub clock phase adjustment circuit 64, the fourth output buffer 65 and the fifth output buffer 66 constitute the sub phase conversion means. The external clock signal to be output to the SDRAM 7 and the sub-clock phase adjustment circuit 64 generate a plurality of the sub-external clock signals to be output to the slave chip 8. A phase test is executed before the data access in order to select a phase of a clock signal to be used at the time of data access from each of the plurality of external clock signals and the sub-external clock signals. , And executes data access using clock signals having phases respectively designated by a CPU (not shown).

Also, during the normal processing, the time during which the memory access is suspended is used, and during the data access, when the execution of the phase test is designated by a CPU (not shown), the phase test is performed. The test results are stored in a CPU
Notify. However, initialization processing such as mode register setting is not performed. The above processing is performed in accordance with an instruction from a CPU (not shown).

Next, the procedure of the phase test will be described with reference to the flowchart of FIG. Note that M in FIG.
1, M2, M3, M4, M5, M6 and M7 indicate each step in this flowchart. M
1, M2 and M3 constitute the phase test instruction step, M4 and M5 constitute the phase test sequence step, and M6 and M3
7 constitutes the clock signal selecting step.

Next, M1, M2, M3, M4, M5, M6
And the contents of each process in M7 will be described. First, M1
After the reset of the previous phase test, the phase control test circuit 52 monitors the test flag signal in Table 1 output from the CPU (not shown). The CPU (not shown) instructs the execution of the phase test by outputting the test flag signal = 1 to the phase control test circuit 52. Usually, the test flag signal is 0.

Next, at M2, when the phase control test circuit 52 detects the test flag signal = 1,
The phase control test circuit 52 notifies the slave chip 8 of an instruction to shift to the phase test mode. In M3, the CPU (not shown) sets the test flag signal to 0. If the flag is set to 1 during data access, it waits until the memory interface device 6 is suspended, and executes the phase test sequence.

Next, in M4, the test mode indicated by the phase test mode instruction signal in Table 1 above;
The first phase test mode is in accordance with a clock phase indication signal indicated to the SDRAM 7 indicated by the clock phase indication signal, and the second phase test mode is indicated by a clock phase indication signal indicated to the slave chip 8 indicated by the clock phase indication signal. A phase test sequence described later is performed, and when the phase test sequence is completed, the test result is written to the first phase test result signal and the second phase test result signal in Table 1 above.

At M5, the first phase test result signal and the second phase test result signal in Table 1 which are the test results are output to the CPU (not shown). In M6, PHASE_INT in Table 1 which is an interrupt signal indicating the end of the phase test is output to the CPU (not shown), and the present phase test is ended. Finally, in M7, a clock signal having an appropriate phase is selected from the plurality of clock signals having different phases based on the first phase test result signal and the second phase test result signal in Table 1, and the selected result is clocked. Phase adjustment circuit 53 and sub clock phase adjustment circuit
64 are notified by the phase selection signal.

It should be noted here that the SDRAM 7 and the slave chip 8 operate at the phases indicated by the first clock phase instruction signal and the second clock phase instruction signal in Table 1 except during the phase test sequence. Yes, and at the end of the test including the initialization of the SDRAM 7, the initialization of the SDRAM 7 is always executed at the phase designated by the first clock phase instruction signal and the second clock phase instruction signal in Table 1.

Next, a subroutine to which one embodiment of the phase test sequence step (corresponding to claim 6) in M4 of the above phase test is applied will be described with reference to FIG. Note that S1 to S11 in FIG. 22 indicate each step of this subroutine. Table 2 below shows the types of the test data used in one phase test sequence and the order of writing (reading order) to the SDRAM 7. The test data used in the phase test sequence is stored in advance in a phase test data table in the phase test control circuit, and eight types are considered in consideration of fluctuations in the power supply of the memory interface device 6 and the SDRAM 7 and the like. It is prepared.

[0075]

[Table 2]

First, the memory interface device 6
A method of determining whether the phase of the clock signal output to the RAM 7 is appropriate will be described in detail. S1 constitutes the clock signal selection step of selecting and outputting one clock signal from clock signals having different phases, each of which is generated as a plurality of candidates for the external clock signal by the phase converter 55, and S2 is And writing the test data into the SDRAM 7.

S3 constitutes the test data reading step for reading predetermined test data written in the SDRAM 7 in the test data writing step, and S4 includes the data read in the test data reading step and the test data reading step. The test data comparing step for comparing predetermined test data is constituted, and S5 and S6 constitute the comparison result recording step.

In S1, the amount of phase shift in the clock phase adjusting circuit 53 is set based on the first phase test mode clock phase instruction signal shown in Table 1 above. Next, in S2, predetermined test data in the phase test data table is written to the SDRAM 7. Here, the state of the test data at this time is referred to as test data (A).

In S3, the test data written in the SDRAM 7 in S2 is read from the SDRAM 7. The state of the test data at this time is referred to as test data (B). Then, in S4, the predetermined test data is compared with the test data (B). If the predetermined test data and the test data (B) match in the comparison, the phase shift amount in the clock phase adjustment circuit 53 set based on the first phase test mode clock phase instruction signal is appropriate. In S6, the first phase test result signal in Table 1 is set to 1. On the other hand, if the predetermined test data and the test data (B) do not match in the comparison,
In the phase test mode, the phase shift amount in the clock phase adjusting circuit 53 set based on the clock phase instruction signal is inappropriate. In S5, the first phase test result signal is set to 0, and the phase test mode is set. Notify the end.

Next, a method of determining whether the phase of the clock signal output to the slave chip 8 by the memory interface device 6 is appropriate will be described in detail. S7 constitutes the clock signal selecting step,
S8 constitutes the test data reading step, S9 constitutes the test data comparison step, and S10 and S11 constitute the comparison result recording step.

First, in S7, the phase shift amount in the sub clock phase adjustment circuit 64 is set based on the second phase test mode clock phase instruction signal shown in Table 1 above. Next, in S8, the test data (A) is read from the SDRAM 7 to the slave chip 8. At this time, the slave chip 8
The state of the test data read out to the test data (C)
And

In step S9, the predetermined test data is compared with the test data (C). If the predetermined test data and the test data (C) match in the comparison, Two-phase test mode The phase shift amount in the sub-clock phase adjustment circuit 64 set based on the clock phase instruction signal is appropriate, and the flow shifts to S11 to set the second phase test result signal in Table 1 to 1. Then, the present phase test sequence is completed. On the other hand, if the predetermined test data and the test data (C) do not match in the comparison result, the sub clock phase adjustment circuit 64 set based on the second phase test mode clock phase instruction signal in Table 1 above. Since the phase shift amount is inappropriate, the process shifts to S10, the second phase test result signal in Table 1 is set to 0, and the present phase test sequence ends.

As described above, when the phase test is executed, the following two factors are considered as causes for the inconsistency between the predetermined test data and the data read from the SDRAM 7. First, as the first cause, the rising phase of the clock signal output to the SDRAM 7 used in the phase test and the setup time or the hold time, which is the timing condition for writing the SDRAM command or the predetermined test data, are not satisfied. Therefore, it is considered that the predetermined test data could not be correctly written in the SDRAM 7. When the phase of the SDRAM command and the phase of the clock signal output to the SDRAM 7 do not satisfy the timing conditions of the SDRAM 7, the test data may not be read correctly.

As a second cause, although the writing of the predetermined test data to the SDRAM 7 has been performed correctly, the SDRAM 7
7 cannot be correctly latched by the third flip-flop 62.
When the phase test is performed during a data access period in the SDRAM 7, the SDRAM 7
If there is no match between the predetermined test data and the read data, the data may not have been written to the address of the SDRAM 7 for the phase test sequence. There is a possibility of breaking.

Therefore, when the phase test is executed using the period during which the memory access is suspended during the execution of the normal processing, about one phase before and after the phase of the clock output to the SDRAM 7 at that time is determined. It is preferable to test. Since the read timing is stricter than the write timing to the SDRAM, there is little possibility of destroying data already written to the SDRAM by such a phase shift. Assuming this, the phase difference between the phases is set so that data access to the SDRAM 7 can always be performed correctly with clock signals of three types.

Further, the phase variation due to temperature or the like does not occur suddenly, and the test cycle is set to a certain cycle (for example, 1
(Approximately 30 times per second), the trial with the clock signals of the three phases is sufficient. As described above, in the present embodiment, by performing a phase test in advance by using predetermined test data with a plurality of clock signals having different phases, accurate data access in a high-frequency clock signal is realized. A clock signal having an appropriate phase can be output to a data access target in response to a change in temperature or a change in voltage. Further, the phase test sequence is realized by a simple method.

[0087]

According to the first aspect of the present invention, a clock signal to be output to a data access target is generated by inverting the phase of the clock signal by 180 degrees and further shifting the clock signal. Therefore, for example, when the access target is a RAM, in order to secure a setup time and a hold time necessary for synchronizing a command signal output from the interface side to the RAM to each signal such as an external clock signal, and The clock signal is greatly increased in order to secure the setup time and hold time required for latching data such as read data read from the target by an interface-side flip-flop according to the internal clock signal that is the internal operation clock of the interface device. Even when it is necessary to shift the phase, the amount of phase shift can be reduced, and the circuit configuration can be simplified.

[0088] Also, each other, from among the different phases plurality of clock signals, based on a result of attempting to whether it is possible to successfully access using the clock signal, selects a clock signal used for the subsequent data access Therefore, an appropriate clock signal can be output in response to a change in temperature or a change in voltage.

[0089] According to the second aspect of the present invention, since against <br/> response to the sub-circuit by-phase converting means is provided, even for a plurality of access target, corresponds with a simple circuit configuration can do. Further, since the phase conversion means and the sub-phase conversion means are arranged in the device having substantially the same environmental conditions, even if the access targets are related to each other, the access operation can be performed in response to a change in use conditions due to a temperature change or the like. Can be stabilized.

According to the invention described in claim 3 , according to claim 2,
In addition to the effects of the above-mentioned invention, the sub-phase conversion means is also claimed
The same effect as that of the invention described in Item 1 can be obtained. Claim
According to the invention described in Item 4 , by performing a phase test in advance by using predetermined test data with a plurality of clock signals having different phases, accurate data access in a high-frequency clock signal is realized. A clock signal having an appropriate phase can be output to an access target in response to a change in temperature or a change in voltage.

In the fifth aspect of the present invention, the fourth aspect
The described phase test sequence can be realized by a simple circuit configuration and method.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a memory interface device to which a first embodiment of a clock phase adjusting circuit according to the present invention is applied.

FIG. 2 is a timing chart of signals input to and output from the SDRAM 2 of FIG.

FIG. 3 is a timing chart of a read phase when a setup time of 1.5 ns of a third flip-flop 21 of FIG. 1 is secured.

FIG. 4 is a holding time of a third flip-flop 21 of FIG. 1;
6 is a timing chart of a reading phase when 0.8 ns is secured.

FIG. 5 is a circuit diagram showing a detailed configuration of a clock phase adjustment circuit of FIG. 1;

FIG. 6 is a timing chart of a write phase when a setup time of 3.5 ns of the first flip-flop 16 of FIG. 1 is secured.

FIG. 7 is a hold time of a first flip-flop 16 of FIG. 1;
6 is a timing chart of a write phase when 1.5 ns is secured.

FIG. 8 is a circuit diagram showing a preferred embodiment of the clock phase adjustment circuit in the first embodiment.

FIG. 9 is a circuit diagram showing a practical mode of the clock phase adjustment circuit in the first embodiment.

FIG. 10 is a circuit diagram showing a memory interface device to which a second embodiment of the clock phase adjusting circuit of the present invention is applied.

11 is a timing chart of signals input to and output from the SDRAM 4 in FIG.

12 is a timing chart of a read phase when a setup time of 1.5 ns for latching data read from the SDRAM 4 in FIG. 10 by a flip-flop in the slave chip 5 is secured.

13 shows data read from the SDRAM 4 of FIG.
5 is a timing chart of a read phase when a setup time of 1.5 ns for latching by a flip-flop in a slave chip 5 is secured.

FIG. 14 shows data read from the SDRAM 4 of FIG.
5 is a timing chart of a read phase when a hold time of 0.8 ns for latching by a flip-flop in a slave chip is secured.

FIG. 15 shows data read from the SDRAM 4 of FIG.
5 is a timing chart of a read phase when a hold time of 0.8 ns for latching by a flip-flop in a slave chip is secured.

FIG. 16 is a circuit diagram showing a preferred embodiment of a sub clock phase adjustment circuit in the second embodiment.

FIG. 17 is a circuit diagram showing a preferred embodiment of a sub clock phase adjustment circuit according to the second embodiment.

FIG. 18 is a circuit diagram showing a memory interface device to which a third embodiment of the clock phase adjusting circuit of the present invention is applied, particularly a memory interface device corresponding to an asynchronous memory.

19 is a timing chart of signals input to and output from the DRAM of FIG. 18;

FIG. 20 is a circuit diagram showing a memory interface device to which a fourth embodiment of the clock phase adjusting circuit of the present invention is applied.

FIG. 21 is a flowchart illustrating a main routine of a clock phase adjusting method according to the fourth embodiment.

FIG. 22 is a flowchart showing a subroutine of step M4 in FIG. 21.

FIG. 23 is a circuit diagram showing a conventional memory interface device.

24 is a timing chart of signals input to and output from the SDRAM 2000 in FIG.

FIG. 25A is a timing chart showing AC specifications in a reading phase, and FIG. 25B is a timing chart showing AC specifications in a writing phase.

[Explanation of symbols]

Reference Signs List 1 memory interface device 2 SDRAM (synchronous dynamic random access memory) 3 memory interface device 4 SDRAM (synchronous dynamic random access memory) 5 slave chip 6 memory interface device 7 SDRAM (synchronous dynamic random access memory) 8 slave chip 10 clock Frequency converter 11 First input buffer 12 Clock phase adjustment circuit 13 Inverter 14 Phase converter 15 First output buffer 16 First flip-flop 17 Second output buffer 18 Second flip-flop 19 Third output buffer 20 Second input buffer 21 Third flip-flop 30 Clock frequency converter 31 First input buffer 32 Clock phase adjustment circuit 33 Inverter 34 Phase converter 35 1 output buffer 36 first flip-flop 37 second output buffer 38 second flip-flop 39 third output buffer 40 second input buffer 41 third flip-flop 42 fourth flip-flop 43 sub-clock phase adjustment circuit 44 fourth output buffer 45 Fifth output buffer 50 Clock frequency converter 51 First input buffer 52 Phase test control circuit 53 Clock phase adjustment circuit 54 Inverter 55 Phase converter 56 First output buffer 57 First flip-flop 58 Second output buffer 59 Second flip-flop Reference Signs List 60 third output buffer 61 second input buffer 62 third flip-flop 63 fourth flip-flop 64 sub-clock phase adjustment circuit 65 fourth output buffer 66 fifth output buffer 100 memory interface device DESCRIPTION OF SYMBOLS 10 Clock frequency converter 111 1st input buffer 112 Address strobe phase adjustment circuit 113 Logical AND circuit 114 Inverter 115 Phase adjustment circuit 116 1st output buffer 117 1st flip-flop 118 2nd output buffer 119 2nd flip-flop 120 3rd Output buffer 121 Second input buffer 122 Third flip-flop 140 to 143 Delay unit 144 Selector 200 DRAM with EDO (extended data out) mode (asynchronous dynamic random access memory)

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takayuki Kobayashi 4-36-19 Yoyogi, Shibuya-ku, Tokyo Inside Graphics Communication Laboratories Inc. (72) Inventor Shunji Nakatomi Yoyogi, Shibuya-ku, Tokyo 4-36-19, in Graphics Communication Laboratories, Inc. (72) Inventor Ryuji Saito 4-36-19, Yoyogi, Shibuya-ku, Tokyo, Japan In Graphics Communication Laboratories (72) Inventor Kenichi Tominaga 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Yutaka Okada 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi, Ltd. (72) Inventor Koji Asada Hitachinaka, Ibaraki Pref. 1410 Inada Ichiichi Hitachi, Ltd. Personal Media Equipment Division (56) References JP-A-6-124136 (JP, A) JP-A-4-253321 (JP, A) JP-A-5-8629 (JP, U (58) Fields surveyed (Int. Cl. ⁶ , DB name) G06F 1/04-1/14

Claims (5)

(57) [Claims] A clock phase adjusting circuit for adjusting a phase of a clock signal to execute an appropriate data access to an access target, wherein the phase of the clock signal as a reference for operation is inverted and shifted by 180 degrees. wherein a phase converting means for outputting the access target, the phase converting means, phase 180 degrees inversion of the clock signal as a reference of the operation
And a plurality of phase inverting units that output the clock signal from the phase inverting unit.
Multiple clocks that generate and output clock signals with different phases
Click generator and said plurality of different positions input from said plurality of clock generation unit
Selecting one of the phase clock signals and
A phase selector for outputting to the elephant, and controlling the plurality of different phases by controlling the phase selector.
Clock signal is sequentially output to the access target, and the clock signal of each phase is output.
Attempt whether normal data access is possible with lock signal
And, in the phase selection unit based on the trial result
For subsequent data access from multiple phase clock signals
Phase test controller for selecting one clock signal to be used
And a clock phase adjustment circuit. (2) Appropriate data access for the access target
Clock to adjust the phase of the clock signal to perform
In the phase adjustment circuit, Inverts the phase of the clock signal used as the operation reference by 180 degrees
Phase shift output to the access target
Exchange means, A control signal for controlling the access target is transmitted to the access pair.
Control signal output means for outputting to the elephant; The clock signal input from the phase conversion means and
While maintaining the phase difference with the control signal,
The sub-circuit that accesses according to the control signal
And a sub signal for shifting and outputting the control signal and the control signal.
Phase conversion means; Clock phase characterized by comprising
Adjustment circuit. 3. The clock phase adjusting circuit according to claim 2 , wherein the plurality of clock signals having different phases are sequentially accessed by the accessor.
Normal data with the clock signal of each phase
Tries whether access is possible or not, based on the trial result
Data access is subsequently performed from among the plurality of phase clock signals.
Phase test system to select one clock signal used for clock
A sub-multiple clock generator , wherein the sub-phase converter generates and outputs a plurality of clock signals having different phases from the clock signal input from the phase converter. A sub-phase selection unit that selects one of the plurality of different-phase clock signals and outputs the clock signal to the sub-circuit , wherein the phase test control unit controls the sub-phase selection unit. The plurality of clock signals of different phases are sequentially output to the sub-circuit, and it is tried whether or not normal data access is possible with the clock signals of each phase, and based on the result of the trial, the sub-phase selecting unit is used. 3. The clock phase adjusting circuit according to claim 1, wherein one of the plurality of phase clock signals is used to select one clock signal to be used for data access thereafter. 4. A generates a clock signal as a reference timing for accessing the access target, the included in the data in tough ace to input and output data to be accessed on the basis of a clock signal, in order to perform a proper data access In the clock phase adjusting method for adjusting a phase of the clock signal, a phase test instruction step of instructing the access target to execute a phase test, and using the clock signal having a plurality of different phases as the access target in the phase test instruction step. A phase test sequence step of performing data access on a trial basis, and a clock signal having an appropriate phase used in subsequent data access from among the plurality of clock signals having different phases based on the result of the trial in the phase test sequence step Click to select And click signal selection step,
And a clock phase adjusting method. 5. The clock phase adjusting method according to claim 4 , wherein the phase test sequence step selects a clock signal from among the plurality of clock signals having different phases, and the clock signal. A test data writing step of writing predetermined test data to the access target based on the clock signal selected in the selection step; a test data reading step of reading the predetermined test data written to the access target in the test data writing step A test data comparing step of comparing the predetermined test data with the data read in the test data reading step; and a comparison result recording step of recording a comparison result in the test data comparing step. Clock phase adjustment method characterized by, and respectively perform the phase test sequence in different clock signals of the plurality of phases.