JP2850363B2 - PLL video detector - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video detection device used for a television or the like, and particularly to a PLL video detection device compatible with a ghost canceller.

[Conventional technology]

As a video detection circuit of a recent television, a fully synchronous detection circuit using a phase locked loop (hereinafter, PLL) having good linearity is often used, and its performance has been improved.

FIG. 3 is a block diagram of a conventional PLL video detector. In the figure, a video intermediate frequency signal is input from a video intermediate frequency input terminal 1 to a video intermediate frequency amplifier 2 and amplified to a predetermined level. The PLL circuit 3 forms a carrier that is phase-synchronized with the carrier of the video intermediate frequency signal.

The output of the video intermediate frequency amplifier 2 is input to the phase comparator 4. The output of the voltage controlled oscillator (hereinafter, VCO) 5 is input to the phase comparator 4 after being phase shifted by (−45) degrees by the phase shifter 6. The phase comparator 4 compares the phases of the two signals and outputs a signal corresponding to the phase difference to the output terminal 7. VCO5 is a capacitor for determining the free-running oscillation frequency.
It has 16 and 17 coils.

The output terminal 7 is connected to a positive potential side terminal of a reference voltage source 9 via a resistor 8. The negative potential side terminal of the reference voltage source 9 is grounded. The output terminal 7 is connected to one end of a capacitor 11 via a terminal 10 serving as an input terminal of VCO5.
The other end of the capacitor 11 is grounded via a resistor 12.
The capacitor 11 and the resistor 12 constitute a low-pass filter circuit for removing a high-frequency component of the input of the VCO 5.

The output of the VCO 5 is input to the phase shifter 13 as the output of the PLL circuit 3, and is input to the multiplier 14 after being phase-shifted by +45 degrees.
The multiplier 14 multiplies and detects the output of the video intermediate frequency amplifier 2 and the output of the phase shifter 13 and outputs the demodulated signal to the video signal output terminal 15.
Output to

Next, the operation will be described. Since the PLL circuit 3 is configured as described above, the phase difference between the two inputs of the phase comparator 4 is 90 degrees, and the voltage of the output terminal 7 is
When the potential becomes equal to the potential of the positive potential side terminal, the entire circuit enters a stable state. When this voltage is fed back to the VCO 5, a signal having the same frequency as the carrier of the video intermediate frequency signal is generated at the output of the VCO 5. Further, the phase of the output is shifted by (-45) degrees by the phase shifter 6 and set by the PLL circuit 3 so as to have a phase difference of 90 degrees from the video intermediate frequency signal.
This is 45 degrees behind the video intermediate frequency signal. The capacitor 11 and the resistor 12 form a low-pass filter circuit, which removes a high-frequency component of the input of the VCO 5 and suppresses a sudden change in the output of the VCO 5.

The output of VCO 5 is provided to phase shifter 13, where it is phase shifted by 45 degrees, so that the two inputs of multiplier 14 have the same frequency and phase. Therefore, multiplication detection is performed, the video intermediate frequency signal is demodulated, and a demodulated signal is generated at the video output terminal 15.

The above-described PLL circuit 3 operates in the entire period with respect to the input in order to shorten the response time. In addition, since the stability of the video intermediate frequency signal is poor and the lock range of the PLL circuit 3 is desired to be 3 MHz or more, the frequency at which the gain is reduced by 3 dB in the closed loop frequency characteristic is generally reduced by 50%.
It is set to about 100KHz.

By the way, in recent years, there is a movement to improve the signal itself on the broadcasting station side such as EDTV. One of them is to insert a ghost cancellation reference signal, which is a reference for eliminating ghosts, in one horizontal period of the vertical retrace period, and adjust the ghost on the image receiving side to be minimized based on this signal. There is known a technique in which a circuit called a ghost canceller having a function is provided at a subsequent stage of a PLL circuit.

FIG. 4A is a timing chart showing a ghost reference signal. A ghost cancel reference signal GS is inserted during one horizontal period of a pulse sequence of a composite video signal including a vertical synchronizing signal generated during a vertical blanking period. The series of composite video signals are supplied to the video output terminal shown in FIG.
15 is a demodulated signal formed at 15.

FIG. 4 (b) is a timing chart showing a ghost cancellation reference signal affected by a ghost. When a ghost failure occurs, the ghost cancellation reference signal GS
A deformed portion such as a missing portion LP occurs. The ghost canceller connected at the subsequent stage detects the deformed portion such as the missing portion LP and performs adjustment so that the ghost failure is reduced. However, if the frequency response of the PLL circuit 3 is fast, the PLL circuit 3 also responds to a ghost, and the missing part LP
Becomes inaccurate. It is known that the performance of the video detector is very important for the ghost canceller to function sufficiently.

[Problems to be solved by the invention]

Since the conventional PLL video detector is configured as described above, the PLL circuit 3 always operates, and its closed loop frequency characteristic has a relatively fast response characteristic of 50 to 100 KHz. Therefore, the PLL circuit 3 responds to the ghost, and the ghost influence signal appearing in the ghost cancel reference signal GS becomes inaccurate. As a result, even if the ghost canceller is used, the ghost cannot be completely eliminated. There was a point.

If the response in the closed loop frequency characteristic of the PLL circuit 3 is extremely slowed down, the ghost canceller functions sufficiently,
Although the ghost failure is improved, there arises a problem that the whole PLL video detection device becomes unstable with respect to phase fluctuation and frequency fluctuation on the transmission side.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is possible to accurately transmit a predetermined reference signal, for example, a ghost cancel reference signal, to sufficiently perform ghost rejection, and to achieve stable and responsive performance. The objective is to obtain a good PLL video detector.

[Means for solving the problem]

A PLL image detection device according to the present invention eliminates a ghost by a phase locked loop including a phase comparator, a voltage controlled oscillator, and a low-pass filter provided at an input stage of the voltage controlled oscillator and provided with an output of the phase comparator. A PLL video detector that demodulates an input video signal including a reference signal that is a reference signal for a reference signal that is interposed between a phase comparator and a low-pass filter and corresponds to the reference signal A switch circuit that opens an electric path between the phase comparator and the low-pass filter during the period and closes the electric path during a period other than the reference signal period, and the voltage is controlled by the switch circuit and the low-pass filter. A sample-and-hold circuit for the input of the control oscillator is configured.

[Action]

The switch circuit according to the present invention opens an electric path between the phase comparator and the low-pass filter during the reference signal period and closes the electric path during periods other than the reference signal period. The sample and hold circuit is in the hold state, and is in the sample state during periods other than the reference signal period.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a PLL video detector according to an embodiment of the present invention.

Terminal 7 is connected to the base of transistor 18 and the collector of transistor 19. The collector of the transistor 18 is connected to the power supply terminal 20 and the emitter is connected to one end of the resistor 21 and the transistor.
Connected to 22 collectors. The other end of the resistor 21 is connected to the terminal 10.

The base of the transistor 19 is connected to the pulse input terminal 23, and the base of the transistor 22 is connected to the positive potential side terminal of the bias voltage source 24. The negative potential side terminal of the bias voltage source 24 is grounded. Further, the emitters of the transistors 19 and 22 are commonly connected, and are grounded via the resistor 25.

Transistors 18, 19, 22, power supply terminal 20, bias voltage source
The switch 24 and the resistor 25 constitute a switch circuit 26. Also, this switch circuit 26 includes a resistor 21 and a capacitor 11 in the subsequent stage.
A sample and hold circuit is configured together with the resistor 12 and the resistor 12. Other configurations and connection relations are the same as those of the conventional PLL video detector shown in FIG.

Next, the operation will be described. FIG. 2A is a timing chart showing a ghost cancel reference signal GS inserted during the vertical flyback period, and FIG. 2B is a ghost cancel reference signal having a missing portion LP indicating the effect of a ghost fault. 6 is a timing chart showing GS. These signals are formed as demodulated signals at the video output terminal 15 in FIG. FIGS. 2 (a) and 2 (b) correspond to FIGS. 4 (a) and 4 (b), respectively.

FIG. 2 (c) is a timing chart showing the control pulse which goes to "H" level before and after the occurrence of the ghost cancel reference signal GS. Since the position where the ghost cancel reference signal GS occurs in the vertical blanking period is determined in advance, such a pulse can be easily prepared.
The pulse width is equal to the ghost cancel reference signal GS
Is a length corresponding to one horizontal period in which the data is inserted.

The control pulse shown in FIG. 2C is input to the pulse input terminal 23 in FIG. When the control pulse is at the “L” level, the transistor 19 is turned off and the transistors 18 and 22 are turned on. The transistor 22 operates as a constant current source, and the transistor 18 operates as an emitter follower.

The switch circuit 26 becomes conductive, and the sample and hold circuit becomes sampled. The output of terminal 7 is applied via transistor 18 to a lag-lead filter circuit composed of resistor 21, capacitor 11 and resistor 12. The frequency characteristic of the lag-lead filter circuit is configured to substantially match the frequency characteristic of the low-pass filter circuit of FIG. 3 described above, for example, by selecting the resistance value of the resistor 21. Therefore, the control pulse is “L”
In the sample state at the time of the level, the PLL circuit 3 is in the third state.
Like the PLL circuit 3 in the figure, it has a relatively fast response characteristic,
Video detection is performed.

When the control pulse becomes “H” level higher than the potential of the positive potential terminal of the bias voltage source 24, the transistor 19 is turned on,
The transistor 22 is turned off. When the resistance of the resistor 25 is made sufficiently small, the base potential of the transistor 18 drops momentarily, and the transistor 18 becomes non-conductive.

The switch circuit 26 is turned off, and the sample-hold circuit is turned on. The output of the terminal 7 is not supplied to the VCO 5, the constant potential held in the capacitor 11 is supplied to the VCO 5 via the terminal 10, and the output frequency of the VCO 5 becomes constant.

Therefore, in the hold state when the control pulse is at the “H” level, the PLL circuit 3 does not respond to a change in the input frequency. Therefore, the ghost cancel reference signal GS is accurately transmitted to the subsequent ghost canceller without receiving unnecessary deformation, so that the ghost canceller functions sufficiently and the ghost can be sufficiently eliminated.

As described above, the phase comparator 4, the resistor 21, the capacitor 1
A switch circuit 26 is provided between the lag-lead filter circuit and the lag-lead filter circuit that removes high-frequency components of the input of VCO5. Since the open / close state of the switch circuit 26 is controlled so as to be in the hold state in the period corresponding to the reference signal GS and in the sample state in other periods, the ghost cancel reference signal GS can be transmitted accurately and the ghost can be sufficiently eliminated. With stable and responsive performance
A PLL video detector can be obtained.

The same effect can be obtained by using another switch circuit using a MOSFET or the like as the switch circuit 26.

〔The invention's effect〕

As described above, according to the present invention, the switch circuit opens the electric path between the phase comparator and the low-pass filter during the reference signal period, and closes the electric path during the period other than the reference signal period. During the reference signal period, the sample hold circuit is in the hold state, and during periods other than the reference signal period, it is in the sample state.

Therefore, the reference signal, which is a reference signal for removing ghosts, can be accurately transmitted to sufficiently eliminate ghosts, and a PLL with stable and good response performance can be obtained.
An image detector can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL video detector according to an embodiment of the present invention, FIG. 2 is a timing chart showing a ghost cancel reference signal and a control pulse, and FIG. 3 is a block diagram of a conventional PLL video detector. FIG. 4 is a timing chart showing a ghost cancel reference signal. In the figure, 3 is a PLL circuit, 4 is a phase comparator, 5 is a voltage controlled oscillator, 11 is a capacitor, 12 is a resistor, 18, 19, and 22 are transistors, 21 is a resistor, 23 is a pulse input terminal, and 24 is a bias voltage. A source, 25 is a resistor, 26 is a switch circuit, and GS is a ghost cancel reference signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A phase-locked loop including a phase comparator, a voltage-controlled oscillator, and a low-pass filter provided at an input stage of the voltage-controlled oscillator and receiving an output of the phase comparator. A PLL video detector that demodulates an input video signal including a reference signal that is a signal serving as a reference for removing a ghost, being interposed between the phase comparator and the low-pass filter,
In a reference signal period corresponding to the reference signal, open an electrical path between the phase comparator and the low-pass filter,
In a period other than the reference signal period, a switch circuit for closing the electric path is provided, and the switch circuit and the low-pass filter constitute a sample-and-hold circuit for an input of the voltage-controlled oscillator. PLL video detector.