JP2836358B2 - Differential amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit,
In particular, the present invention relates to a differential amplifier circuit composed of MOS transistors.

[0002]

2. Description of the Related Art When a differential amplifier circuit is composed of MOS transistors, the linearity of transconductance poses a problem. As a differential amplifier circuit with improved linearity,
Conventionally, for example, those shown in FIGS. 4, 5, and 6 are known. These are referred to since they are described in detail in the following documents.

FIG. 4: A. Nedungadi and TRViswanathan
“Design of Linear CMOS Transco-nductance Element
s ”IEEE TRANSACTION ON CIRCUITS AND SYSTEMS, VOL, C
AS-31, NO.10, pp.891-894, OCTOBER 1984.

FIG. 5: Zhenhua Wang and Walter Guggenbu
hl “A Voltage-Controllable Line-ar MOS Transconduc
tor Using Bias Offset Technique ”IEEE JOURNAL OF
SOL-ID-STATE CIRCUITS, VOL.25, NO.1, PP.315-317, FEBRU
ARY 1990.

FIG. 6: Francois Krummenacher and Norber
t Joehl “A 4-MHz CMOS Continuo-us-Time Filter wit
h On-Chip Automatic Tuning ”IEEE JOURNAL OF SOLID-
STA-TE CIRCUITS, V0L.23, NO.3 pp.750-758, JUNE 1988.

[0006]

However, in the conventional differential amplifier circuit in which the transconductance linearity is improved, even if the output current value is maximum, the output current value is one-third or one-third of the drive current.
2 or less, the current efficiency is poor (FIGS. 4 and 6), and it is difficult to generate a stable offset voltage (FIG. 5).
In addition, there is a problem that manufacturing tolerance and temperature characteristics are weak as a whole.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a differential amplifier circuit having a novel configuration which has high current efficiency, reduces the influence of manufacturing deviation and temperature characteristics, and can improve the linearity of transconductance.

[0008]

To achieve the above object, a differential amplifier circuit according to the present invention has the following configuration. That is,
A differential amplifier circuit according to the present invention includes: a balanced differential pair including two FETs having equal capacities (ratio of gate width and gate length) and a first constant current source for driving the FETs; A first unbalanced differential pair including two FETs and a second constant current source for driving them; two FETs having a capacity of 1: K and the second constant current source for driving them And a second unbalanced differential pair having a constant current source having the same value as that of the first pair.
The gate of the FET having the capability of the unbalanced differential pair of K and the gate of the FET having the capability of the second unbalanced differential pair of 1, and the other FET of the balanced differential pair and the first unbalanced differential Ability of pair 1
And the capability of the second unbalanced differential pair is K
ET and the gates are connected to each other in common;
The differential output pair is formed by the drains of the other FET of the balanced differential pair, the FET of which the capacity of the first unbalanced differential pair is K, and the FET of which the capacity of the second unbalanced differential pair is 1 And one FET of the balanced differential pair and an FET whose capacity of the first unbalanced differential pair is 1 and an FET whose capacity of the second unbalanced differential pair is K
And the drains are commonly connected to each other.

[0009]

Next, the operation of the differential amplifier circuit of the present invention configured as described above will be described. In the present invention, two unbalanced differential pairs are so-called cross-connected, and the balanced differential pair is connected in reverse, so that even if the current efficiency is set high, the linearity of the transconductance of the differential amplifier circuit can be improved. . At this time, since each FET operates in the saturation region, the temperature characteristics are the same, and therefore the temperature can be easily compensated by the constant current source. Regarding the influence of manufacturing deviation, the threshold voltage, which is most significantly affected because it operates differentially, does not contribute to circuit operation, and the transconductance parameter also operates in a similar manner, so that the manufacturing deviation as a whole Can be unaffected.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a differential amplifier circuit according to one embodiment of the present invention. The same reference numerals are used for the FETs (MOS transistors) as in the related art (FIGS. 4, 5, and 6).
This does not mean that they are the same. Also, the same symbol may be used for the sake of convenience of description, but this does not mean that the content is the same.

This differential amplifier circuit has a capacity (gate width W /
Two transistors (M1, M2) having a gate length L) of M1: M2 = K: 1 and a constant current source I for driving the transistors (M1, M2)
_The (first) unbalanced differential pair with ₀ and the capability is M3:
Two transistors (M3, M4) where M4 = 1: K
And a (second) unbalanced differential pair having a constant current source I ₀ for driving the same and two transistors (M 5, M 6) having the capability of M 5: M 6 = K ′: K ′ and driving the same And a balanced differential pair having a constant current source I ₀ ′.

[0012] Between these three differential pairs, one transistor M5 of the balanced differential pair and the transistor M1 of which the capacity of the first unbalanced differential pair is K and the transistor M5 of the second unbalanced differential pair are used. The gates of the transistor M3 having the capability of 1 and the other transistor M6 of the balanced differential pair and the capability of the transistor M2 and the second unbalanced differential pair having the capability of the first unbalanced differential pair are 1 The gates of the transistor M4 of K are commonly connected to each other to form a differential input pair.

The other transistor M of the balanced differential pair
6 and the drain of transistor M1 having the capability of the first unbalanced differential pair of K and the transistor M3 of the capability of the second unbalanced differential pair being 1 and one transistor M5 of the balanced differential pair having The drains of a transistor M2 whose first unbalanced differential pair has a capacity of 1 and a transistor M4 whose second unbalanced differential pair has a capacity of K are commonly connected to each other to form a differential output pair. ing.

In other words, in two unbalanced differential pairs, the drains of transistors having different capacities are connected in common, as in a so-called crosstalk, whereas in the balanced differential pair, the drains of transistors on opposite sides are connected. (Reverse connection).

In the above configuration, assuming that the device operates in the saturation region, the drain current I _{d1 of} M1 is given by the following equation (1).
Of the drain current I _d2 is the drain current I _d3 of formula 2, M3
Is the expression 3, the drain current _{Id4 of the} M4 is the expression 4, the drain current _{Id5 of the} M5 is the expression 5, and the drain current _{Id6 of the} M6 is the expression 6.

[0016]

I _d1 = Kβ (V _GS1 −V _T ) ²

[0017]

## EQU2 ## I _d2 = β (V _GS2 −V _T ) ²

[0018]

## _EQU3 ## I _d3 = β (V _GS3 −V _T ) ²

[0019]

## EQU4 ## I _d4 = Kβ (V _GS4 −V _T ) ²

[0020]

I _d5 = K′β (V _GS5 −V _T ) ²

[0021]

[6] _{I d6 = K'β (V GS6 -V} T) 2

Here, V _T is a threshold voltage, V
_GSi is a gate-source voltage. Β is a transconductance parameter of the transistor, and can be expressed by Expression 7 using mobility μ, gate oxide film capacitance C _OX per unit area, gate width W, and gate length L.

[0023]

## EQU7 ## β = μC _OX (W / L) (1/2)

The constant current source I ₀ is given by equation (8), the constant current source I ₀ ′ is given by equation (9), and the difference between the gate and source voltages between the transistors of each differential pair is equal to equation (10).

[0025]

## _EQU8 ## I ₀ = I _d1 + I _d2 = I _d3 + I _d4

[0026]

## _EQU9 ## I ₀ ′ = I _d5 + I _d6

[0027]

[Number 10] _{V GS1 -V GS2 = V GS3 -V} GS4 = V GS5 -V GS6

Accordingly, from Equations (1) and (10), the difference current ΔI ₁ of the drain current in the first unbalanced differential pair is given by Equation (11).
The difference current ΔI ₂ of the drain current in the _second unbalanced differential pair is expressed by the following equation (12), and the difference current of the drain current in the balanced differential pair is ΔI
₃ is obtained by Expression 13. Note that in Equation 13,
K ′ is expressed by Expression 14, and I ₀ ′ is expressed by Expression 15.

[0029]

[Equation 11]

[0030]

(Equation 12)

[0031]

(Equation 13)

[0032]

[Equation 14]

[0033]

(Equation 15)

[0034] Now, the difference current ΔI of the differential output current of the differential amplifier circuit, the drain of the transistor of the balanced differential pair is called reverse connection, although the equation 16, inputs the voltage V _IN Is the transconductance of the differential amplifier circuit (Equation 17).

[0035]

ΔI = ΔI ₁ + ΔI ₂ −ΔI ₃

[0036]

[Equation 17]

Here, the balanced differential pair aims at improving the linearity of the transconductance of the differential amplifier circuit.
Let us consider parameters a and b that satisfy

[0038]

K ″ · I ₀ ″ = a ² · K ′ · I ₀ ′

[0039]

K ′ / I ₀ ″ = b · K ′ / I ₀ ′

When, for example, K = 4 and K = 2, Equations 11 to 13 for each value of a and b are differentiated by the input voltage V _IN to obtain the value of transconductance according to Equation 17. FIG. 2 (K = 4) and FIG. 3 (K = 2)
Becomes 2 and 3, when a = 0 and b = 0, there is a transconductance without a balanced differential pair. Show the contribution of the differential pair.

There is a great improvement effect, and when the input voltage range is in the range shown by Expression 20,

[0042]

数 (I ₀ / (Kβ)) ≧ │V _IN │

That is, although the horizontal axis is normalized, it is almost -1.
It can be understood that the transconductance is substantially constant in the range of / √K to + 1 / √K.

Next, from equations (18) and (19), K ″ is obtained as equation (21), and I ₀ ″ is obtained as equation (22). Therefore, the capacity (W / L) of the transistor of the balanced differential pair and the constant current source are independent. Can be set. Therefore, even when the current efficiency is set higher than the conventional one, the transconductance of the differential amplifier circuit can be improved. 2 and 3 illustrate this.

[0045]

(Equation 21)

[0046]

(Equation 22)

In the differential amplifier circuit, since each transistor operates in the saturation region, the temperature characteristics are the same, and therefore, the temperature can be easily compensated by the constant current source. With respect to the influence of the manufacturing deviation, the threshold voltage _VT is most affected and the transconductance parameter β is also affected.However, since the differential operation is performed, the threshold voltage _VT is canceled out and does not contribute to the circuit operation. Since the characteristics of the transconductance parameter move in a similar manner, the transconductance parameter can be totally unaffected by the manufacturing deviation.

[0048]

As described above, according to the differential amplifying circuit of the present invention, two unbalanced differential pairs are so-called crossed, and a balanced differential pair is connected in reverse, so that the current efficiency can be improved. Even if it is set high, the linearity of the transconductance of the differential amplifier circuit can be improved. At this time, since each FET operates in the saturation region, the temperature characteristics are the same, and therefore the temperature can be easily compensated by the constant current source. Regarding the influence of manufacturing deviation, the threshold voltage, which is most significantly affected because it operates differentially, does not contribute to circuit operation, and the transconductance parameter also operates in a similar manner, so that the manufacturing deviation as a whole There are effects such as not being affected.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit according to one embodiment of the present invention.

FIG. 2 is a transconductance characteristic diagram (K = 4) of the differential amplifier circuit of the present invention.

FIG. 3 is a transconductance characteristic diagram (K = 2) of the differential amplifier circuit of the present invention.

FIG. 4 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 5 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 6 is a circuit diagram of a conventional differential amplifier circuit.

[Explanation of symbols]

M1 to M6 MOS transistors I ₀ constant current source I ₀ ′ constant current source V _IN input voltage K capability (gate width / gate length) K ′ capability (gate width / gate length)

Claims (1)

(57) [Claims] 1. A balanced differential pair comprising two FETs having the same capacity (ratio of gate width to gate length) and a first constant current source for driving the two FETs; and two FEs having a capacity of 1: K.
A first unbalanced differential pair comprising T and a second constant current source for driving them; two FETs having a capacity of 1: K; the second constant current source for driving them; A second unbalanced differential pair having an equal constant current source; and a differential input pair, wherein the FET of one of the balanced differential pair and the first unbalanced differential pair have a capacity of K. And the second unbalanced differential pair has a gate of one FET, and the other FET of the balanced differential pair and the FE of the first unbalanced differential pair have one performance
T and the gate of the FET of which the capacity of the second unbalanced differential pair is K are commonly connected to each other; and the differential output pair is formed by connecting the other FET of the balanced differential pair with the first unbalanced FET. The FET whose differential pair has a capacity of K and the second unbalanced differential pair have a capacity of 1
And the other FET of the balanced differential pair, the FET of which the capacity of the first unbalanced differential pair is 1, and the FET of which the capacity of the second unbalanced differential pair is K. A differential amplifier circuit having drains commonly connected to each other;