JP2834298B2 - Data processing device and data processing method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to high-speed processing of a computer, and more particularly to variable-structure data that changes the execution method of a program in response to the parallelism inherent in the program. The present invention relates to a processing device and a data processing method.

[Conventional technology]

In general, there are two types of configuration methods for a data processing device having a plurality of processor elements, each of which executes instructions in parallel. The first configuration method is a multiprocessor type computer system, and the second configuration method is a superscalar type computer system.

In a multiprocessor type computer system, a plurality of processor elements operate by sharing a memory device or a cache storage device. A program counter that indicates a program execution position is provided inside the processor element, and each processor element fetches an instruction from a position indicated by the program counter and executes the instruction. That is, each processor element independently executes a separate program.

Also in the superscalar computer system, a plurality (n) of processor elements operate by sharing a cache storage device and a register. However, the operation of each processor element is to execute a plurality of instructions existing in one program synchronously and in parallel. In the superscalar computer system, all registers including the program counter are shared, n instructions are extracted from the position pointed to by the program counter, and each instruction is executed by each processor element. One type of superscalar computer system is a VLIW (ultra-long instruction) computer system. The VLIW type computer system is a computer capable of performing a plurality of operations and controls by one instruction, and distributes and executes these operations and controls to each processor element.

The data processing devices of both the multiprocessor type computer system and the superscalar type computer system are high-speed technologies conventionally applied to various fields. Here, the following three types of documents are shown as examples of both the computer system and the VLIW type computer system.

1) Multiprocessor S. Thakkar et.al .: “The Balance Multiprocessor Syst
em, "IEEE MICRO, 1989, 2, pp. 57-69.2) Superscalar K. Murakami et.al .:" SIMP (Single Instruction strea)
m / Multiple instruction Pipelining): A Novel High-
Speed Single-Processor Architecture, "Proc.16th In
ternational Symposium on Computer Architecture, 198
9, pp. 78-85. 3) VLIW H. Hagiwara et.al .: “A Dynamically Microprogrammabl
e Computer with Low-Level Parallelism, "IEEE Tran
sC-29, No. 7, 1980, pp. 577-595. [Problem to be Solved by the Invention] In the superscalar computer system described above,
Since it is necessary to execute n instructions (n operations in a VLIW type computer system) synchronously and in parallel, it is important to minimize the communication delay between each processor element. Therefore, each processor element must be arranged on one LSI chip or one board. With recent advances in VLSI technology,
LSI chips can be made in units of 0.5 μm (micron), 0.3 μm, and even 0.1 μm, and the above requirement for communication delay is being satisfied.

However, even if hardware for executing instructions in parallel in a synchronized manner with n processor elements is provided, if parallelism cannot be found in the program to be executed, a limited number of realized hardware is required. It becomes a state in which only the specified part can be used. As an extreme example, if a program without parallelism is executed between consecutive instructions, only one processor element that actually operates exists among the n processor elements, and the remaining (n) -1) The processor elements are wasted. Assuming that there are n such programs and the execution time of each program is Si (i is 1 to n) seconds, the execution time of all programs is ΣSi (Σ represents full addition). When such a program is executed in a multiprocessor type computer system, it can be executed very effectively. If there is no problem even if the execution order of each program is changed (this is a common assumption such as a program of n different users), n processor elements are used to independently execute each program. The program can be executed. At this time,
Ideally, all programs can be terminated with the maximum value of the execution time Si of each program. Actually, the execution time is increased due to competition between the processor elements of the cache storage device and the memory device, but it is still very advantageous as compared with the superscalar computer system.

Contrary to this example, there is a possibility that the multiprocessor type computer system is disadvantageous. As an example, there is a case where the environment is not an environment where a plurality of programs are executed simultaneously, or a case where the number of processor elements is larger than the number of programs. That is, in a multi-processor computer system, only the degree of parallelism can be realized by the number of existing programs. Therefore, when the number of programs is p-type, if the number of processor elements (n) is larger than the number of programs, ( np) processor elements are wasted. In a superscalar computer system, parallelism can be found even in one program, so that processor elements are often not wasted even when the number of programs is small.

A first object of the present invention is to complement the above-mentioned problems of the superscalar computer system and the multiprocessor computer system. Specifically, data processing depends on the degree of parallelism of a program. Set the operation mode of the device to one of the superscalar computer system and the multiprocessor computer system (the operation of the superscalar computer system is referred to as “parallel operation”, and the operation of the multiprocessor computer system is referred to as “multiprocessor processor”). The operation is called “operation”.

A second object of the present invention is to enable the VLSI design technology used for realizing the parallel operation to be effectively used also in the multiprocessor operation. As described at the beginning of this section, in order to realize parallel operation (superscalar computer system), it is necessary to arrange each processor element on the same LSI chip or on the same board. Such an arrangement of the processor elements is not particularly required in a normal multiprocessor operation (multiprocessor computer system). However, in the present invention, considering the case where a plurality of programs operate in cooperation with each other, the fact that "processor elements are arranged close to each other for parallel operation" It is intended to make effective use in the setting operation. Specifically, a second object is to provide means for performing high-speed synchronization and communication between a plurality of programs.

[Means for solving the problem]

The first object is achieved by the following three types of means.

1) a multi-processor operating mechanism for independently operating n processor elements; 2) a parallel operating mechanism for operating n processor elements in synchronization with a basic clock; and, if necessary, 3) the present invention. A parallelization flag indicating whether the data processing device is executing in a parallel operation or in a multiprocessor operation; the parallel operation mechanism is provided in each processor element.

The second object is achieved by the following three means.

a) a communication bus for transmitting and receiving data, addresses, control signals, and the like between the processor elements; b) a bus arbitration circuit for managing the communication bus; c) a synchronization facility for synchronizing between the processor elements; The above three types of means are components of the multiprocessor operating mechanism.

[Action]

The multi-processor operating mechanism allows the n processor elements to operate independently in the data processing device of the present invention. Also, the present invention provides a means for synchronizing and communicating with the programs running in each processor element at high speed.

The parallel operating mechanism synchronizes the n processor elements. In parallel operation, registers are shared between the processor elements. For this reason, when a register is referred to at the time of instruction execution, it is determined whether or not the parallel operation mechanism in each processor element is a register in the own processor element, and if it is a register in the own processor element, The contents of the register are sent to the processor element that has executed the instruction.

The parallelization flag specifies whether the data processing device of the present invention is being executed in a multiprocessor operation or is being executed in a parallel operation. When the parallelization flag specifies a multiprocessor operation, the operation of the parallel operation mechanism is suppressed.
If the parallelization flag specifies parallel operation, the operation of the multiprocessor operation mechanism is suppressed.

The communication bus is used when a processor element cooperates and executes a program at the time of multiprocessor operation, and performs data transfer and the like.

The bus management device manages the right to use the communication bus, and grants the right to use the communication bus according to the priority of the processor element when each processor element performs data transfer or the like using the communication bus. I do.

When data transfer and synchronization are performed between the processor elements, the synchronization facility holds the transferred data, and stops and restarts the processor elements.

〔Example〕

 An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an overall configuration diagram of a data processing device according to the present invention. A2 and A3 are processor elements, which execute operations based on instructions and data read from a cache storage device or a memory device. FIG. 1 shows a case where the number of processor elements is two, but the number of processor elements in the present invention is not limited. However, in the present embodiment, description will be made below assuming that the number of processor elements is two. A4 is a memory device that stores programs, data, and the like. A5 is a cache storage device for temporarily storing commands and data read from the memory device. Assume that the cache store is a multi-port cache. That is, assuming that the number of processor elements is n, a cache having at least n input / output ports, or n input ports and n output ports, and further having n address input ports. It is a storage device. A11 is the basic clock,
Processor elements A2, A3, multi-processor operation mechanism
Used as A8 clock.

The n processor elements have two modes: a multi-processor operation in which each processor element operates independently, and a parallel operation in which each processor element operates in synchronization with a basic clock. Multiprocessor operation mechanism as a mechanism for controlling two operation modes
It is equipped with two types of control mechanisms, A8 and parallel operation mechanisms A9 and A10. Of these, the parallel operation mechanisms A9 and A10 synchronize the n processor elements and share registers between the processor elements. At this time, a check for register conflict is performed between instructions executed by each processor element. When a conflict occurs, the execution of the instruction of one processor element is delayed to eliminate the register conflict. Note that hardware that does not check for and eliminate register conflicts may be considered.
A1 does not operate as a superscalar processor, but as a VLIW processor.

Further, a parallel flag A7 is prepared to indicate whether the data processing device is executing in the multiprocessor operation mode or in the parallel operation mode. When the parallelization flag A7 indicates the multiprocessor operation mode, the operation of the parallel operation mechanisms A9 and A10 in each processor element is suppressed, and when the parallel operation mode indicates the parallel processor mode, the multiprocessor operation mechanism
A8 suppresses its own movement.

The setting of the parallelization flag A7 is based on a privileged instruction that can be executed only by the OS. However, an external input can be used instead of the parallelization flag A7.

A6 is a cache control device, which changes the read / write data width and the number of data of the cache storage device A5 according to the value of the parallelization flag A7. Parallelization flag A7
Indicates the multiprocessor operation mode, the n processor elements asynchronously read / read instructions and data.
Write. Therefore, assuming that the read / write bit width of one processor element is k, the cache storage device A5
Is set to n address input, k bits and n input / output. When the parallelization flag A7 indicates the parallel operation mode, the n processor elements read / write instructions and data in synchronization. In this case, the instruction is read with one address input and n × k bits / one output, but the reading and writing of data is the same as in the multiprocessor operation mode.

Processor elements A2, A3 (including parallel operation mechanisms A9, A10), cache storage device A5, cache control device A6,
The processor A1 is a combination of the parallelization flag A7, the multiprocessor operation mechanism A8, and the basic clock A11. Although it is possible to provide each of the above functional parts of the processor A1 on a different board, in the present embodiment, it is assumed that the entire processor A1 is mounted on one chip LSI or one board. In FIG. 1, the processor A1 is connected one-to-one with the memory device A4, but a shared memory type multi-processor in which a plurality of processors are connected to the memory device A4 via a communication bus, a network, or the like. A processor configuration is also possible.

a1 to a9 are signal lines representing data lines, address lines, control lines, and the like. a1 is an output line of the parallelization flag A7, which outputs 1-bit information indicating whether the operation mode is the multiprocessor operation mode or the parallel operation mode, by the cache control device A
6. The information is transmitted to the multiprocessor operating mechanism A8 and the parallel operating mechanisms A9 and A10. a2 and a3 indicate data lines used to transfer data or instructions between the processor elements A2 and A3 and the cache storage device A5. a2 and a3 have a reference width of 32 to 128 bits. a4 and a5 are address lines for specifying addresses of data and instructions. Cache control device A6
Transmits the address signals a4 and a5 of each processor element to the cache memory A5 according to the operation mode indicated by the parallelization flag A7. a6 and a7 are signal lines connecting the multiprocessor operation mechanism A8 and the processor elements A2 and A3, and are used in the multiprocessor operation mode. a6 and a7 have an address line, a data line, and a control line, respectively. a8 is an output signal of the basic clock A11, and transmits a clock signal to the processor elements A2, A3 and the multiprocessor operating mechanism A8. a9 generally indicates data lines and control lines for performing communication between multiprocessor operation mechanisms in a multiprocessor system equipped with a plurality of processors A1.

FIG. 2 shows an overall configuration diagram when the cache storage device A5 is divided into an instruction cache and a data cache in the present invention. A1 to A4, A6 to A11 and a1 and
Reference numerals a4 to a9 denote the same mechanisms and signal lines as those in FIG. B1 is an instruction cache, and B2 is a data cache, which is a cache storage device that individually stores instructions and data. B3 is a selector, and when performing block transfer between the cache storage device and the memory device, if the transfer target is an instruction, the instruction cache B1 is connected to the memory device A4, and if the transfer target is data, , Data Cache
Connect B2 to memory device A4.

b1 and b2 and b3 and b4 are data lines, which are used for instruction transfer and data transfer between the instruction cache B1 and the data cache B2 and the processor elements A2 and A3, respectively. Instruction cache B from processor elements A2 and A3
Since writing to 1 cannot occur, the instruction cache B1
The operation of the data lines b1 and b2 is only in the output mode.

It is assumed that the instruction cache B1 and the data cache B2 are both multiport caches and have n address input ports and n input / output ports (the instruction cache B1 has only output ports). By using a multiport cache as the data cache, data reading and writing are independently performed by n processor elements in each of the multiprocessor operation mode and the parallel operation mode.
Therefore, n address inputs to the data cache B2 use the address lines from each processor element as they are. Instruction reading is performed independently by each processor element during multiprocessor operation, and during parallel operation, each processor element fetches and executes consecutive n instructions. For this reason, when the parallelization flag A7 indicates the multiprocessor operation mode, the address lines of the n processor elements are directly input to the instruction cache B1 as they are. Only the address lines of the th processor element are used. The configuration of the cache control device A6 for performing such control will be described with reference to FIG. 4 and subsequent drawings.

FIG. 3 shows processor elements A2 and A3 (parallel operation mechanism A
9, A10). It is assumed that each processor element itself is a superscalar processor capable of executing two instructions in parallel. That is, during multiprocessor operation, each processor independently executes two instructions in parallel, and during parallel operation, the four instructions are synchronized with the basic clock.
Execute instructions in parallel. In the figure, A1 to A4, A6 to A8, A11
And a1, a4 to a9 show the same mechanism and signal lines as those in FIG. B1 to B3 and b1 to b4 are the same mechanism and signal lines as those in FIG.

D1 to D4 are instruction registers, which temporarily hold the instruction read from the instruction cache B1. D5 to D8 are decoders for decoding instructions stored in the instruction register. D9 and D10 are selectors for performing different controls on the decoder during the multiprocessor operation and the parallel operation. D11 to D14 are arithmetic units, and D15 and D16 are register files shared by two arithmetic units. D17 is a gate for transferring the value of the register between the processor elements.

d1 and d2 are read buses d3 and d3 for referring to register values.
d4 is a store bus for storing data in the register. In addition, a global read bus d5 and a global store bus d6 are provided to refer to register values between processor elements during parallel operation. d7 to d10 are signal lines for controlling the decoders D5 to D8. In the figure, selectors D9 and D10, gate D17, and signal lines d5 to d10 constitute parallel operation mechanisms A9 and A10.

The processor elements A2 and A3 execute two instructions in parallel, though there is a difference that they are independent during the multiprocessor operation and synchronized with the basic clock during the parallel operation. Therefore, assuming that the bit length of the instruction is k, the signal lines b1 and b2 connecting the instruction cache B1 and the instruction registers D1 to D4 require a data width of 2 × k bits (two instructions). In each case, k bits are sent to the instruction registers D1 to D4. Here, first, an operation in the case where the first processor element A2 executes two instructions in parallel will be described. The instructions held in the first and second instruction registers D1 and D2 are the first and second decoders D and D2, respectively.
Decoded by 5, D6. Arithmetic unit D1 according to decoded instruction
1, D12 and the register file D15 are controlled. The contents of the register specified by the operand of each instruction are read from the first register file D15 via the read bus d1, and the operation specified by the operation code of each instruction is performed by the first and second operations. It is executed in parallel using the arithmetic units D11 and D12. The operation result is stored in the register file D15 via the store bus d3. Similarly, the second processor element A3 executes two instructions in parallel.

However, among a plurality of instructions fetched simultaneously by the processor elements A2 and A3, there are combinations of instructions that cannot be executed in parallel. First instruction and second
This corresponds to a case where a register conflict occurs with the second instruction. When the destination register of the first instruction (the register for storing the operation result of the instruction) is specified as the source register of the second instruction (the register having a value to be referred to in the instruction), Two instructions cannot be executed in parallel. That is, the first instruction must be executed and the execution of the second instruction must be delayed until a result is obtained. The parallel operation mechanism A9, A10,
It has a role of resolving such register conflicts and a role of register sharing between processor elements. Note that the present invention assumes that parallel processing in the processor elements A2 and A3 performs a superscalar operation, so that it is necessary to eliminate register conflicts for the purpose of maintaining compatibility with the conventional processor. ing. However, if the processor elements A2 and A3 perform parallel processing as VLIW processors, it is not necessary to eliminate register conflicts. In this case, an instruction sequence must be generated by the compiler so that register conflicts cannot occur.

First, a method of resolving register conflicts by the parallel operation mechanisms A9 and A10 will be described. The first instruction (instruction register D1
) Are originally the instructions to be executed first, so that there is no influence from other instructions to be executed in parallel. However, the second instruction (the instruction held in the instruction register D2) is an instruction that should be executed next to the first instruction, so that
If the destination register of the first instruction is specified as the source register of the second instruction, the second instruction cannot refer to the correct value of the source register unless the second instruction is executed after the execution of the first instruction. Erroneous calculation may be performed. Therefore, the decoder D5 sends the destination register number of the first instruction to the decoder D6 via the signal line d8.
Pass to. In the decoder D6, a comparison is made between the source register number of the second instruction and the destination register number of the received first instruction. As a result, if they match, the decoder D6 suppresses its own instruction decoding operation,
After the operation indicated by the first instruction is executed by the arithmetic unit D11, the second
Controls execution of instructions.

The same operation is performed in the second processor element A3, but the operation differs between the multiprocessor operation and the parallel operation. At the time of the multiprocessor operation, since the processor elements operate independently of each other, the processor element A3 is not affected by the processor element A2. Therefore, the third instruction (instruction register D3
), No register conflict can occur. Further, in the fourth instruction (the instruction held in the instruction register D4), it is only necessary to resolve the register conflict between the destination register of the third instruction and the source register of the fourth instruction. At the time of the parallel operation, the processor element A3 executes instructions in parallel with the processor element A2, and thus is affected by the first instruction and the second instruction being executed by the processor element A2. That is, the third instruction resolves the conflict between the destination register of the first instruction and the second instruction and the source register of the own instruction.
The instruction must resolve the conflict between the destination registers of the first to third instructions and the source register of the instruction. Therefore, for the third instruction, the destination register numbers of the first instruction and the second instruction are passed through signal lines d7 and d9, and the source register number of the third instruction received at the decoder D7 is received. A comparison is made between the destination register numbers of the first instruction and the second instruction. If it is determined that there is no conflict, the operation of the third instruction is immediately executed using the arithmetic unit D13. On the other hand, if it is determined that there is a conflict, the decoder D7 suppresses its own instruction decoding operation at least until the second instruction completes the operation using the arithmetic unit D12. For the fourth instruction, the destination register numbers of the first to third instructions are sent via signal lines d7 and d10. In the decoder D8, a comparison is made between the source register number of the fourth instruction and the destination register numbers of the received first to third instructions. If it is determined that there is no conflict, the operation of the fourth instruction is immediately executed using the arithmetic unit D14. Conversely, if it is determined that there is a conflict, the decoder D8 suppresses its own instruction decoding operation at least until the third instruction completes the operation using the arithmetic unit D13. When the execution of the n-th instruction is suppressed due to the register conflict, the execution of the (n + 1) -th instruction is also suppressed.

It is necessary to change the control of the operations of the decoders D7 and D8 in the processor element A3 by the multiprocessor operation and the parallel operation as described above. This is the selector D9, D
Performed by 10. Selector D9, D10 is parallel flag A7
The signal is transmitted by the signal line a1 indicating the value of, and sends a 0 signal (does not suppress the instruction decoding operation) to the decoder D7 and the destination register number of the third instruction to the decoder D8 during the multiprocessor operation. In the parallel operation, the destination register numbers of the first and second instructions are passed to the decoder D7, and the destination register numbers of the first to third instructions are passed to the decoder D8.

Next, register sharing, which is another role of the parallel operation mechanisms A9 and A10, will be described. Register sharing is performed by the gate D17 and the signal lines d5 and d6 among the parallel operation mechanisms A9 and A10. Since each processor element operates independently during the multiprocessor operation, even if the register numbers match, the values of physically different registers are referred to. That is, the register of the register file D15 is used when the processing is executed by the processor element A2, and the register of the register file D16 is used when the processing is executed by the processor element A3. This is the read bus d1,
This can be achieved by performing read / write using d2 and the store buses d3 and d4, respectively. However, when each processor element specifies the same register number during the parallel operation, the same register is referred to completely. Therefore, it is necessary to change the register to be read and the register to be written according to the two operation modes. In the present invention, in order to solve this problem, the number of output ports and the number of input ports of the register file D15 are set to twice the number of ports of the register file D16, and the values of the registers in the register file D15 are transmitted and received with other processor elements. A global read bus d5 and a glow bus store bus d6. If the number of processor elements is n, the number of ports in the register file D15 is n times the number of ports in the register file in another processor element. Such a register file configuration has a drawback as the number of processor elements increases, but the VLSI
It can be realized in the future as the scale of the system increases.

During multiprocessor operation, each processor element independently refers to a register file. The registers necessary for the parallel execution of the two instructions are read using the read buses d1 and d2, and the operation result is written into the registers using the store buses d3 and d4. The read buses d1, d2 and the store buses d3, d4 are used only in each processor element, and do not affect other processor elements.

In the parallel operation, the processor element A3 refers to the register file D15 using the global read bus d5 and the global store bus d6, and does not use the register file D16. Such control of register sharing is performed by opening and closing the gate D17 existing on the global read bus d5 and the global store bus d6 by the signal a1 from the parallelization flag A7. In addition, of the contents of the register read from the register file D15,
Data used in the processor element A2 is transmitted to the arithmetic unit D11 or the arithmetic unit D12 via the read bus d1. The writing of the operation result by the operation unit D11 or the operation unit D12 is also performed via the store bus d6, and no communication is performed with another processor element.

As described above, the processor elements A2 and A3 and the parallel operation mechanisms A9 and A10, which are the components thereof, have been described. Next, a cache control device for changing the read number and read width of the instruction cache B1 by multiprocessor operation and parallel operation.
A6 is shown.

Instruction reading is performed independently by each processor element during multiprocessor operation, and during parallel operation, each processor element fetches and executes consecutive n instructions. For this reason, when the parallelization flag A7 indicates the multiprocessor operation mode, the instruction cache B1 is connected to the address lines of the n processor elements as they are.
, And to indicate parallel operation, use only the address line of the first processor element,
The value of the address line and the value are respectively 1 to (n-1)
It is necessary to use the value increased by the instruction length as the address input of the instruction cache B1.

FIG. 4 shows the simplest configuration of the cache control device A6 for controlling such a cache storage device. The address lines a4 and a5 of each processor element are directly input to the data cache B2. E1 is an adder which outputs a signal which is increased by one instruction length from the value of the address line of the first processor element A2 to the address line e1. E2 is a selector, and the parallelization flag A7
Indicates the multi-processor operation mode, selects the address line a5 from the second processor element A3, and selects the address line e1 in the parallel operation mode. Thus, in the multiprocessor operation mode, each processor element independently inputs an address of an instruction. In a parallel operation, n consecutive instructions are read from the value of the address line of the first processor element A2. It can be specified.

Note that, in addition to the configuration shown in FIG.
Out of the n output ports, one of which is an n × m × k bit output port (k is the bit length of the instruction, m
Is the number of instructions that each processor element retrieves at the same time).
This configuration is shown in FIG. 5 (n = m = 2). F1 is a selector, which is controlled by the output signal a1 of the parallelization flag A7. f1 indicates a data line from the first output port, and f2 indicates a data line from the second output port. In this case, the address lines a4 and a5 from each processor element are used as the address input of the instruction cache B1. The output port f1 has a bit width n times that of the other output port f2. this house
The mxk bit is the processor element A2 via signal line b1.
, But the remainder becomes the input of the selector F4 via the signal line f4. At the time of multiprocessor operation, m × k bits are fetched from each output port as an instruction to be executed. At this time, of the output from the first output port, the remaining (n-1) × m × k bits are not used. In parallel operation, n × m continuous instructions (n × m × k bits) taken out from the output port of the first processor element are distributed to each processor element. At this time, the remaining (n-1) outputs are not used. Processor element A3 is connected to signal line f2 or
Which instruction sequence of f3 should be executed depends on the parallelization flag A7
This is performed by controlling the selector F1 according to the output signal a1. At the time of multiprocessor operation, the signal line f2
During the parallel operation, the signal line f3 is selected.

Next, an embodiment in which the data processing device of the present invention is used in a multiprocessor operation mode will be described.

FIG. 6 shows the function of the multiprocessor operation mechanism. The multiprocessor operating mechanism is a communication device between the processor elements necessary for the data processing device of the present invention to operate as a multiprocessor.

As a function to interrupt between processor elements,
There are three types: a function that generates an interrupt by specifying the other processor element number, a function that distributes an interrupt to all processor elements (ALL), and an interrupt that any one processor element can accept (ANYONE). Exists.

For control instructions, instructions for transferring register values between processor elements to execute parallel processing in detail, a stop instruction (WAIT) that waits until a start signal from another processor element arrives, There is a restart instruction (START) to cancel this.

As exclusive control, there is an instruction to execute Test & Set or Compare & Swap for a specific address of the memory device. The Compare & Swap instruction is an instruction for reading data from a memory device, determining the value of the read data, and writing the data to the memory device according to the result. During this series of processing, it is necessary to prevent other processor elements from performing Compare & Swap for the same address. For this reason, each processor element is a Compare & S
Before executing the wap instruction, a request to execute the Compare & Swap instruction is issued to the multiprocessor operating mechanism. After the execution request is granted, the operation of the Compare & Swap instruction is performed,
Thereafter, control is performed so as to withdraw the request. The multi-processor operation mechanism gives execution rights to only one processor element if there is a request from a plurality of processor elements and if the request is for the same address, and issues a request for a different address. If so, the execution right is given to each processor element.

FIG. 7 shows an internal configuration diagram of the multiprocessor operating mechanism A8 for performing the above Compare & Swap instruction control.

In the figure, g1 and g2 are Compare & Sw for each processor element.
Address line used when executing ap instruction, g3 and g4 are Compa
Signal lines to indicate the end of re & Swap instruction execution, g5 and g6 are C
This is a signal line for indicating the start of execution of the ompare & Swap instruction. g7 and g8 are signal lines for notifying the execution right of Execute of the Compare & Swap instruction from the multiprocessor operation mechanism A8 to the processor elements A2 and A3, which are executable when "ON" and executable when "OFF". Indicates impossibility. The signal lines g1 to g8 constitute the signal lines a6 and a7 in FIG. The multiprocessor operation mechanism A8 uses the output signal a1 of the parallelization flag A7 as an input.

G1 is a buffer register that holds the address of the currently executing Compare & Swap instruction, and G2 is the currently executing Compare & Swap instruction.
This is a counter indicating the number of wap instructions. G3 to G5 are arithmetic units for performing addition and subtraction. G6 to G8 are comparators,
Compares the address of the Compare & Swap instruction and the value of the counter G2. G9 and G10 are compared based on the value of the parallelization flag.
G9 and G10 are selectors for changing the values of the signal lines g7 and g8 according to the value of the parallelization flag, and G11 is a selector for selecting an address to be input to the buffer.

Next, an operation example of the above hardware will be described. The address lines g1 and g2 from the two processor elements A2 and A3 are both compared with the contents of the buffer by the comparators G6 and G7. If there is a matching address, "ON";
F ”is output to the signal lines g9 and g10. Further, the value of the counter G2 is always compared with 0 by the comparator G8, and the negation thereof becomes the signal line g11. That is, the signal line g11 is "ON" when the value of the counter G2 is not 0 (the address stored in the buffer G1 exists), and is "OFF" when the value of the counter G2 is 0. At this time, by taking the logical product of the signal lines g5, g9, and g11, the first processor element
When A2 executes the Compare & Swap instruction, it can be shown that the same address exists in the buffer G1. Also, by taking the logical product of the signal lines g6, g9, and g11, the second
When the processor element executes the Compare & Swap instruction, it can indicate that the same address exists in the buffer G1. If these signals are negated by signal lines g12 and g13, respectively, this means that the same address does not exist in the buffer G1, that is, a permission signal that can execute the Compare & Swap instruction. However, this is a comparison with the address of the Compare & Swap instruction that is already being executed.
& Conflict with Swap instruction must be resolved.

As an embodiment, FIG. 7 shows hardware that always gives priority to the first processor element A2. Accordingly, the enable signal g12 of the first processor element A2 is transmitted as it is via the selector G9 as the signal g7. However, the second processor element A3 is transmitted as the signal g8 via the selector G10 on condition that no competition occurs with the permission signal g12 of the first processor element A2. The fact that the two permission signals g12 and g13 do not compete with each other can be obtained by taking the negative g14 of the logical product of the signals g12 and g13.
Accordingly, the true enable signal g15 of the second processor element A3 is the logical product of the signals g13 and g14. This is the input of the selector G10.

The selectors g9 and g10 select the permission signals g12 and g15 when the parallelization flag A7 indicates a multiprocessor operation,
When the parallel operation is indicated, the multiprocessor operation mechanism is unnecessary, so that the value of the parallelization flag A7 itself is always set to be returned.

The selection for storing the address to the buffer G1 is performed by the selector G11. An address line to be supplied to the buffer G1 is selected depending on which processor element is given execution right. When the execution right is given, the value of the counter G2 is increased by the arithmetic unit G3. The operation unit G3 is controlled by the permission signals of the two processor elements.
This is performed by the logical sum g16 of g12 and g15. When the execution of the Compare & Swap instruction is completed, the end signal g3 or g4 is passed, whereby the counter G2 is calculated using the arithmetic units G4 and G5.
Decrease. The control of the arithmetic units G4 and G5 is performed by ending signals g3 and g4,
This is performed by the logical products g17 and g18 with the output signals g9 and g10 of the comparators G6 and G7 indicating that the specified address exists in the buffer G1.

Here, the buffer G1 may overflow, but when the execution of the Compare & Swap instruction is completed, the address is immediately deleted from the buffer G1, so that there is no problem if a sufficiently large buffer G1 is prepared. in this way,
The multiprocessor operation mechanism of the present invention is characterized in that execution rights are given to a plurality of basically, if a Compare & Swap instruction is executed at a different address.

Next, FIG. 8 shows a configuration diagram of the multiprocessor operation mechanism A8 for realizing the register transfer instruction and the stop / restart instruction shown in FIG. H1 and H2 are synchronous facilities,
Performs data transfer and synchronization between the processor elements. H3 is a bus arbitration circuit that arbitrates the right to use the bus when performing data transfer or the like between the processor elements. h1 to h3 are address lines, data lines,
This is a signal line including a control line and the like. Note that h1 is generally called a communication bus.

By using such a multiprocessor operation mechanism A8, it is possible to execute a program in cooperation between the processor elements. As shown in FIG. 6, the coordination instruction between the processor elements described in this embodiment is a "register transfer instruction" for transferring the contents of a register between the processor elements. A "stop instruction" for stopping an element and a "restart instruction" for restarting a processor element stopped at a specified address. FIG. 9 shows an example of the format of each instruction. Regarding the register transfer instruction, two types of formats are shown.

In the register transfer instruction (1), the format of the transmission instruction executed by the transmission-side processor element is different from the format of the reception instruction executed by the reception-side processor element. When using these two instructions in combination,
In the transmission instruction, the number of the register holding the value to be transferred (R1) and the number of the receiving processor element (PE
#), 3 of the register number (R2) for storing the transferred value
Specify the type. There is no need to specify anything in the receive command. The instruction format of the register transfer instruction (2) is common to transmission and reception. In the transmission instruction, the number of the register holding the value to be transferred (R1) and the number of the receiving processor element (PE #) are specified. In the receiving command,
The register number (R1) for storing the transferred value,
Specifies the number (PE #) of the transmitting processor element.

In the the format of register transfer instruction of FIG. 9, for field to specify the number of processor elements is 11 bits, a case of performing one-to-one register transfer, the number of processor elements is up to 2 ¹¹ acceptable. Also, in order to enable one-to-many register transfer, one bit must correspond to one processor element, so that a maximum of 11 processor elements can be provided.

In register transfer, two types of synchronization methods can be considered. That is, regardless of whether the receiving processor element is executing the receiving instruction or not, the transmitting processor element can transmit the contents of the register and execute the next instruction as it is (synchronous method (a)). There is a method (synchronization method (b)) in which the transmission-side processor element is temporarily stopped until the reception-side processor element executes the reception instruction. Four types of hardware can be considered by combining the above-mentioned two types of formats and two types of synchronization methods. In the present embodiment, the instruction format (1) and the synchronization method (a) are combined. Only two types of hardware and hardware combining the instruction format (2) and the synchronization method (b) will be described. The other two types of combinations can be easily changed from the following two types of hardware.

FIG. 9 also shows a stop instruction and a restart instruction. The address specified in the stop instruction and the restart instruction is calculated by the register R1, the displacement d, and the base register Rb. In an ordinary computer, (Rb + R1 + d) is often calculated as an address, but in the present invention, it is sufficient if it is guaranteed that the stop address is uniquely determined by these values.

FIGS. 10 to 14 show hardware configuration diagrams for realizing the register transfer instruction. FIGS. 10 and 11 show hardware combining the instruction format (1) and the synchronization method (a). FIGS. 12 and 13 show hardware in which the instruction format (2) and the synchronization method (b) are combined. FIG. 14 shows a priority determining circuit common to the two types of hardware. Hereinafter, according to the order of the figure numbers,
Give an explanation.

FIG. 10 shows the instruction format (1) and the synchronization method (a).
5 shows the inside of the synchronization facility H1 when combined with.
The same applies to the synchronous facility H2. In the synchronous method (a), the processor element that has executed the transmission instruction does not wait for the reception instruction of the receiving processor element. Therefore, for each processor element, it is necessary to prepare a buffer (register file) for temporarily holding the value of the transferred register and the number of the register in which the value is to be stored. . I1 is a synchronous register file that holds the register value and the register number of the storage destination. I2 and I3 are address registers for specifying the address of the synchronization register file, and are used when the receiving processor element reads out the received value and when the transmitting processor element writes the transmitted value. I4 is an adder that increases the value of each address register after reading / writing of the synchronization register file I1 by the address registers I2 and I3. This is because the synchronous register file I1 performs reading and writing in a FIFO (first-in first-out) format, so that both the address registers I2 and I3 must increase the address after reading and writing. I5 is a selector, which selects an address input to the synchronization register file I1 from one of the address registers I2 and I3 according to each operation of read / write. I6 and I7 are comparison circuits. If there is no data stored in the synchronous register file I1, the processor element that executes the receiving instruction is stopped, and if the data is stored up to the capacity limit of the synchronous register file I1, the processing that executes the transmitting instruction is stopped. The sensor element must be stopped. Assuming that the value of the read address register I2 is RA and the value of the write address register I3 is WA, a signal indicating "WA = RA" is generated, thereby generating a synchronous register file.
It can indicate that there is no data stored in I1. Further, it is possible to indicate that data is stored up to the capacity limit of the synchronization register file I1 by a signal representing “WA + 1 = RA”.

i1 to i8 indicate control lines. i1 is a clock signal line, which is used as an input clock by the processor element A
2. The address registers I2, I3, etc. operate. i2 is a read signal line, which is turned "ON" when the processor element A2 executes a reception command. i3 is a write signal line. When another processor element executes a transmission instruction to its own processor element, a signal i3 is sent.

When a read request and a write request to the synchronous register file I1 occur at the same time, it is necessary to wait for one of the requests. FIG. 10 shows a case where the hardware waits for a read request. Read signal line i2
AND AND write signal line i3
A request is issued to processor element A2 as i4. The processor element A2 suspends the execution of the instruction while the read inhibition signal i4 indicates "ON". i5 and i6 are output signal lines of the comparison circuit, which indicate that there is no data stored in the synchronization register file I1 and that data is stored up to the capacity limit. The signal line i5 is connected to the processor element A2. When the processor element A2 attempts to execute the reception command while the signal line i5 indicates "ON", the processor element A2 enters a temporary stop state. The data is actually read from the synchronous register file I1 when the receiving instruction is executed, there is no write request, and there is data stored in the synchronous register file I1. Therefore, the logical product of the signal lines i2, i4 'and i5' is
And this is used as a control line for the read address register I2 (x 'represents negation of x). After reading data from the synchronous register file I1, the signal i7 is
Increase I2. The same is true for writing data to the synchronous register file I1, executing a transmission instruction,
This is performed when data is not stored up to the capacity limit of the synchronous register file I1. Therefore, signal line i3
A logical product of the logical address of i6 'and i6' is defined as a signal line i8, which is used as a control line of the write address register I3. The signal i8 increases the address register I3 after writing data to the synchronization register file I1. The signal i8 also controls the selector I5,
It is also used to control the read / write mode of the synchronization register file I1.

i9 and i10 are signal lines for transmitting and receiving the value of the register and the number of the storage destination register. Reference numeral i11 denotes various control lines, including a signal line for requesting the right to use the communication bus h1, a signal line for designating the number of the receiving processor element, and the like.

FIG. 11 shows an internal configuration diagram of the bus arbitration circuit H3. J1 is an oscillator that generates a clock signal. This may be considered the same as the basic clock A11. J2 is a priority determining circuit, and when the use of the communication bus h1 conflicts with a plurality of processor elements, the right to use the communication bus h1 is assigned to one of the processor elements according to a variable or fixed priority. To be awarded. J3 and J4 are flip-flops for storing the right to use the communication bus h1, and this value is set to "ON" while the right to use is given to each processor element. J5 is a multiplexer, and according to the processor element number specified by the transmission instruction,
The given signal is sent to one of the output signal lines.

j1 to j14 are signal lines constituting the communication bus h1. j1
Is a clock signal line for outputting a clock signal for controlling the entire data processing device of the present invention. The signal line j1 corresponds to the signal line i1 in FIG. j2 and j3 are bus request signal lines, and each processor element outputs bus request signals j2 and j3 when using the communication bus h1 for register transfer. j4 and j5 are bus grant signal lines. When a bus request signal j2, j3 is output from a certain processor element and the right to use the communication bus h1 can be given, a bus grant signal j4, j5 is sent to the processor element. When a bus request signal is output from a plurality of processor elements at the same time, the right to use the communication bus h1 is granted via the signal line j4 or j5 according to the fixed or variable priority. j6 and j7 are write inhibit signal lines. As described in FIG. 10, a certain processor element executes a transmission instruction,
Further, when data is stored up to the capacity limit of the synchronization register file I1 of the receiving processor element, it is necessary to temporarily stop the transmission command. When it is necessary to stop the transmission command, a write inhibit signal is transmitted to signal lines j6 and j7. j8 and j9 are signal lines indicating that data is stored up to the capacity limit of the synchronization register file I1. j10 and j11 are write signal lines for sending out a signal indicating that a transmission instruction has been executed to each processor element. Signal lines j8 and j10 are signal lines in FIG. 10, respectively.
Corresponds to i6, i3. j12 is a signal line for designating a processor element number. Used to specify the receiving processor element when executing a transmission instruction. Signal line j
2, j4, j6 and j12 correspond to the signal line i11 in FIG. j
13 and j14 are data lines and signal lines for specifying register numbers, respectively.
These are only managed using the bus grant signals j2 and j3 and the bus grant signals j4 and j5, and are not directly used in the bus arbitration circuit H3.

Next, the signals j6, j7, j10 generated in the bus arbitration circuit H3 are
The generation method of j11 is described. The method of generating the bus grant signals j4 and j5 will be described later with reference to FIG. The write request signals j10 and j11 are signals sent to the processor element specified when the transmission command is executed. Here, the processor element number is specified by the signal line j12, and the fact that any of the processor elements is executing the transmission instruction is specified by the logical sum j15 of all the bus grant signals. Accordingly, the multiplexer J having the signal line j15 as an input and the processor element number j12 as a selection signal
The output signal of No. 5 may be used as it is as write request signals j10 and j11. The write inhibit signals j6 and j7 are transmitted when the data is stored up to the capacity limit of the synchronous register file I1 of the receiving processor element when the transmission command is executed. The fact that data is stored up to the capacity limit of the synchronous register file I1 is indicated by signal lines j8 and j9, and that the transmission instruction is being executed is indicated by signal lines j4 and j5 or j10 and j11.
(J4 and j5 are detected on the transmitting side and j10 and j11 are detected on the receiving side). Therefore, the logical product j16 of the signal lines j8 and j10 or the logical product j17 of the signal lines j9 and j11 is received. Indicates a write inhibit signal in the side processor element. If all the logical sums j18 of the signals j16, j17, etc. are generated and the logical product of the signal line j18 and j4, j5 is generated, these become write inhibit signals j6, j7 in the transmitting processor element.

Next, the instruction format (2) shown in FIG.
A description will be given of hardware that combines the above and the synchronization method (b). FIG. 12 shows a synchronization facility H1 when the instruction format (2) and the synchronization method (b) are combined. As shown in FIG. 12, the synchronization facility H1 is composed of only signal lines, and the multiprocessor operating mechanism A8 is realized by centralized management by the bus arbitration circuit H3. m1 is a clock signal line, which is the same as the signal line i1 in FIG.
m2 and m3 indicate a read signal line and a write signal line. When the register transfer instruction is executed, a signal is transmitted to the read signal line m2 when the reception instruction is executed, and to the write signal line m3 when the transmission instruction is executed. m4 is a transfer prohibition signal, which is used to temporarily stop the processor element A2 when a transmission command and a reception command do not correspond in register transfer. m5 is a data line, and m6 is various control lines.

FIG. 13 shows an internal configuration diagram of the bus arbitration circuit H3. J1 ~
J4 and j1 to j5 are the same circuits and signal lines as in FIG. N1 and N2 are multiplexers that have a role of transmitting a read signal to the transmitting processor element when the receiving instruction is executed. N3 and N4 are similar multiplexers, but have a role of transmitting a write signal to a receiving processor element when executing a transmission instruction. N5 and N6 are selectors used when executing the transmission instruction. A read signal line of the receiving processor element is selected by inputting a read signal from each processor element and designating the number of the receiving processor element. Since the read signal line indicates that the processor element has executed the reception instruction, the contents of the register can be transferred when the outputs of the selectors N5 and N6 indicate "ON" at the time of execution of the transmission instruction. N7 and N8 are selectors used when executing the reception instruction. The write signal from each processor element is input, and the number of the processor element on the transmission side is designated to select the write signal line of the processor element on the transmission side. Similarly to the transmission instruction, when the outputs of the selectors N7 and N8 indicate "ON" at the time of execution of the reception instruction, the contents of the register can be transferred.

n1 and n2 and n3 and n4 are a read signal line and a write signal line, respectively. The signal lines n1 and n2, and n3 and n4 become "ON" when a reception command and a transmission command are executed. The signal lines n1 and n3 are the first
This corresponds to the signal lines m2 and m3 in FIG. n5 and n6 are transfer inhibition signal lines. A signal is sent when a transmission command or a reception command is executed and the other processor element is not executing the reception command or the transmission command. Execution of the processor element is suspended by the transfer inhibition signals n5 and n6. The signal line n5 corresponds to the signal line m4 in FIG. n7 and n8 are signal lines for designating a processor element number, and indicate a processor element number of a designated transfer partner when a register transfer instruction is executed. Signal lines j2, j4 and n7 correspond to signal line m6 in FIG. n9
Is a data line, which corresponds to m5 in FIG.

The signals n5 and n6 generated in the bus arbitration circuit H3 are transmitted when the transmission command or the reception command is executed and the corresponding reception command or the transmission command is not being executed by the other processor element. The fact that the other processor element is executing the reception instruction is based on the output signal n of the selectors N5 and N6.
According to 10, n11, the transmission instruction is being executed.
This is indicated by output signals n12 and n13 of N7 and N8, respectively. Accordingly, the execution of the transmission instruction and the fact that the other processor element is not executing the reception instruction are performed by signals n3 and n1.
It can be indicated by a logical product n14 of 0 'or a logical product n15 of signals n4 and n11'. The fact that the receiving instruction is being executed and the other processor element is not executing the transmitting instruction is indicated by the logical product n16 of the signals n1 and n12 'or the logical product n17 of the signals n2 and n13'. Is possible. OR of signal lines n14 and n16, signal lines n15 and n17
Are the transfer prohibition signals n5 and n6.

FIG. 14 shows an internal configuration diagram of the priority order determination circuit J2 used in FIG. 11 and FIG. Bus request signals j2, j3 and bus grant signals j4, j of each processor element
5, and clock signal j1 are input. R1 and R2 are flip-flops. R1 is used to delay the input to the flip-flop R2, and R2 is used to store the processor element to which the previous bus grant signal was given.

Bus request signals j2 and j3 of each processor element
Do not conflict with each other, the bus request signals j2 and j3 can be directly used as the inputs of the flip-flops J3 and J4, and the bus grant signals j4 and j5 can be given. However, the bus request signal j2
And j3 conflict (the logical product r1 of the signal lines j2 and j3 is "ON"
In this case, it is necessary to calculate the priority between competing processor elements and send a bus grant signal to the processor element having a higher priority. Although there is a method of setting a fixed priority between the processor elements, the priority determining circuit shown in FIG. 14 employs a method of lowering the priority of the processor element to which the bus grant signal was given last time. .

The negation r2 of the logical sum of the bus grant signals j4 and j5 of each processor element is used as the clock input of the flip-flop R2. As a result, one of the bus grant signals becomes "O
When the state changes from "N" to "OFF" (the right to use the communication bus is relinquished), the contents of the flip-flop R2 are rewritten.
Flip flop R1 is the second processor element
The bus grant signal j5 of A3 is input. The flip-flop R1 delays the bus grant signal j5 of the second processor element A3 in synchronization with the clock signal j1.
The output signal line r3 of the flip-flop R1 is connected to the flip-flop.
It becomes the input signal of R2. For this reason, flip flop R2
Will record whether or not the given bus grant signal is for the second processor element A3 when any processor element relinquishes the right to use the communication bus. The output signal line of the flip-flop R2 is denoted by r4. When the bus request signals j2 and j3 compete, when the signal r4 is "ON" (when the previous bus grant signal has been given to the second processor element A3), the first processor element A2 To the bus grant signal j4, and when the signal r4 is "OFF", the second
The bus grant signal j5 is supplied to the third processor element A3. However, if a bus grant signal has already been given to any of the processor elements, that state shall be maintained.

When the above-described logic is used as a circuit, the input signal to the flip-flop J3 is (r1'.j2 + r1. (R4.r2 + j4)) The input signal to J4 is (r1'.j3 + r1. (R4'.r2 + j5) ). Note that xy indicates the logical product of x and y, and x +
y indicates the logical sum of x and y. The meaning of each term in each logical expression indicates that r1'.j2 and r1'.j3 do not conflict with bus request signals, and r1.r4.r2 or r1.
R4'.r2 indicates a case where a bus request signal conflicts (r2 indicates that a bus grant signal has not been given to any of the processor elements). r1, j4 and r1
J5 indicates that when a bus grant signal is already given, the bus grant signal is continued.

Next, hardware for realizing the stop instruction and the restart instruction shown in FIG. 9 will be described. FIG. 15 shows a synchronization facility H1 for executing a stop instruction and a restart instruction. T1 is a stop address register which stores an address to be specified when the processor element A2 executes a stop instruction. T2 is a comparison circuit, which compares the address input from the communication bus h1 with the stop address register T1 when another processor element executes the restart instruction.

t1 is a clock signal line, which is similar to i1 or m1. A restart signal line t2 is output simultaneously with the address line t3 when a restart instruction is executed. Address line t3
Is used to specify an address when executing a restart instruction and when executing a stop instruction. When the restart instruction is executed, the address is output to the communication bus h1, but when the stop instruction is executed, the address is stored in the stop address register T1. t6 is a stop signal line. The signal line t6 is output at the same time as the address line t3 when the processor element A2 executes the stop instruction, and is used to store a specified address in the stop address register T1. t4 and t5 are both address lines, respectively, the output of the stop address register T1 and the communication bus.
Indicates an address from another processor element obtained via h1. These are the input signals of the comparison circuit T2, and it can be shown by the signal line t8 that both addresses match. When the signal t8 is turned "ON" and another processor element sends the restart signal t7, a signal t9 for activating the stopped processor element is sent to the processor element A2. t10 is various control lines, and includes a control signal for managing the communication bus h1 and the like.

In the hardware for realizing the stop instruction and the restart instruction, the role of the bus arbitration circuit H3 only manages the right to use the address line and the control line in the communication bus h1. Therefore, the internal configuration of the bus arbitration circuit H3 is shown in FIG.
In the figure, an oscillator J1, a priority determining circuit J2, flip-flops J3 and J4, a clock signal j1, and a bus request signal
Only circuits including j2 and j3 and bus grant signals j4 and j5 are required.
That is, the hardware capable of executing all the three types of coordination instructions, the register transfer instruction, the stop instruction, and the restart instruction already described, is a synchronous facility H1 combining FIG. 10 or FIG. 12 and FIG. This can be realized by using the bus arbitration circuit H3 shown in FIG. 13 or FIG. It is also possible to combine these hardware with the hardware shown in FIG. 7 to control the Compare & Swap instruction.

16 to 21 show an operation example of the control command shown in this embodiment. 16 to 20 show an operation example when the instruction format (1) and the synchronization method (a) shown in FIG. 9 are combined, and FIG. 21 shows an operation example when a stop instruction and a restart instruction are executed. Is shown. When the instruction format (2) and the synchronous system (b) are combined, as shown in FIGS. 12 and 13, except for the priority order determination circuit J2 and the flip-flops J3 and J4, the sequential circuit (storage circuit) Does not exist. Therefore, an operation example for this hardware is not shown.

An operation example in which the instruction format (1) and the synchronization method (a) are combined will be described with reference to the timing charts of FIGS. 16 to 20. FIG. 16 is a timing chart in the case where the first processor element (PE1) executes a transmission instruction to the second processor element (PE2). First, the transmitting processor element sends out a bus request signal (BR). When neither processor element uses the communication bus, a bus grant signal (BG) is given in synchronization with a clock signal (clock). When a communication bus is used or when a bus request signal competes, a bus grant signal may not be given immediately. After receiving the bus grant signal, the transmitting-side processor element receives the number of the receiving-side processor element (PE) specified in the transmission command and the value of the specified register (dat
a) Send the number of the register on the receiving side (REG). In addition,
In FIG. 16, the interval of sending these data is 1.5 clock cycles, but this length can be changed by various factors such as the arrangement of the processor elements. By designating the processor element number by the transmission instruction, a write signal (write) is sent to the receiving processor element. If data is not stored up to the capacity limit of the synchronization register file of the receiving processor element, the value of the designated register and the number of the receiving register are written in the synchronization register file, and the write address register (WA) is increased. At the end of the transfer, the bus request signal is changed to "OFF", whereby the bus grant signal changes to "OFF".

FIG. 17 is also a timing chart when the transmission command is executed. However, the case where the data is stored up to the capacity limit of the synchronization register file of the receiving processor element at the beginning of the execution of the transmission command is shown. The signals of BR, BG, PE, data, REG in the transmitting-side processor element and the signals of write and WA in the receiving-side processor element are the same as in FIG. When data is stored up to the capacity limit of the synchronization register file of the receiving processor element (when the full signal is "ON"), a write inhibit signal (Inhibit) is transmitted as a logical product of write and full signals. . As a result, the transmitting-side processor element is temporarily stopped while holding the right to use the communication bus. When the receiving processor element reads the contents of the synchronization register file by the receiving command and changes the full signal to "OFF", the write inhibit signal of the transmitting processor element becomes "OFF" and the pause state is released. . As a result, the value of the designated register and the number of the register on the receiving side are stored in the synchronization register file on the receiving side. in this case,
The time during which data is output to each of the PE, data, and REG signals of the transmission-side processor element becomes longer by the time the write inhibit signal is "ON". The same applies to BR and BG.

FIG. 18 shows another timing chart when the transmission command is executed. When the transmission instruction is executed, if data is stored up to the capacity limit of the synchronization register file of the receiving processor element, the right to use the communication bus is relinquished. When the write-inhibit signal is sent to the transmitting-side processor element, the transmitting-side processor element is temporarily stopped, and the bus request signal is changed from "ON" to "OFF". As a result, the bus grant signal also changes to "OFF", meaning that the right to use the communication bus has been abandoned. Thereafter, when the full signal changes from “ON” to “OFF” in the receiving processor element, an interrupt or the like is generated for the transmitting processor element, and the pause state of the transmitting processor element is released. . The system shown in FIG. 18 is a system for reducing contention of the communication bus.

FIG. 19 shows a timing chart when the reception command is executed. The receiving processor element (PE1) outputs a read signal (read), and reads the transferred register value (data) and data storage destination register number (REG) from the synchronization register file. At this time, the contents of the read address register (RA) are increased. Although the output interval of the read signal is set to 1.5 clock cycles during execution of the reception command, this length can be changed by various factors such as the arrangement of the processor elements.

FIG. 20 shows a timing chart when there is no data stored in the synchronization register file at the time of executing the reception command. The meanings of the read, data, REG, and RA signals are the same as in FIG. When the receiving-side processor element executes the receiving instruction and outputs a read signal, data stored in the synchronous register file may not exist.
In this case, the empty signal is "ON". The processor element that has executed the reception instruction determines from the empty signal that there is no data stored in the synchronization register, and enters a pause state. At this point, another processor element executes a transmission instruction to PE1 (write
Signal “ON”) and the empty signal changes from “ON” to “OFF”. As a result, the receiving processor element is released from the suspended state, and reads the transferred register value and the number of the data storage destination register from the synchronization register file as in FIG. Increase the content of

FIG. 21 is a timing chart at the time of executing a stop instruction and a restart instruction. 1st processor element (PE1)
Sends a stop instruction to the second processor element (PE
2) executes the restart instruction. When the stop instruction is executed, the address (WAR) specified by the instruction is transmitted, and the stop signal (sleep) is output. The stop signal causes the designated address to be stored in the stop address register. After outputting the stop signal, PE1 enters the pause state.

In response to the restart instruction, all the processor elements that are in the pause state at the specified address are restarted. Therefore, the specified address is notified to all the processor elements via the communication bus. Therefore, PE2
Must first output a bus request signal (BR) and secure the right to use the communication bus by a bus grant signal (BG). After the right to use the communication bus is secured, the resume signal (resume) and the address (ad
dress) on the communication bus. The output address is compared with the contents of a stop address register on another processor element, and if they match, a wake-up signal (wakeup) is sent to the corresponding processor element. This allows
The suspended processor element resumes execution. The output interval of both the stop signal and the restart signal is 1.5 clock cycles, but this length can be changed by various factors such as the arrangement of the processor elements.

Lastly, a method of switching between the parallel operation mode and the multiprocessor operation mode in the parallel processing device of the present invention will be described.

In the present invention, two instructions, a multiprocessor operation instruction and a parallel operation instruction, are prepared as special instructions for switching between two operation modes. The multiprocessor operation instruction sets the parallelization flag A7 to the multiprocessor operation mode. The parallel operation instruction sets the parallelization flag A7 to the parallel operation mode. Each instruction is a privileged instruction that can be executed only by the OS (operating system).

FIG. 22 shows an example of the flow of OS control when changing from the parallel operation mode to the multiprocessor operation mode. When the program running in the parallel operation mode ends or pauses (X1), the OS is started (X2). In the OS, a new program to be executed is extracted by the scheduling X3. At this time, if there is no program to be executed, an idle loop waits until a new program is generated. The OS checks the parallelism of the program to be executed (X
4) If the degree of parallelism is high, the parallel operation is efficient, and the process exits from the OS control in the parallel operation mode (X
Five). When the degree of parallelism is low, it is more efficient to execute a plurality of programs in parallel in the multiprocessor operation mode. Therefore, the multiprocessor operation instruction is executed (X6), and each processor element is operated independently.
Since the program to be executed by the first processor element has already been selected in the scheduling X3, the control directly exits from the OS control (X7). Also, the second
In the processor elements following the first one, a new scheduling X8 is performed, and a program to be executed is extracted.

FIG. 23 shows an example of the flow of OS control when changing from the multiprocessor operation mode to the parallel operation mode. It is assumed that the program executed by the first processor element among the plurality of processor elements has been completed (Y1). In the same manner as in FIG. 22, OS startup Y2 and scheduling Y3 are performed, and thereafter, the degree of parallelism of a program to be newly executed is checked (Y4). If the degree of parallelism of the program is low, the control exits the OS in the multi-processor operation mode (Y5). When the degree of parallelism of the program is high, the parallel operation mode is more efficient. Therefore, a parallel operation instruction is executed (Y6), and the mode shifts to the parallel operation mode. At this time, since it is impossible to change to the parallel operation mode while another processor element is executing the program, executing the parallel operation instruction is performed by waiting for the end of the program (Y7). Later. When the program being executed by the other processor element is terminated or temporarily stopped, the parallel operation instruction is executed.

The degree of parallelism of the program described here can be known at the time of converting the source program into the target program. Therefore, the OS can recognize the degree of parallelism by embedding the degree of parallelism of the program in the target program by a compiler or the like.

〔The invention's effect〕

By using the data processing device of the present invention, it is possible to realize a configuration of a computer system optimal for the program according to the degree of parallelism inherent in the program. In other words, if the degree of parallelism inside the program is high, the program should be executed in parallel operation. Can be. As a result, the operation rate of a plurality of processor elements can be improved, and as a result, the performance can be improved as compared with a multi-processor computer system or a superscalar computer system.

In a multiprocessor type computer system, dedicated hardware is rarely provided for synchronization and data transfer between the processor elements, and even if dedicated hardware is provided, the high speed is not so important. Note that in the present invention, each processor element is arranged "close" for parallel operation,
High-speed synchronization and data communication can be performed between processor elements even during multiprocessor operation. Accordingly, even when a plurality of programs operate in cooperation with each other, the speed can be easily increased.

[Brief description of the drawings]

FIGS. 1 and 2 show the overall configuration of a data processing apparatus according to the present invention, FIG. 3 shows the internal configuration of a processor element, and FIG.
5 and 5 are diagrams showing the internal configuration of the cache control device, FIG. 6 is a diagram showing the functions of the multiprocessor operation mechanism, and FIG. 7 is an internal configuration diagram of the multiprocessor operation mechanism for performing the exclusive control function. , FIG. 8 is an internal configuration diagram of a multi-processor operation mechanism for executing a coordination instruction between processor elements, FIG. 9 is a format of a coordination instruction between processor elements, FIG. 10, FIG. 12, and FIG. 11 and 13 are internal configuration diagrams of a bus arbitration circuit, FIG. 14 is an internal configuration diagram of a priority order determination circuit, and FIGS. 16 to 20 are diagrams for explaining a register transfer instruction. FIG. 21 is a timing chart for executing a stop instruction and a resuming instruction, and FIGS. 22 and 23 are control flow charts of an OS when switching between a multiprocessor operation mode and a parallel operation mode. A1 …… Processor, A2, A3 …… Processor element, A
5: Cache storage device, A6: Cache control device, A7: Parallelization flag, A8: Multiprocessor operation mechanism, A9, A10: Parallel operation mechanism, B1: Instruction cache, B2: Data cache Push, D1 to D4: Instruction register, D5 to D8: Decoder, D11 to D14: Arithmetic unit, D1
5, D16: Register file, H1, H2: Synchronous facility, H3: Bus arbitration circuit, h1: Communication bus, I1: Synchronous register file, I2: Read address register
I3 Write address register, J1 Oscillator, J2
… Priority order determination circuit, T1… Stop address register.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-321549 (JP, A) JP-A-59-16071 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G06F 15 / 16,15 / 80

Claims (8)

(57) [Claims] 1. A data processing apparatus comprising: n processor elements; a basic clock for operating the n processor elements; a cache memory shared by the n processor elements; and a memory device. The apparatus includes a multiprocessor operating mechanism for operating the n processor elements independently, a parallel operating mechanism for simultaneously operating the n processor elements in synchronization with the basic clock, and an operating state of the data processing device. A parallel operation flag, a parallel operation mechanism that causes the data processing device to perform either the multiprocessor operation or the parallel operation according to the parallel operation flag, and a data read / write width of the cache storage device according to the parallel operation flag. And a cache control mechanism for changing the number of data read / writes. Processing apparatus. 2. The data processing device according to claim 1, wherein said parallel operation mechanism simultaneously reads n instructions sequentially arranged in said memory device or said cache storage device according to said basic clock, and said n instructions Is simultaneously shared with the n processor elements, and the n processor elements are simultaneously executed in synchronization, thereby executing n instructions in parallel. 3. The data processing device according to claim 1, wherein said n processor elements each include m instruction registers, m instruction decoders, and m arithmetic units, and at least m inputs and 2 × m outputs. A data processing device having a multi-port register file having ports and executing m instructions in parallel. 4. The data processing device according to claim 3, wherein said parallel operation mechanism simultaneously reads out n × m instructions sequentially arranged in said memory device or said cache storage device in accordance with said basic clock, and reads out said n × m instructions. m instructions
A data processing device for simultaneously executing n × m instructions in parallel by simultaneously supplying the n processor elements in units of units and simultaneously executing the n processor elements in synchronization. 5. The data processing device according to claim 1, wherein said n processor elements each have a program counter pointing to addresses of m consecutively arranged k-bit instructions, and said cache control device comprises: When the parallelization flag indicates the multiprocessor operation, the cache storage device is individually read out from the addresses pointed to by the respective program counters of the n processor elements, m m-bit instructions are read. n
If the address input / m × k bits, n output mode is set and the parallelization flag indicates the parallel operation, the cache storage device is set to n ×, A data processing device for reading one instruction continuously, setting one address input / n × m × k bits, and one output mode. 6. The data processing device according to claim 1, wherein said multiprocessor operating mechanism comprises: a communication bus for transferring data between said n processor elements; a bus arbitration circuit for managing said communication bus; A data processing device having n synchronization facilities for performing synchronization between elements. 7. The data processing device according to claim 1, wherein the multiprocessor operating mechanism includes a reference control signal line and a reference address line for the memory device for the n processor elements, respectively. When referring to the memory device from the plurality of processor elements, a reference execution right is given to only one of the processor elements in the case of a reference request to the same address, and a reference execution right is simultaneously provided in a reference request to a different address. Data processing device that controls to give 8. The data processing device according to claim 1, wherein said data processing device sets a parallel operation instruction to set said parallelization flag to said parallel operation, and sets a multiprocessor operation to set said parallelization flag to multiprocessor operation. A data processing device having instructions and two types of configuration control instructions.