JP2834182B2 - Modulation and demodulation of digital signals - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation method of a recording signal in a device for recording / reproducing a digital signal and a demodulation method suitable therefor.

[Conventional technology]

As a modulation scheme suitable for a digital VTR, a modulation scheme called a so-called mirror square is often used. For example, "TV Technical Report Vol. 12, No. 56 (December 1988
Mon) uses this mirror square code in the D-2 format VTR. This code has the advantage of having no DC component, but has the disadvantage that the equivalent S / N is 3 dB worse than that of NRZ recording because the aperture width of the eye pattern is narrow.

It is well known that the NRZ code is the widest modulation code in terms of the aperture width. However, since NRZ gives a high level to data 1 and a low level to data 0, when data 1 or 0 continues, a DC component is generated. In a digital VTR using a rotary transformer, a cause of a code error is generated. It was connected.

[Problems to be solved by the invention]

The above-described conventional mirror square cord has a drawback that the aperture width is narrow at the emphasis of DC component removal. When trying to record data at a higher speed than before in a digital VTR, for example, when trying to digitize and record a high-definition television signal, a narrow aperture width means that the equivalent S / N becomes worse, This was the biggest net when trying to increase the recording density.

An object of the present invention is to provide a modulation method and a demodulation method in which the generation of a DC component is smaller than that of an NRZ code and the aperture width is the same as that of the NRZ code, that is, half the mirror square.

[Means for solving the problem]

In order to achieve the above object, the present invention basically comprises an NRZI
In the data 1, the polarity of the signal is inverted in the middle of the data bit interval. For data 0, the polarity is not inverted. However, the data is combined two by two, and especially when all the data are 0 in a continuous set, that is, only when four consecutive 0s continue, the first two 0s and the second half 2
The polarity is inverted between the zeros and at the boundaries of the bit intervals.

On the other hand, when demodulation is performed after compensating for the signal deterioration of the tape-head system, the reproduced signal is identified by the binary identification circuit at the bit interval period, that is, at the same interval as NRZ during demodulation. In addition, 4
A ternary identification circuit is also used as an identification circuit to identify the polarity inversion due to "0".

The ternary discriminating circuit discriminates the reproduced signal by a so-called reproducing equalizing circuit, and then passes this signal through a limiter circuit.
This is done by inputting to a value identification circuit.

[Action]

Since the polarity inversion is performed when four consecutive 0s of the modulation code are present, there is no defense against the continuation of "0" as in NRZ and NRZI, and the generation of a DC component is small.

On the other hand, at the time of demodulation, since it is identified by the bit interval, the clock frequency is not the clock frequency of half the bit interval like the mirror square, but is the clock frequency of the bit interval like NRZ and NRZI.

If the output of the ternary discriminating circuit is always referred to, the equivalent S / N is degraded by 3 dB like a mirror square code. Therefore, 2
Only when there is a possibility that four consecutive “0” s exist in the value discriminating circuit, the ternary discriminating circuit is referred to, and the equivalent S / N
To prevent deterioration.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. To clarify the features of the present invention, waveforms of other modulation codes for the same data are also shown.

(A) is an NRZ modulation code for giving a high level to data 1 and a low level to data 0.

FIG. 3B shows a case where the polarity is inverted when the data is 1 in the NRZI modulation code.

(C) is a mirror square modulation code. In the case of data 1, the polarity is inverted at the center of the bit interval. When two data 0s continue, the polarity is inverted at the bit boundary. However, a condition is set that there is no polarity inversion at the boundary of the immediately preceding bit.

(D) is a waveform of the modulation code according to the present invention.
The polarity is reversed at the center of the bit interval. When the data is divided every two bits and four “0” s continue, 2
Invert the polarity at the bit boundary of two breaks.

FIG. 2 is a block diagram of a modulation circuit for generating a modulation code according to one embodiment of the present invention. FIG. 3 shows signal waveforms at various parts in FIG.

In FIG. 2, input data AB and CD are input terminals 1-1 to 1-1.
The data is input to the 4-bit shift register 3 through 1-4. The 4-bit register 3 takes in the four-phase input data A to D by the clock E generated by the clock generation circuit 4, reads out the data at high speed by the clock F, and creates high-speed serial data I. In order to cause inversion at the center of the data bit interval when the zeta I is at the high level, the inverted output of the data I and the clock F (inverted by the inverting circuit 5) is input to the AND circuit 7, and the output J is obtained. . On the other hand, in order to detect whether the data is all "0" every four units, the output H is used by using the AND circuit 8a via the inversion circuits 2-1 to 2-4.
Get. When the output H goes high, inversion occurs at the boundary of the data bits.
The inverted output of the clock E (inverted by the inverting circuit 6), the clock F and the clock G (the clock F is divided) are input, and the output K is obtained. Here, each clock is obtained by the clock signal generating circuit 4.

The output J and the output K are obtained by an OR circuit 9 to obtain an output L, which is input to a clock input terminal of a flip-flop 10. If the inverted output is connected to the delayed input D, the polarity of the output signal M is inverted at the rising edge of the clock input waveform, and the modulation code signal M of the present invention is obtained at the output terminal 11.

The method of demodulation during reproduction will be described with reference to the signal block diagram of the demodulation circuit in FIG. FIGS. 5 (a) and 5 (b) show signal waveforms at various parts in FIG.

The signal recorded on the magnetic tape 12 is read by the reproducing magnetic head 13 and input to the equalizing circuit 15 via the reproducing amplifier 14. The equalizing circuit 15 compensates for the frequency characteristics of the signal degraded in the recording / reproducing process, and performs equalization called integration detection. The output of the equalizing circuit 15 is limited in amplitude by a limiter circuit 16 so that amplitude fluctuations in the head output do not affect subsequent circuits. Limiter output a is 3 comparison circuits
It is input to clock extraction circuit 20 while being input to 17, 18, and 19. The clock extraction circuit generates a clock b having a period equal to the bit period and synchronized with the reproduced data a.

FIG. 6 shows an enlarged waveform of the output signal a of the limiter circuit 16. Since the amplitude V of the output signal a is constant, comparison level V _H to give three comparator circuits, V _L, V _a can be easily set, And

Outputs c, d, and e of the three comparison circuits are obtained. The output e is a conventional binary identification output, and in the modulation code,
Two data every separated connexion (referred to as one block), if all of the data in the two blocks is no polarity inversion I ₀ inserted 0, the position of the modulation code of the inversion of the output e Since it corresponds to data "1", it can be easily restored.

Therefore, when data is "0" in two consecutive blocks from the output e, it is necessary to detect and remove the inserted polarity inversion. At the time corresponding to the polarity inversion I _0, the comparison circuit
The 19 input signal is susceptible to noise by passing near 1/2 V, and the output e at that time becomes an unreliable value. In FIG. 5, it is indicated by oblique lines.

On the other hand, the outputs c and d of the comparison circuits 17 and 18 corresponding to the polarity inversion I ₀
In the polarity inversion I ₀ position is determined by the fact that the output c and the output d is different. However, simply output c and output d
Take the exclusive or of Therefore, how to receive the noise It is greater than in a higher probability of erroneous connexion detecting the polarity inversion I _0. Therefore, first, the data in the two blocks will detect the fact that a "0", further the time data at the output c and the output d is assumed that the polarity inversion I ₀ if the reversed had occurred.

Specifically, data before and after the two bits of the polarity inversion I ₀ is
Since the polarity is reversed, the output e is flip-flop 2
Delay by one clock at 5, 26, 27, 28.

The outputs e and e 'are input to an exclusive OR circuit 36, and inverted outputs of the outputs e and e' (not shown) Is similarly input to the exclusive OR circuit 35. circuit
The outputs of 35 and 36 are input to the AND circuit 39 via the inverting circuits 37 and 38, and the output (g) is obtained.

In the output (g) waveform of FIG. 5 (a), the hatched portion indicates that the uncertain region of the output e is propagating.

On the other hand, when the exclusive OR of the outputs c and d is taken, the exclusive OR circuit is delayed by two bits at the flip-flops 21, 22, and 23, 24 so that the time coincides with the output g. At 29, an exclusive OR output (f) is obtained.

The AND circuit 30 obtains an AND output (h) from the output (g) and the output (f). The polarity of the output (h) is inverted at the rising edge of the clock (detected by the output (f)).
The two bits before and after the polarity inversion have the same sign, the two bits after the same sign have the same sign, and the two bits before and after are opposite signs (output (g)).
In detection) indicates that, it means that that there is polarity inversion I ₀ been made to detect by eliminating the influence of noise.

Since the polarity inversion of the output (e) corresponds to the data "1", the outputs e "and e are input to the exclusive circuit 33 to obtain the output i, and the high level of the output i corresponds to the data 1. to. to remove the effect of the oblique line portion by polarity reversal I ₀ of the output e, (due to the inversion circuit 32.) inverted output j outputs h and 1 bit (by flip flop 31.) inverting output k of the delayed and output i The output 1 is input to the AND circuit 34 to obtain an output 1. Since there is a time difference between the output 1 and the clock b by the delay time of each logic element, the clock b is output.
When the output 1 is latched (by the flip-flop 40) at the inverted clock n (by the inverting circuit 41), composite data m in the NRZ format is obtained at the output terminal 42.

The above description is based on general NRZ format data as input data. Therefore, it is not known at all how much data "0" continues.

Conventionally, especially in the case of image data, since the property of the image data, that is, the correlation is high in the adjacent pixel data, the image is arranged in a word group arranged in the word order having the same weight (the weight is the number of data "1" in one word). Convert the data once,
A so-called 8-8 mapping system has been proposed in which the DC component is reduced by inverting the word between adjacent words. A small DC component corresponds to a discontinuity of data "0". Therefore, another embodiment of the application of the present invention is, as shown in FIG. 7, provided with an inverting circuit 44 for inverting the output signal of the 8-8 mapping conversion circuit 43 for each word, and then providing the modulation circuit of the present invention. 45 applies.

Still another form is to remove some of the 256 words of the 8-bit 256 words so as to prevent continuous “0” in consideration of the connection with the adjacent word,
A mapping method has been proposed. With this restriction 8-
It is conceivable to apply the modulation circuit 45 of the present invention after the 8-mapping circuit 46. In any case, the DC component is further reduced after the modulation as compared with the case of the conventional system alone, and the reliability of recording and reproduction in the rotary transformer and the winding head system is improved.

In the above explanation, when all data is 0 in 2 blocks,
The method of forcibly inserting the polarity inversion has been described. As another embodiment, the present invention can be applied to a system in which the polarity inversion is forcibly inserted simply when there are four consecutive data "0".

〔The invention's effect〕

According to the present invention, the maximum magnetization reversal width is 7 bits, the infinite magnetization reversal width does not occur unlike NRZ and NRZI, the DC component can be reduced, and the rotary Even in digital recording using a transformer and a winding head, highly reliable recording and reproduction with little signal deterioration can be realized.

[Brief description of the drawings]

FIG. 1 is a signal waveform diagram showing a modulation code according to one embodiment of the present invention, FIG. 2 is a circuit diagram of a modulation code generating circuit according to an embodiment of the present invention, and FIG. 3 is a signal waveform diagram of each part in FIG. FIG. 4 is a circuit diagram of a demodulation circuit according to an embodiment of the present invention, FIG. 5 is a signal waveform diagram of each part in FIG. 4, FIG. 6 is an enlarged view of a limiter output waveform,
7 and 8 are block diagrams of a signal modulation circuit according to another embodiment of the present invention. 3 ... 4 bit shift register, 4 ... clock generation circuit, 15 ... equalization circuit, 16 ... limiter circuit, 17,18,19 ...
... Comparison circuit, 20 ... Clock extraction circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03M 7/00 G11B 20/00

Claims (2)

(57) [Claims] 1. Inverting the polarity at the center of the bit interval in correspondence with data 1, and when two consecutive blocks of data appear as data 0 as two blocks of continuous two-bit data as one block. A modulation method of a digital signal, wherein a polarity inversion is inserted at a boundary position. 2. A demodulation system for a digital signal modulated by the modulation system according to claim 1, further comprising a first comparator for comparing the modulation signal with a predetermined threshold value, wherein the first comparator compares the polarity of the bit interval with the center of the bit interval. A first circuit unit for generating a pulse signal including insertion polarity reversal of the block boundary; a second comparator for comparing the modulation signal with a second threshold higher than the predetermined threshold; A third comparator for comparing with a third threshold lower than a predetermined threshold, a second circuit unit for generating a correction pulse corresponding to the insertion polarity inversion, and using the correction pulse signal A third circuit unit for removing the insertion polarity inversion from the pulse signal output from the first circuit unit.