JP2828491B2 - Storage control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention can reduce contention of requests for accessing one storage bank (independently operable storage unit) from a plurality of access request control devices. The present invention relates to a storage control method of a possible computer system.

2. Description of the Related Art Conventionally, in a storage control method, when processing an access request having a data width smaller than a processing unit of a storage device, when data corresponding to the access request is continuously allocated to the storage device, In order to avoid contention for access, a method has been proposed in which a plurality of access requests are combined into one to access a storage device (for example, Japanese Patent Application Laid-Open No.
175970).

The storage control method includes a mechanism for determining a priority order among a plurality of access requests by a single-stage priority order determination circuit,
A plurality of access requests issued from a plurality of access request control devices at the same time or at different times are divided into groups in the order of issuance for each storage unit, and the groups are collectively accessed as a single access request. Thus, conflicts between access requests are avoided.

[Problems to be Solved by the Invention] By the way, in order to meet the demand for performance improvement of the system, a multiprocessor system sharing a storage device has been configured. The same applies to a processor dedicated to scientific and technical calculations that requires a high memory throughput. Such a multiprocessor
In the system, the number of access request control devices from which access requests are issued becomes large. That is, the number of access request control devices sharing the main storage device is increased as compared with the single processor configuration, and the prior art performs priority control among a large number of access requests from these access request control devices. If this is attempted, the logic becomes complicated, the number of pins of the integrated circuit increases, and there is a problem that it is extremely difficult to physically realize it.

An object of the present invention is to reduce the contention when accessing one storage bank from a plurality of access request control devices by selecting the priority of an access request in multiple stages, to write and read data in the storage device. An object of the present invention is to provide a storage control method capable of improving the read throughput and simplifying the control logic configuration when there are many access request sources.

[Means for Solving the Problems] To achieve the above object, a storage control method according to the present invention comprises:
A storage device composed of a plurality of storage units that can be independently accessed, a plurality of access request control devices accessing the storage device, and a priority order between access requests issued by the plurality of access request control devices are determined. And a storage controller that sends the access request to the target storage unit. The storage system integrates a plurality of access requests with a data width smaller than the access processing unit of the storage device as a single access request. A control method, wherein the storage control device is configured by a plurality of stages of priority order determination means,
The access request control device integrates access requests issued by the access request control device based on a start address of the plurality of access requests, an address increment value, and connection mode information between the storage control device and the plurality of stages of priority order determination means. An access group information including the position information of the priority order determining means to be performed is added to the access request and sent to the storage control device, and each stage of the priority order determining means of the storage control device,
When an access request having access group information designating itself as an access integration location is received, the access requests are integrated after waiting for the arrival of the access request of the partner to be integrated.

The access group information includes, for example, the stage number of the priority order determining means and the number of integrated access requests.

In the storage control method, based on access request identification information indicating whether or not each access request accesses, a storage device address corresponding to an access request not to be accessed is compressed and stored in a storage device corresponding to the access request to be accessed. Means may be provided for detecting processing of an instruction for generating an address, and upon detecting the instruction, the access request identification information may be included in the access group information.

When the access request is for reading data from the storage device, the read data is conveyed to the access request control device that issued the access request by following the path through which the access request passed.

When the access request is storage of data in the storage device, for each data corresponding to a plurality of access requests to the same access processing unit in the access request control device, a data storage identification indicating a portion where the data is combined Information is generated, and each stage of the priority order determining means synthesizes data based on the data storage identification information.

When there is no access request to be integrated, the access request control device does not add the access group information to the access request, and no access group information is added at each stage of the priority order determining means. Access integration is not performed for access requests.

In each stage of the priority order determining means, when a part of the access request to the same access processing unit is integrated, the access group information in which the part of the access group information relating to the part is invalidated is transmitted to the subsequent stage. When all the access requests to the same access processing unit are added to the access request and integrated, all the access group information of the access request is invalidated.

According to another detection, the storage control method according to the present invention includes a storage device including a plurality of storage units that can be accessed independently, a plurality of access request control devices that access the storage device, and a plurality of access requests. A storage controller for determining a priority order between access requests issued by the request controller and transmitting the access request to the target storage unit, a data width smaller than an access processing unit of the storage device. A storage control method for integrating a plurality of access requests as a single access request, wherein the storage control device is configured by a plurality of stages of priority order determining means, and is sequentially assigned to the plurality of access request control devices. Means for detecting that a plurality of access requests out of a plurality of address consecutive access requests are accesses to one access processing unit In addition, at the time of the detection, access group information indicating at which stage of the priority order determination means integration of the access requests should be performed for a plurality of access requests is added to the access request and sent to the storage control device, In each stage of the priority order determining means of the storage control device,
The access requests are integrated based on the access group information.

[Operation] The present invention determines the priority of an access request to a storage device in multiple stages, and sends a plurality of access requests for accessing the same storage unit of the storage device to the same priority determination means. The position information of the priority order determining means and, in some cases, the number information of access requests to the same storage unit sent to the priority order determining means are added at the time of sending the access request. In
Waiting for access requests to the same number of storage units indicated by the number information, integrating the plurality of access requests into one access request, and sending it to the next priority determination means,
Finally, the plurality of access requests are combined into one access request to access the storage device.

In this operation, it is possible to know in advance the source access request control device number of each access request corresponding to the integrated access request and the number of access requests necessary to generate the integrated access request. The position information of the priority order determining means to be integrated and the information on the number of access requests in each stage can be added to the access request, and the information makes it possible to generate an integrated access request.

According to the present invention, since the priorities are performed in multiple stages, the control logic is not concentrated at one place, and it is easy to realize logically and physically.

Embodiment FIG. 1 shows a configuration example of a main part of a computer system adopting an embodiment of the present invention.

Here, the computer system uses a plurality of (8 in this embodiment) access request control devices 10A to 10H, and a plurality of access requests (the destinations of the access requests issued from the access request control devices 10A to 10H). In the present embodiment, it is assumed that the priority order is 8).
Second priority determining devices 12A to 12H for determining the priority between two access requests at each destination of the access requests issued from the first priority determining devices 11A to 11H, and the second priority determining device A destination of an access request issued from 12A to 12H, which is composed of third priority determining devices 13A to 13H for determining the priority between two access requests, and a storage device 14. The storage device 14 includes storage banks 14A to 14H corresponding to the third priority determination devices 13A to 13H on a one-to-one basis. As a result of decoding the address of the access request, each access request control device and the first and second priority determination circuits select which priority determination device each access request is sent to, and the third priority determination device. To access the corresponding storage bank. The access request control devices 10A to 1A
0D and 10E-10H each belong to a separate processor (not shown).

In the computer system shown in FIG. 1, a plurality of access requests having consecutive addresses are
The issuance of an access request in the case where the access requests are continuously assigned to A to 10H will be described.

The processing for issuing an access request differs depending on whether the issued instruction is detected as an invalid access request address compression instruction by the invalid access request address compression instruction detection circuit 20 (FIG. 2).

First, how an access request is issued when an invalid access request address compression instruction is not detected will be described with reference to FIG.

The access requests are sent to each of the access request control devices 24A to 24H.
(Corresponding to 10A to 10H in FIG. 1). Here, the access request control device 24A is taken as an example.

From the access request start address 21, the first address information signal 21 at which the plurality of consecutive access requests are started
is transmitted, and from the access request increment value 22, an information signal 22a of a value of the address width between the consecutive access requests is transmitted, and both are transmitted to the access group information generation circuit 241 in the access request control device 24A. .

From the integrated access request generation circuit connection information 23, the access request issued from each access request control device and the access request transmitted from each priority An information signal 23a indicating whether or not a connection is made to the request generation circuit is generated by the access group information generation circuit 2 in the access request control device 24A.
Sent to 41.

The access request valid identification information 24 is issued at the same time as the access request when the command is detected by the access request valid identification information control command signal 25a sent from the access request valid identification information control command circuit 25. When the command is not detected, the access request valid identification information (“valid” or “invalid”) corresponding to all the access requests is set to “valid”. The identification information signal 24a is sent to the access group information generation circuit 241, and the access request valid identification information signal 24 corresponding to only the access request is transmitted.
a 'is sent to the access request control circuit 240 and the data storage identification information generation circuit 242.

The access request control circuit 240 sends an access request signal 2
40a is issued to the access group information generation circuit 241; at the same time, the access request issues an access request issuer information signal 240c for returning a valid access signal to the issue destination access request controller after accessing the storage device; and A storage data signal if the access request is for storing data.
240d is sent to the access request issuing control circuit 243.

The access group information generation circuit 241 uses the received access request start address information signal 21a, the access request increment value information signal 22a, and the connection mode information signal 23a to generate the integrated access request in response to the access request. Number and the number of access requests for integrated access request generation are determined as access group information,
The access group information signal 241g is sent to the access request issuance control circuit 243 together with the access request signal 241e.

If the access request is for storing data,
The access group information generation circuit 241 sends an access group assignment information signal 241f indicating at which position in the address width of the storage processing unit the storage data corresponding to the access request is stored.
The data storage identification information generating circuit 242 indicates the access group assignment information. Access request valid identification information is generated at the position where the data of the storage processing unit is to be stored, and data storage identification information is embedded at all other positions with invalid information.
2a is sent to the access request issuing control circuit 243.

The access request issuance control circuit 243 selects the first priority determining device to which the access request is sent according to the address indicated by the access request signal 241e, and stores the access request, access group information, and access request issuer information in the first order. 1 Transmit to the priority determining device.

If the access request is for storing data,
The stored data is moved to the valid portion indicated by the data storage identification information, and the stored data and the data storage identification information are sent to the selected first priority determination device.

Using FIG. 3, the first of the access request and the stored data will be described.
The processing in the priority order determining device will be described.

For example, the access request signal 24Aa, together with the access group information signal 24Ab, the access request issuer information signal 24Ac, the data storage identification information signal 24Ad, and the storage data signal 24Ae, when issued from the access request control device, the previous access request signal 30Ba has its priority selected by the first priority determination circuit 32, so that the access request reception control circuit 35
Sends an access request acceptance permission signal 35e, and the flip-flops 30B to 30F enter the set state.

However, if the priority of the access request signal 30Ba is not selected by the first priority determination circuit 32, the access request acceptance permission signal 35e is not sent out, and accordingly, the access request signal 30B, the access group information signal 30C, and the access If the request issuer information signal 30D and the access request are for storing data, neither the data storage identification information signal 30E nor the stored data signal 30F is updated.

For example, an access request signal 24Aa, an access group information signal 24Ab, an access request issuer information signal 24Ac, and a data storage identification information signal if the access request is data storage.
24Ad and stored data signal 24Ae are both flip-flops.
When set in each of 30B to 30F, the access request signal 30B
a, the access group information signal 30Ca and the access request source information signal 30Da correspond to the first integrated access request generation circuit 310.
If the access request is for data storage, the data storage identification information signal 30Ea and the storage data signal 30Fa
Are sent to the first stored data synthesizing circuit 311 respectively. The first integrated access request generation circuit 310 determines whether the access request generates an integrated access request based on the access group information 30Ca. The first integrated access request generation circuit 310 and the first stored data synthesis circuit 311 constitute a first integrated access request generation device 31.

Similarly, the access request signal 24Ba, the access group information signal 24Bb, the access request source information signal 24Bc, and if the access request is for storing data, the data storage identification information signal 24Bd and the stored data signal 24Be are transmitted to the flip-flop 30.
H to 30L, the access request signal 30Ha, the access group information signal 30Ia, the access request issuer information signal 30
Ja transmits the first integrated access request generation circuit 310, the data storage identification information signal 30Ka, and the stored data signal 30La to the first storage data synthesis circuit 311. Further, the first integrated access request generation circuit 310 generates the integrated access request. Determines whether to generate.

Hereinafter, the case where the generation of the integrated access request is not detected and the case where the generation of the integrated access request is detected by the first integrated access request generation circuit 310 will be described.

First, a case where the integrated access request generation by the first integrated access request generation circuit 310 is not detected for the access request signal 30Ba will be described.

First, the access request signal 310b, the access group information signal 310c, and the access request issuer information signal 310d are sent to the first priority determination circuit 32. At this time, the integrated access request generation validity information signal 310a is invalidated and sent to the first priority determination circuit 32.

If the access request is for data storage, the storage data combining control information signal 310i is invalidated and sent to the first stored data combining circuit 311.

The first stored data synthesizing circuit 311 determines from the synthesized data generation instruction signal 310i that the stored data is not to be synthesized, and sends the stored data signal 311a and the data storage identification information signal 311b to the stored data selecting circuit 33. I do. The access request signal 310e and the access group information signal
310f and an access request issuer information signal 310g, and a storage data signal when the access request is data storage.
The same applies to 311c and the data storage identification information signal 311d.

Next, the processing in the first priority order determination circuit 32 will be described.

Here, the access request signals 310b and 310e sent from the first integrated access request generation circuit 310 are received, and
The priority is selected only when the destination second priority determining devices of the two signals are the same. Therefore, in the first priority determination circuit, two priority determination means are provided for each transmission destination, and priority control is performed based on a predetermined priority, and one or two selected access requests are determined. An access request selection address signal 32b indicating an address is transmitted to the access request return control circuit 35 and the access request transmission control circuit 34, and an access group information signal 32c corresponding to the access request selection control signal 32b and an access request issuer information signal 32d and access group information signal 32
e, one or both of the two sets of the access request issuer information signal 32f are sent to the access request transmission control circuit 34.
Send to

However, the two second destinations of the destination of the first priority determination device
If the access request transmission permission signals 45Aa and 45Ba described later are not detected by the first priority determination circuit 32 from the priority determination device, the access request signals 310b and 310e are not taken in by the two priority determination means. .

If the access request is for data storage, the storage data selection circuit 33 sends a storage data selection information signal 32i corresponding to the access request signal output from the two priority order determination circuits. Storage data selection circuit 33
In the information signal 32i, one of two signals of a data storage identification information signal 33a, a storage data signal 33b, a data storage identification information signal 33c, and a storage data signal 33d corresponding to the access request signals 310b and 310e. Alternatively, both are transmitted to the access request transmission control circuit 34.

In the access request transmission control circuit 34, the received access request selection address signal 32b responds to the access request signal 3 shown as a part of the access request selection address signal 32b.
10b, an access group information signal 32c corresponding to the address request signal, an access request source information signal 32d, and a data storage identification information signal 33a and a storage data signal 33 if the access request is data storage.
b, and the same access request signal as the access request signal 310e indicated as a part of the access request selection address signal 32b, the access group information signal 32e corresponding to the access request signal, the access request source information signal 32f, the access Data storage identification information signal if the request is for data storage
Either one or both of the two signals 33c and the stored data signal 33d are sent to the corresponding second priority determining device.

Further, the first priority determining device detects the access request signal selected by the first priority determining circuit 32 based on the access request selection address signal 32b, and issues a corresponding issuing source access request control device and flip-flops 30B to 30F. Or to the flip-flops 30H to 30L, for example, when the access request signal 310b is selected, the access request transmission permission signal
35Aa, and sends an access request acceptance signal 35e.

By this processing, for example, the access request signal 24Aa is set to the access request acceptance permission state, and the next access request is temporally set in the flip-flop 30B.

On the other hand, the issuer access request control device enters an access request transmission permission state, and transmits the next access request.

Next, when the integrated access request generation in the first integrated access request generation circuit 310 is detected for the access request signal 30Ba, the time when the first integrated access request generation is detected for the access group information signal 30Ca is described. An example is described.

First, the access request signal 30Ba waits for the appearance of an access request signal 30Ha for generating an integrated access request with the access request signal 30Ba based on the access group information signal 30Ia.

Therefore, the access request signal 30Ha is
When the access request is not an access request for generating an integrated access request with Ba, the first integrated access request generation circuit 310 sends the access request signal 30Ha as it is to the first priority determination circuit 32 as the access request signal 310e. Sends an access request to the second priority determining device.

When it is detected that the access request signal 30Ha is an access request for generating an integrated access request, the two access request signals 30Ba and 30Ha are converted into one access request signal 31Ha.
0b, the access group information signal 310c in which part of the information corresponding to the integrated access request in the access group information is invalidated, and two different issuer access request control device information are combined into one piece of information. The combined issuer access request control device information signal 310d is used as a first priority determination circuit.
Send to 32.

Conversely, when the integrated access request generation is first detected by the first integrated access request generation circuit 310 with respect to the access request signal 30Ha, the access request signal 30Ba is transmitted to the access request signal 30Ba similarly to the processing for the access request signal 30Ba. signal
It waits for an access request to generate an integrated access request with 30Ha, and generates an integrated access request 310b.

At this time, from the first integrated access request generation circuit 310,
An integrated access request identification signal 310a for identifying that the access request 310b is an integrated access request is sent to the first priority determination circuit 32.

The two access request signals 30Ba and 30Ha to be integrated
When the access request valid identification information included in the access group information signals 30Ca and 30Ia corresponding to the above is detected that all the access requests satisfying the storage processing unit are invalid, the integrated access rejection detection signal 310h is accepted as the access request. Sent to the control circuit 35 to generate a synthesized data generation instruction signal
310i to the first stored data synthesizing circuit 311;
The transmission of the two access request signals to the first priority determination circuit is both suppressed. The access request reception control circuit 35 detects the integrated access disable detection signal 310h, and combines the access request source information signals 30Da and 30Ja received via the flip-flops 30D and 30J into one access request source information. The signal 35Ad and the valid access signal 35Ac are both sent to the valid access return control circuit (FIG. 7) in the first priority determining device.

If the access request is for storing data,
The storage data 30Fa and the storage data 30La received by the first storage data synthesis circuit 311 are sent to the first storage data synthesis circuit 311.
Then, a combined data generation instruction signal 310i indicating the combination with is transmitted. In the first stored data synthesizing circuit 311, the instruction signal 310 i
, The composite data of the storage data 30Fa and 30La is generated according to the respective data storage identification information 30Ea and 30Ka.

At this time, further, the data storage identification information 30Ea and the data storage identification information corresponding to the synthesized data generated by 30Ka.
311a is generated, and both are sent to the storage data selection circuit 33.

In the first priority determination circuit 32, the integrated access request 31
The integrated access request 310b is transmitted as an access request selection address signal 32b into the access request transmission control circuit 34 upon detection of, for example, the access request transmission permission signal 45Aa transmitted from the second priority determination device of the transmission destination of 0b. Further, when the access request is data storage, the storage data selection for selecting the combined data 311b and the data storage identification information 311a corresponding to the integrated access request whose priority is selected from the first priority determination circuit 32. The information 32i is sent. In the storage data selection circuit 33, the storage data selection information
32i, the composite data 311b and the stored data identification information 311
a is transmitted to the access request transmission control circuit 34.

The access request transmission control circuit 34 determines the destination second priority determining device based on the address of the access request selection address signal 32b, and determines the access request selection address signal 32b received from the first priority determination circuit 32, Group information signal 32c, access request issuer information signal 3
2d, if the access request is storage of data,
The combined data signal 33b and the data storage identification information signal 33a are both transmitted.

In this case, the first priority determination circuit 32 sends the integrated access request identification signal 32a indicating that the access request whose priority is selected is the integrated access request to the access request reception control circuit 35. Access request reception control circuit
In 35, upon detection of the integrated access request selection detection signal 32a, access request acceptance permission signals 35e and 35f are sent to the flip-flops 30B to 30F and 30H to 30L, and two issuer access request control signals are sent. The access request transmission permission signals 35Aa and 35Ab are transmitted to the signal.

By this processing, the next access request in time, for example,
Access request signal 24Ba, access group information signal 24B
b, if the access request issuer information signal 24Bc indicates that the access request is data storage, the data storage identification information signal
Both 24Bd and the stored data signal 24Be enter the access request accepting state and are set in each of the flip-flops 30H to 30L. On the other hand, the issuing source access request control device enters the access request sending permission state and sends the next access request. Can be performed.

Next, the state of the processing of the second priority determining device is shown in FIG. The components of the second priority order determining device are the same as those of the device of FIG. 3, but the reference numerals of the corresponding components have a maximum digit of "4".

Here, the same processing as that of the above-described first priority determining device is performed on the access request transmitted from the two first priority determining devices, and the access request is transmitted to the third priority determining device.

Next, the state of the processing in the third priority determining device is shown in FIG. Although the components of this device also correspond to those in FIG. 3, the reference numeral is set to the maximum digit "5".

Although the contents of the processing are almost the same as those of the first and second priority determining devices, the contents of the processing in the third priority determining circuit 52 are partially different.

That is, the third priority determination circuit 52 is connected corresponding to each storage bank, and the access request with the priority is accessed as it is. However, also in this case, the access request is not taken into the priority determination circuit 52 unless the access request permission signal 14Aa is detected from the storage bank.

The above is the flow of processing up to the access to the storage device. Next, the process of returning a valid access signal to the issuing access request control device will be described with reference to FIGS.

As shown in FIG. 6, a valid access signal 14Aa, an access request issuer information signal 14Ab, and a read data signal 14Ac are also transmitted from the storage bank to the valid access return control circuit if the access request is for reading data. Sent to 60A.

The valid access return control circuit 60A determines whether the corresponding third integrated access request generation circuit has generated an integrated access request for the valid access signal 14Aa based on the access request issuer information signal 14Ab.

First, when it is not detected by the determination that the integrated access request is being generated, the access request issuer information signal 14Ab determines whether the valid access return control circuit 61A of the second priority determining device at the return destination is different from the valid access return control circuit 61A. 2 Select one of the valid access return control circuits 61C of the priority order determining device. For example, if the valid access return control circuit 61A is selected, the valid access signal 60Aa, the access request issuer information signal 60Ab, and if the access request is a data read, the read data signal 60Ac is also included in the valid access return control circuit 61A. Returned to 61A.

When the third integrated access request generation circuit detects that the integrated access request is generated by the determination, the return destination is different from the valid access return control circuit 61A of the second priority order determination device. Both of the valid access return control circuits 61C of the second priority determining device are selected, and the second priority determining device of two different return destinations is selected in response to the valid access signals 60Aa and 60Ad and the access request source information signal 14Ab. If the access request source information signals 60Ab and 60Ae generated in accordance with the above, and the access request is a data read, both the read data signals 60Ac and 60Af are also transmitted to the valid access return control circuit 61A of the second priority order determination device. , Effective access return control circuit 61C of a different second priority determining device
Return to

At this time, when the third integrated access request generation circuit detects that all the access requests satisfying the storage processing unit are invalid access requests by the valid access signal 54Ac, the access transmitted together with the detection signal is transmitted. The valid access return control circuit 61 is issued by the request issuer information signal 54Ad.
The valid access signals 60Aa and 60Ad and the access request issuer information signals 60Ab and 60Ae are returned to both A and 61C.

The same applies to the valid access return control circuit 60B.

Next, regarding the processing in the second priority determining device, as shown in FIG. 7, for example, the valid access return control circuit 61A of the second priority determining device also controls the validity of the third priority determining device. Valid access signal 60Aa returned from access return control circuit 60A, access request issuer information signal
60Ab, if the access request is a data read, the read data signal 60Ac is also the first data selected based on the access request issuer information signal 60Ab, as in the valid access return control circuit 60A of the third priority determining device. For the valid access return control circuits 70A to 70B of the priority order determination device, valid access signals 60Ab to 61Ae and an access request issuer information signal 61
Aa to 61Ad, if the access request is for reading data,
One or both of the read data signals 61Ac to 61Af are returned.

At this time, if the valid access signal 45Ac detects that all access requests satisfying the storage processing unit are invalid access requests in the second integrated access request generation circuit, the access transmitted together with the detection signal is detected. Based on the request issuer information 45Ad, both the valid access signals 61Aa to 61Ad and the access request issuer information signals 61Ab to 61Ae are returned to the valid access return control circuits 70A to 70B.

Further, as shown in FIG. 8, the same process is performed in the valid access return control circuit of the first priority determining device which has received the valid access signal from the second priority determining device, and the corresponding access request control device is sent to the corresponding access request control device. On the other hand, a valid access signal and, if the access request is a data read, a read data signal are also transmitted. However, the access request issuing source information signal from the first priority determining device is not returned from the first priority determining device due to the determination of the valid access signal return destination access request control device. .

Next, processing in the access request control device will be described with reference to FIG.

For example, when returning from the valid access return control circuit 70A of the first priority order determination device to the access request control device 80, the valid access signal 70Aa, and further, if the access request is data reading, the read data signal 70Ab is also returned. The valid access signal 70Aa is returned to the access request control circuit 801 via the OR circuit 803, and the read data signal 70Ab is
It is returned to the read data return control circuit 800.

In the access group information generation circuit 802, the start address of the representative access request that generated the integrated access request by detecting the valid access signal 803a, the address of the access request corresponding to the valid access signal 70Aa, and the access request address increment Generating information indicating a corresponding portion of the read data corresponding to the access request by the value;
The information signal 802a is read out and sent to the data return control circuit 800.

In the read data return control circuit 800, the information signal 802a
Thus, only the valid portion of the received read data signal 70Ab is selected, and the data signal 800a is transmitted to the access request control circuit 801.

In the access request control circuit 801, the valid access signal 803
By detecting a, the received read data signal 800a can be captured.

When an integrated access request is generated by the first priority order determination device 11A corresponding to the valid access return control circuit 70A, the valid access signal 70Aa is set to the read data signal 70Ab if the access request is for reading data. At the same time, when the access request control device 80 is returned, the effective access signal 62Ac is returned to the access request control device 81 together with the read data signal 62Ad if the access request is data reading. The processing described above is performed by the control devices 80 and 81.

The same applies to the valid access return control circuit 70B.

Next, the processing of generating the integrated access request when the invalid access request address compression instruction is detected will be described again in the second section.
This will be described with reference to the drawings.

In the invalid access request address compression instruction, addresses are assigned so as to be continuous only for access requests that are valid according to the access request valid identification information.

For example, in the case of the access request control device 24A, when the detection signal 20a of the invalid access request address compression instruction is received by the access group information generation circuit 241, the access request valid identification information signal 24a sent from the access request valid identification information 24 Then, it is determined whether the access request signal 240a is valid or invalid.

 Next, each case will be described.

If it is determined to be invalid, the access group information generation circuit 241 returns an access request end signal 241h to the access request control circuit, and ends the processing.

If it is determined to be valid, the access request valid identification information signal
24a, information on the number of valid access requests among all access requests issued before the generated access request, access request valid identification information on all access requests issued at the same time, and access request With the start address information signal 21a and the access request increment value information signal 22a, an address is assigned again only for a valid access request.

Next, the access request control device to which the access request is issued is recognized by the access request effective identification information of all access requests issued at the same time included in the access request effective identification information signal 24a. Address information signal 21a, access request increment value information signal 2
2a, connection form information signal 23a, and the access request signal 2
According to 40a, for an access request issued at the same time, the stage number of the priority determining device that generates the integrated access request and the number of access requests for generating the integrated access request in the priority determining device are obtained, and the access group is determined. Information.

The access group information signal 241g is sent to the access request issuance control circuit 243 together with the access request signal 241e and the access request issuer information signal 240c, and is processed in the same manner as when no invalid access request address compression instruction is detected. . Also, when the access request is data storage, processing is performed in the same manner as when no invalid access request address compression instruction is detected.

Next, a process of generating an integrated access request will be described with an example.

For the access request control devices 10A to 10D shown in FIG.
It is assumed that access requests having consecutive addresses are sequentially allocated, and an integrated access request is generated by four access requests issued from each access request control device. For example, in the first priority order determination device 11A, the path 10A
a, for two access requests sent by 10Ba,
An integrated access request is generated, and among the access group information, information corresponding to the integrated access request generation in the first priority order determining device 11A is invalidated, and together with the integrated access request, the information is sent to the second priority order determining device 12A. It is sent out by the path 11Aa.

On the other hand, the first priority order determination device 11C also generates an integrated access request for the two access requests transmitted from the access request control devices 10C and 10D via the paths 10Ca and 10Da, and Is invalidated and sent to the second priority determining device 12A via the path 11Ca.

In the second priority determining device 12A, the path 11Aa and the path 11C
a) receives the two integrated access requests sent by a, generates an integrated access request corresponding to the four access requests, invalidates all bits of the same access group information, and sets a third integrated access request together with the completed integrated access request. It is sent to the priority order determining device 13A.

In the third priority determining device 13A, when a priority is selected from the access request transmitted from the second priority determining device 12C, the priority is transmitted to the storage bank 14A.

At this time, the process of returning the valid access signal to the issuer access request control devices 10A to 10D will be described.

The valid access signal return control device of the third priority determining device 13A responds to the valid access signal returned from the storage bank 14A by using the source access request control device information returned together with the valid access signal returned from the storage bank 14A. 12A and 12C
12A, and returns the valid access signal.
In the second priority determining device 12A, the third priority determining device 1
In response to the valid access signal returned from 3A, both of the return destination first priority determination devices 11A and 11C are selected based on the issuer access request control device information returned together, and the valid access signal is returned.

For example, in the first priority determining device 11A, in response to the valid access signal returned from the second priority determining device 12A, the return destination access request control devices 10A and 10B are used according to the source access request control device information returned together. Select both and invalidate the issuer access request controller information,
I will send it back.

On the other hand, the first priority order determination device 11C also responds to the valid access signal returned from the second priority order determination device 12A.
The same processing is performed, and the valid access signal is returned to both of the access request control devices 10C and 10D.

The access request control devices 10A, 10B, 10G, 1 shown in FIG.
For 0H, the address is the access request control device 10G, 10H,
In the case where continuous access requests are allocated in the order of 10A and 10B, and an integrated access request is generated by four access requests issued from each access request control device, the first
The priority order determining devices 11A and 11G generate the integrated access request as described above by the access requests sent from the access request control devices 10A and 10B and the access requests sent from the access request control devices 10G and 10H, respectively. Send out.

In the second priority determining devices 12A and 12C, based on the access group information, the second integrated access request generating circuit of the second priority determining device detects that the integrated access request is not generated, and the second priority determining device determines the second priority determining device. The circuit sends out. When the priority is selected by the second priority determining circuit, the third priority determining device 13A generates an integrated access request corresponding to the four access requests, and
Send to A.

At this time, the process of returning the valid access signal to the issuer access request control devices 10A, 10B, 10G, and 10H will be described.

The valid access signal return control device of the third priority determining device 13A responds to the valid access signal returned from the storage bank 14A by using the source access request control device information returned together with the valid access signal returned from the storage bank 14A. And 12C, and returns the valid access signal.

For example, in the second priority determining device 12A, in response to the valid access signal returned from the third priority determining device 13A, the return destination first priority determining device 11A is used based on the issuer access request control device information returned together. And 11C out of 11
A is selected and the valid access signal is returned.

In the first priority determining device 11A, both of the return destination access request control devices 10A and 10B are controlled by the issuer access request control device returned together with the valid access signal returned from the second priority determining device 12A. Select and invalidate the issuer access request control device information and send it back.

On the other hand, the second priority determining device 12C also responds to the valid access signal returned from the third priority determining device 13A by
Based on the issuer access request control device information returned together, 11G is selected from the first priority determination devices 11E and 11G, and the valid access signal is returned.

In the first priority determination device 11G, the effective access signal returned from the second priority determination device 12C is processed in the same manner as the first priority determination device 11A, and both the access request control devices 10G and 10H perform The valid access signal is returned.

In the above-described embodiment, each priority determining device receives an access request from two access request control devices and controls the priority. However, as shown in FIG. It is also possible to change to receive an access request from (4 in the figure).

[Effects of the Invention] As described above, according to the present invention, access requests for accessing one storage bank from a plurality of access request control devices can be collectively processed by a multi-stage priority order determination device. Thus, contention of storage banks between access requests can be reduced, and access request processing of storage devices can be greatly improved. Further, the priority order determining device at each stage can be realized with a relatively simple logical configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a storage control device showing an embodiment of the present invention, FIG. 2 is a configuration diagram of an access request control device in FIG. 1, and FIG. 3 is a configuration diagram of a first priority determination device in FIG. FIG. 4 is a block diagram of the second priority determining device in FIG. 1, FIG. 5 is a block diagram of the third priority determining device in FIG. 1, and FIG. FIG. 7 is an explanatory diagram of returning an effective access signal to the second priority determining device. FIG. 7 is an explanatory diagram of returning an effective access signal from the second priority determining device to the first priority determining device.
FIG. 8 is an explanatory diagram of a case where a valid access signal and read data are returned from the first priority order determining device to the access request control device, and FIG. 9 is a configuration diagram of a storage control device showing another embodiment of the present invention. is there. 10A to 10H ... access request control device, 11A to 11H ... first
Priority determining devices, 12A to 12H... Second priority determining devices, 13A to 13H... Third priority determining devices,..., Storage devices, 14A to 14H.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Shigeko Yazawa 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa factory (56) References JP-A-1-183779 (JP, A) JP-A-63- 175970 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 12/06

Claims (3)

(57) [Claims] 1. A storage device comprising a plurality of storage units that can be accessed independently, a plurality of access request control devices accessing the storage device, and an access request issued by the plurality of access request control devices. A storage controller that determines a priority order and sends the access request to the target storage unit. A computer system comprising: a plurality of access requests having a data width smaller than an access processing unit of the storage device; A storage control method for integrating as a request, wherein the storage control device is configured by a plurality of stages of priority order determination means, wherein the access request control device includes: a start address of a plurality of access requests to be integrated; Address increment value, and connection form information between the access request control device and the plurality of stages of priority determination means. In addition, the access request information to be integrated is added to the access request to be integrated, by adding the stage information indicating which stage of priority determination means should be used to integrate the access requests issued by itself and the access group information including the number of access requests to be integrated. Each stage of the priority determining means of the storage control device, when receiving an access request having access group information designating itself as an access integration location, the access of the partner to be integrated A storage control method characterized in that access requests are integrated after a request arrives. 2. The method according to claim 2, wherein the storage device addresses corresponding to the access requests not to be accessed are compressed based on the access request valid identification information indicating whether or not each access request accesses the storage device. 2. The storage control method according to claim 1, further comprising means for detecting processing of an instruction for generating an address, wherein upon detecting the instruction, the access request valid identification information is also included in the access group information. 3. The method according to claim 1, wherein each stage of said priority order determining means, when integrating some access requests to the same access processing unit, invalidates an access group information part relating to said part. 2. The method according to claim 1, wherein when information is added to an access request to a subsequent stage and all access requests to the same access processing unit are integrated, all access group information of the access request is invalidated. Storage control method.