JP2826490B2 - Vector data processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a vector data processing apparatus, and more particularly to a vector data processing apparatus for determining whether vector data processing is valid or invalid by mask data associated with each vector data.

[0002]

2. Description of the Related Art As a conventional vector data processing apparatus of this type, there is a "vector processing method for conditional statements" disclosed in Japanese Patent Laid-Open No. 60-008942. This example describes a vector processing method that counts the number of true or false masks to be generated when executing a vector mask generation instruction, and selects the optimal execution method of a vector instruction with a mask by referring to this number. It has been disclosed.

[0003] However, the mask data operates in association with each element of the vector data as when used in a vector instruction with a mask, and also transfers data between a main memory or a scalar data processing unit and the mask memory. Alternatively, the operation may be performed independently of vector data, such as operation / transfer between a mask memory and a mask register.

Conventionally, in the instructions corresponding to the above-described operations, in the mask data updating / sending operation, a constant value is defined for the number of processing elements per cycle for each instruction. For example, in the above-described vector mask generation instruction and the vector instruction with mask, the number of processing elements in one cycle is determined by the vector data 1 supplied from the vector register.
It is often determined uniquely in association with the number of processing elements per cycle. On the other hand, when a mask data load instruction from a scalar register or a data transfer instruction between a mask register and a mask memory already has all the elements of the mask data at the transfer source, if these instructions alone are used, it is considered that each instruction alone requires one cycle. The processing speed is faster if the number of write elements to the mask register or mask memory is set larger,
For example, when this instruction is issued between two vector instructions with mask, if it is not guaranteed that the mask data to be read by the preceding vector instruction with mask is not overwritten by the next instruction, the instruction It cannot be issued. Therefore, a mask load instruction or a mask register
As the number of processing elements per cycle of the data transfer instruction between mask memories increases, the issuance of these instructions is postponed, and the issuance of subsequent masked vector instructions is delayed accordingly.

As an example of such a case, the operation of a conventional vector data processing apparatus having one vector pipe and a maximum vector length of 32 that can be processed by one instruction in the vector pipe will be described. For simplicity, it is assumed that the data handled in the vector data processing device is 32 bits, and the vector instruction processes one element per cycle. It is also assumed that the mask control unit has a mask memory composed of a 32-bit mask register and a RAM of 32 bits × 8 words and 1 read port. In the mask data transfer instruction from the mask memory to the mask register, It is assumed that a mask update process of 32 elements (32 bits) is performed per cycle.

Referring to the time chart of FIG. 4, a processing vector length 32, a vector instruction with mask (VMA),
An operation in which a data transfer instruction (MVMC) from a mask memory to a mask register and a vector instruction with mask (VMB) are issued in this order will be described. By the preceding vector operation instruction with mask (VMA), one element of mask data is sent out per cycle from the mask register. When a mask data transfer instruction (MVMC) from the mask memory to the mask register is issued, the mask data of 32 elements (32 bits) is rewritten in one cycle, so that the MVMC instruction is issued at least 29 cycles. have to wait. Subsequently, even if a subsequent masked vector instruction (VMB) is issued two cycles after waiting for writing to the mask register by the preceding MVMC instruction, even if the preceding masked vector instruction VMA is issued and the subsequent masked vector instruction VMB is issued. A total of 66 cycles are required until the mask transmission is completed.

[0007] The total number of cycles can be reduced by setting the number of elements per cycle in the mask data load instruction smaller. For example, if the number of processing elements per cycle is 8, the total is 63 cycles, if it is 4, the total is 59 cycles, and if it is 1, the processing is completed in a total of 37 cycles as shown in the time chart of FIG. Recognize. However, the number of processing cycles of the mask data load instruction itself increases in the opposite direction. Therefore, when instructions capable of processing multiple elements of the mask data at a time are consecutive, the total number of processing elements per cycle is larger than that when the number of processing elements per cycle is large. The number of cycles increases.

[0008] Actually, MVM in one cycle one element processing operation
Assuming that C has been issued before the VMA-MVMC-VMB instruction described above, as shown in FIG.
Issue of MC must wait 32 cycles from the first MVMC. In the above-described conventional example, the timing is set to the write operation (one element per cycle) to the mask register by instructing data read from the memory for 32 cycles by the read instruction section of the mask memory. It is also possible to provide a register or the like for holding 32 cycle data in the lower stage without performing such an operation in the mask memory read unit, but in the end, it is necessary to wait for the same degree of issuance due to busy writing to the register unit. In order to avoid this write busy, data can be held in a buffer of 32 stages, but a considerable increase in hardware is expected.

[0009]

In this conventional vector data processing apparatus, a predetermined value of the number of processing elements per cycle is specified for each mask update / transmission instruction operable independently of vector data. Also, there is a pattern in which the processing speed is reduced depending on the combination of instructions issued before and after when the number of processing elements per cycle is small or large. The choice is made to either accept the slowdown or take a value in between and give up the high-speed processing in exchange for avoiding the slowdown in a certain processing. There is a problem that it is limited.

The present invention focuses on this point and improves the processing speed of an instruction sequence including a mask update / transmission instruction.

[0011]

An apparatus according to the present invention holds mask data attached to vector data and used for discriminating validity / invalidity of the vector data processing, and controls updating and transmission of the mask data. In a vector data processing device having a mask control unit, a cycle element number determining means for determining the number of elements of the mask data to be updated / transmitted in one cycle, and a mask update / transmission according to an instruction from the cycle element number determining means A mask instruction operation switching means for switching an operation by an instruction is provided.

[0012]

FIG. 1 is a block diagram showing a first embodiment of a vector data processing device according to the present invention, which comprises an instruction issuing unit 1, a mask control unit 2, and a vector data processing unit 3. In this vector data processing device, 32
It is assumed that bit data is handled, and the maximum vector length that can be processed by the vector data processing unit 3 is 32.

Referring to FIG. 1, an instruction stack 10 and a cycle element number determining means 12
There is an instruction issue timing control unit 11 including The instruction codes are sequentially read from the instruction stack 10 in the order of issue. The instruction issuance timing control unit 11 receives the code of the next instruction from the instruction stack 10 and refers to the mask control unit 2, the vector data processing unit 3 or other blocks (not shown) that are busy or the instruction execution processing time. An issue start signal is transmitted to each unit by appropriately managing the inter-issue interval.

The cycle element number determination means 12 manages the currently executed mask update / transmission instruction and the number of processing elements per cycle in the instruction, and stores the instruction stack 10
If the code of the next instruction received from the CPU indicates a mask update / transmission instruction, the number of mask processing elements per cycle in the next instruction is determined so as to minimize the issue interval between the previous instruction and the next instruction. .

The mask control unit 2 includes a mask memory 21
, A mask register 22, a mask instruction operation switching means 20, a read register 23, and two read mask registers 24 and 25. The mask memory 21 is 3
It is assumed that the mask register 22 is a 2-bit × 8-word RAM, and the mask register 22 is a 32-bit register. The mask instruction operation switching means 20 receives, from the instruction issuance control unit 1, a start instruction of a mask update / transmission instruction and an instruction of the number of mask processing elements per cycle in the instruction, and reads the mask memory 21 and the mask register 22 or Switches the write operation. Further, the mask register 22 stores the two arithmetic units 4 in the vector data processing unit 3.
Read mask registers 2 corresponding to 0 and 41 respectively
The provision of 4, 25 enables independent reading of mask data.

Next, in order to explain this embodiment more specifically, in the vector data processing device 3, the number of mask data processing elements per cycle can be selected from two, 1 and 32. The operation of each unit when an instruction is issued in the following order will be described. 1. 1. Data transfer from mask memory (word 0) to mask register: MVMC 2. Vector operation with mask A: VMA 3. Data transfer from mask memory (word 1) to mask register: MVMC Masked Vector Operation B: VMB In the instruction issuance control unit 1, instruction codes are sequentially read from the instruction stack 10. When the code of the MVMC instruction is input from the instruction stack 10 first, the cycle element number determination means 12 refers to the execution status of the preceding instruction held in the instruction Is confirmed, and the number of elements per cycle of the MVMC instruction is determined to be 32.

The instruction issuance timing control means 11
A start signal of the MVM instruction, a read address of the mask memory 21, etc., considering whether the circuit used in the VMC instruction is in use by an earlier instruction, whether the data in the mask memory 21 as a source is ready, etc. The accompanying information necessary for the instruction execution and the number of cycle elements (32) determined by the cycle element number determination means 12 are notified to the mask control unit 2.

The mask control unit 2 receives the above-mentioned signal from the instruction issuance control unit 1 and performs a mask instruction operation switching unit 20.
Take in. Since the number of processing elements per cycle notified from the cycle element number determining means 12 is 32,
The mask instruction operation switching means 20 holds the read enable and read address (0) of the mask memory 21 for one cycle. The mask data held in word 0 of the mask memory 21 is read by the read enable and read address (0), and is set in the read register 23.

The mask instruction operation switching means 20 instructs all the bits of the mask register 22 to take in the mask data from the read register 23 for one cycle with two cycles delay from the read timing of the mask memory 21. Writes all 32 bits of the mask data of the read register 23 at a corresponding bit position at a time.

Next, the instruction issuance timing control unit 12
A VMA instruction code is input from the instruction stack 10, and in consideration of a write timing of a preceding MVM instruction to the mask register 22, a start signal of the VMA instruction and information accompanying the VMA instruction are transmitted to the mask control unit 2 and the vector data processing unit. Notify 3. The VMA instruction uses the vector register 30
According to the number of processing elements per cycle of vector data read from .about.35 and sequentially processed (here, one element per cycle), the number of cycle processing elements of mask data is also uniquely defined as one element per cycle. You.

When the mask control unit 2 receives the VMA instruction start signal and the accompanying information from the instruction issuance control unit 1, the mask data is written from the bit 0 to the first cycle by the mask register 22 in which all the 32 bits have been written. Read one bit at a time, read mask register 24
And then sends it to the vector data processing unit 3.

When the vector data processing unit 3 receives the start signal of the VMA instruction and the accompanying signal from the instruction issuance control unit 1, it reads the vector data from the vector registers 30 and 31 one element at a time in one cycle. After being set in the data registers 36 and 37, the data is sent to the arithmetic unit 40. The arithmetic unit 40 inputs the mask data sent one bit at a time from the read mask register 24 of the mask control unit 2 together with the two vector data, sequentially performs the arithmetic processing, and sends the operation result data to the vector register 32. Then, in the vector register 32, the operation result data is sequentially written from word 0.

The instruction issuance timing control unit 11 of the instruction issuance control unit 1 holds information that the VMA instruction is continuing the processing of one element per cycle.
When the next MVMC instruction code is transferred from the instruction stack 10 based on this information, the cycle element number determining means 1
2, the number of elements per cycle of this MVMC instruction is determined to be one.

The mask control unit 2 obtains a start signal of the MVMC instruction and instruction accompanying information from the instruction issuance control unit 1,
Since the instruction for the number of processing elements per cycle is 1, the mask instruction operation switching means 20 sets the mask memory 2
A read enable of 1 and a read address (0) are held for 32 cycles. The mask data held in word 0 of the mask memory 21 is read by the read enable and the read address (0), and the read register 23
Is set to That is, in the read register 23, 32
The same mask data is held during the cycle.

The mask instruction operation switching means 20 instructs bit 0 of the mask register 22 to take in mask data from bit 0 of the read register 23 two cycles later than the read timing of the mask memory 21. For the bit 1 of the register 22, an instruction to take in the mask data from the bit 1 of the read register 23 is issued, and then for the bit 1, an instruction is made to update the mask register one bit at a time per cycle. Thus, the mask register 22 writes 32 bits of the mask data of the read register 23 to the corresponding bit position over 32 cycles.

The instruction issuance timing control unit 11 of the instruction issuance control unit 1 holds information that the MVMC instruction is continuing the processing of one element per cycle. Therefore, when the next VMB instruction code is transferred from the instruction stack 10, the VMM instruction start signal and the instruction accompanying information are mask-controlled by taking into account the timing at which the writing of bit 0 of the mask register 22 is completed by the MVMC. Notify to the section 2 and the vector data processing section 3.
Similarly to the VMA instruction, the number of processing elements per cycle of the vector data read from the vector register and sequentially processed (here, one element per cycle) is also used for the VMB instruction. It is uniquely defined as one element per cycle.

When the mask control unit 2 receives the VMB instruction activation signal and the accompanying information from the instruction issuance control unit 1, the mask data is transferred from the bit 0 to the mask register 22 for one cycle from the mask register 22 in which all the 32 bits have already been written. Read one bit at a time and read mask register 25
And then sends it to the vector data processing unit 3.

When the vector data processing unit 3 receives the start signal of the VMB instruction and the accompanying signal from the instruction issuance control unit 1, it reads the vector data from the vector registers 33 and 34 one element at a time in one cycle, and reads each vector data. After setting in data registers 38 and 39,
It is sent to the arithmetic unit 41. The arithmetic unit 41 inputs the mask data sent one bit at a time from the read mask register 25 of the mask control unit 2 together with the two vector data, sequentially performs the arithmetic processing, and sends the operation result data to the vector register 35. And the vector register 35
Then, the operation result data is sequentially written from word 0.

FIG. 2 shows a time chart of the operation described above. As can be seen from FIG. 2, in this embodiment, the MVM
The process from issuing the first MVMC to transmitting the mask data of the VMB in a series of instruction processing of C-VMA-MVMC-VMB is realized in 39 cycles.

In the above embodiment, the mask memory 21 has a read port number of 1 and a memory capacity of 32 bits × 8 words.
In order to supply the mask data from the mask memory 21 to the mask register 22 one bit at a time in one cycle, the read address is held. Therefore, it is necessary to hold a read address for 32 cycles in order to supply 32 bits to the mask register 22, and after that, in order to activate a read instruction from the mask memory 21, the read operation must be canceled. . In order to avoid such a problem, it is conceivable to add a mask data holding register after the mask read or change the configuration of the mask memory 21. Mask memory 2
The configuration 1 can be changed, for example, by increasing the number of read ports or decreasing the number of bits in the memory to increase the number.

For example, FIG. 3 is a time chart when a mask memory is composed of four RAMs each having one read port and a memory capacity of 8 bits × 8 words, and each of the four RAMs can be independently read. In such an embodiment, the mask instruction operation switching means holds the read address of the first memory for eight cycles, then holds the read address of the second memory for eight cycles, and then holds the third and fourth memories. Data can be transmitted to the 1-bit mask register in one cycle, and the holding of the first read address is completed in eight cycles. Therefore, the subsequent read instruction from the mask memory is equivalent to eight cycles. Issuing is possible if you wait.

[0032]

As described above, in the present invention,
There are provided a cycle element number determining means for determining the number of mask data elements to be updated / transmitted in one cycle, and a mask instruction operation switching means for switching an operation by a mask update / transmission instruction in accordance with an instruction from the cycle element number determining means. As a result, the number of mask elements to be processed per cycle of the mask update / transmission instruction, which was conventionally constant, is made variable. As a result, the waiting time for instruction issuance between instructions, which has occurred because the number of processing mask elements per cycle is constant in the past, is reduced, and the processing time of a vector instruction sequence including a mask processing instruction is greatly shortened. Was.

In the processing of an instruction sequence such as MVMC-VMA-MVMC-VMB, comparing the time chart of FIG. 2 of the embodiment of the present invention with the time chart of FIG. It can be seen that the speed has been increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation example of the vector data processing device of FIG. 1;

FIG. 3 is a time chart showing an operation example of another embodiment of the present invention.

FIG. 4 shows a conventional vector data processing device,
It is a time chart at the time of performing a mask register update operation of 32 elements per cycle by MC instruction.

FIG. 5 shows a conventional vector data processing device,
9 is a time chart in the case of performing a one-cycle / one-element mask register update operation by an MC instruction.

FIG. 6 is a time chart in the case of performing a one-cycle / one-element mask register update operation with an MVMC instruction under another instruction sequence in the conventional vector data processing apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Instruction issue control part 2 Mask control part 3 Vector data processing part 10 Instruction stack 11 Instruction issue timing 12 Cycle element number determination means 20 Mask instruction operation switching means 21 Mask memory 22 Mask register 23 Read register 24, 25 Read mask register 30, 31, 32, 33, 34, 35 Vector register 36, 37, 38, 39 Read data register 40, 41 Arithmetic unit

Claims (2)

(57) [Claims] 1. A vector data processing apparatus having mask data attached to vector data and used for discriminating validity / invalidity of the vector data processing, and having a mask control unit for controlling update and transmission of the mask data. A cycle element number determining means for determining the number of elements of the mask data to be updated / transmitted in one cycle; and a mask instruction operation switching for switching an operation by a mask update / transmission instruction in accordance with an instruction from the cycle element number determining means. A vector data processing device comprising means. 2. A mask control unit comprising: a mask memory comprising k memories having a capacity of n bits.times.m words and holding the mask data, wherein said mask instruction operation switching means includes: 2. The vector according to claim 1, wherein the number of write address / read address holding cycles is switched by an instruction from said cycle element number determining means so that the maximum vector length that can be processed has a value of n × k. Data processing device.