JP2825073B2 - Inspection equipment for semiconductor integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus for a semiconductor integrated circuit, and more particularly to an inspection apparatus for a high-speed and multi-pin device having an improved mounting structure of a pin electronic card.

[0002]

2. Description of the Related Art Referring to FIG. 4, which shows a basic configuration of an inspection apparatus (hereinafter, referred to as a tester) for a general semiconductor integrated circuit (hereinafter, referred to as an IC) of this kind, a tester main body 12 is provided. , Tester CPU section 13, timing generation section 1
5, a format controller 18, a pattern memory 16, a level generator 14, and a level selector 17.

A test head 8 having a built-in pin electronics section 19 is connected by a cable from a tester main body, and is connected to an IC under test via an interface board.
(Hereinafter, referred to as DUT1).

Referring to FIG. 5, which shows a basic structure of a test head of a conventional tester, FIG. 5 (a) is a diagram showing a basic structure of a test head, in which I / O pins mounted in a test head 8 are shown. Pin Electronics Card (PE) 4
Then, a cable 7 for connecting this to the tester main body is connected via the connector 6.

On the other hand, the DUT 1 is mounted on an IC socket 2, and the IC socket is mounted on a test board 3. An electric signal to the DUT 1 and an electric signal from the DUT 1 are transmitted to a test head 8 via a test board and pogo pins 9.
Connected to the pin electronics card inside.

FIG. 5B is a schematic view of a pin electronics card, showing the internal structure of a general conventional pin electronics card. Referring to FIG. 1, one pin electronics card usually has a circuit for a plurality of pins. Referring to FIG. 6 showing a basic circuit configuration of the pin electronics card, the DUT
The input signal voltage VIH / VIL supplied to 1 is high (High) of the logic level of the input waveform from the driver circuit.
Level value (voltage value) at level / low level
And the output voltage VOH / VOL corresponds to a high-level / low-level threshold value (voltage value) when the comparator compares and determines the output waveform of the DUT 1.

[0007] In addition to these level information, a waveform is applied to the DUT 1 based on the waveform information sent from the format controller 18 and the contents of the pattern memory 16.
Alternatively, the waveform from DUT1 is compared and determined. Here, components that are not directly related to the present invention are omitted.

In general, a test head of a logic tester has a cylindrical shape, and a pin electronics card is radially mounted. This is because the length of time from the pin electronics card to the DUT 1 for each pin is equal-length wired. A pin electronics card usually has a circuit for a plurality of pins, for example, 8 I / Os per card.
If a circuit for the pins is configured, a tester for 512 pins is configured by mounting 64 pin electronics cards.

[0009]

In this conventional tester, the pin configuration of the input / output terminals of the tester is composed of I / O pins having both input and output for all pins. If the number of / O pins is 512, then D
It was possible to test only the input / output terminals of the UT1 up to 512 pins or less. However, in the actual DUT1, not all terminals are I / O pins.
The input / output terminals of the tester connected to pins other than the I / O pins of T1 are a driver,
Or only one of the comparators was used.

That is, the remaining driver and comparator are not used at all in this test program. On the other hand, contrary to the recent trend of increasing the number of IC pins,
There has been a problem that the tester is required to have more advanced functions, and simply increasing the number of input / output terminals of the tester makes the tester too expensive, so that the test cost cannot be met.

Also, by increasing the number of I / O pins,
The outer diameter of the test head has inevitably increased, and the transmission distance from the pin electronics card to the DUT 1 has increased.

Referring to FIG. 7A showing a schematic diagram of the DUT connection and FIG. 7B showing a time chart for each function from the basic tester to the device, the DUT 1
If the connection point of the tester is point a, the connection point of the driver circuit 10 is point b, the connection point of the comparator circuit 11 is point c, and the hatched waveform is the output waveform of the DUT1, Driver mode in which an input voltage is applied to the input pin of DUT1, comparator mode in which the output voltage output from the output pin of DUT1 is received by the comparator circuit 11 of the tester,
The input voltage is applied to the input / output pins of the UT 1 and the output voltage output from the input / output pins of the DUT 1 is output to the comparator circuit 11.
2 shows the waveforms at each point in each case of the I / O mode.

That is, FIG. 7B-601 shows the DUT
1 is an input pin, the tester is in the driver mode, and a physical delay time Tab occurs from the point b of the driver circuit 10 to the point a of the DUT 1 in the waveform. Similarly, FIG.
(B) At -602, the DUT 1 is an output pin and the tester is in the comparator mode, and a delay of time Tac occurs from the point a of the DUT 1 to the point c of the comparator circuit 11 until the waveform reaches. In the case of the waveforms 601 and 602 in the figure, the tester normally has a correction function, calculates the delay of the time Tab and Tac measured in advance, and calculates the DUT1.
At point a, a desired waveform is considered so that it can be output and compared.

FIGS. 7B-603 and 604 show DUs.
T1 is the input / output pin and the tester is in the I / O mode, and the switching between the waveforms 601 and 602 occurs. When switching from the driver mode to the comparator mode, the switching time inside the DUT 1 has priority. Conversely, when switching from the comparator mode to the driver mode, the time Tac until the output of the DUT 1 reaches the comparator circuit 11, the time Tio when the hardware switches from the comparator mode to the driver mode inside the tester, and the output of the driver circuit 10 Is DUT1
Is required to reach the time limit, and the sum of these becomes the rate limit.

The time Tio is usually 1.5 ns to 2 ns. When the distance from the DUT 1 to the pin electronics card increases, the times Tab and Tac inevitably increase, and the sum of the times Tio, Tab and Tac increases. High-speed test (100MHz or more)
There is also a problem that it is difficult to realize the above.

[0016]

A feature of the semiconductor integrated circuit testing apparatus of the present invention is that a semiconductor integrated circuit to be tested is mounted radially on a cylindrical test head built in the apparatus for testing a semiconductor integrated circuit. a pin electronics card for inputting and outputting signals to the driver only and comparator only and any combination of three types of pin electronics card group of drivers and comparators combined constitute, and mounting the pin electronics card group In the semiconductor integrated circuit inspection device incorporating the test head, the three types of cards are separated into two card groups , a card group dedicated to the driver and the comparator and a card group dedicated to the driver and the comparator. The pin electronics card which is also used as the driver and the comparator De group is to consist structure than other pin electronics card group is mounted in proximity to the tested semiconductor integrated circuit.

[0017] Each of the card group for the driver only and comparator dedicated is a structure L-shaped, wherein the arrangement position of the connector that implements the card group of the driver only and for comparator to the test head The position of the connector for mounting the driver and comparator card group on the test head is up and down 2
A connector for a card group dedicated to the driver and a comparator dedicated to the driver group and a card dedicated to the comparator are disposed so as to surround the test head support and parallel to the support, and the card serving as both the driver and the comparator is provided. connector group is disposed on the step on one of the two-stage structure comprising at right angles to and with the supports so as to surround the strut, of the driver and comparator serves to these connectors card group and said driver in a state where the dedicated and comparator only the card group were respectively mounted, said L-shaped said driver-only and comparator dedicated card group concave space of the driver Contact good <br/> beauty comparators and for the formation of the A card group can be mounted so as to surround the column.

The card group for both the driver and the comparator and the card group for the driver and the comparator are substantially identical in shape and structure, and the connection positions of the respective connectors are separated in the horizontal direction.
Has a heavy structure, connector of the card group of the driver contact and the comparator and for are arranged at right angles and relative to the supports so as to surround the test head support column, said driver
Connector of the card group for the dedicated and comparator dedicated is arranged at right angles to and the supports so as to surround the connector of the card group of the driver Contact and comparators and for the driver and comparator to these connectors in the state where the dual function card group and said driver only and comparator only the card group were respectively mounted, said as the card group of driver contact and the comparator and for surrounding the implemented outside to surround the strut driver card group of dedicated and comparator-only can also be implemented.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a cross-sectional view of the basic structure of the test head according to the first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along a cutting line XX ′ in the horizontal direction. FIG.

Referring to FIGS. 1A and 1B, the pin electronics card mounted in the test head 8 is a pin electronics card for I / O pins (P
E) 4 and dedicated pin electronics card (PE) 5 for driver (DRV) or comparator (CMP)
The pin electronics card for I / O pins is mounted near DUT1. The mounting structure of these pin electronics cards in the test head is an example in which they are mounted vertically in two stages.

FIG. 2 is a schematic diagram of each pin electronic card according to the embodiment of the present invention, and FIG.
FIG. 2 is a schematic diagram of a pin electronic card for pins,
2 shows the internal configuration of a pin electronics card for the / O pin. The basic configuration is not particularly different from the conventional pin electronics card for I / O pins. FIG. 2B is a schematic view of a pin electronics card dedicated to a comparator.
The internal configuration of a pin electronics card dedicated to a comparator is shown. FIG. 2C is a schematic diagram of the pin electronics card dedicated to the driver, and shows the internal configuration of the pin electronics card dedicated to the driver.

The pin electronics card 4 for I / O pins is located at the center of the test head and is arranged so as to minimize the distance from the DUT 1. On the other hand, the pin electronics card 5 dedicated to the comparator and dedicated to the driver
Is located under the pin electronics card 4 for I / O pins, forms a conductor pattern on a substrate having an L-shaped structure, and is arranged so that it can be connected to a test board by pogo pins from the upper surface of the substrate.

Each pin electronics card is shown in FIG.
As shown in (b), the pogo pin area of each pin electronics card is radially arranged in a double pattern.
A pin electronics card 4 for I / O pins is arranged on the inner side closer to T1, and a pin electronics card 5 dedicated to the comparator and driver is arranged outside the test head.

In the case where 64 sets (connecting connectors) for each pin electronics card are provided in the test head, one pin electronics card 4 for I / O pins is provided.
Assuming that the configuration of the electronic card 5 is 8 pins per board and the comparator dedicated and driver dedicated pins are 4 pins each, the maximum is 512 I / O pins and 25 dedicated comparator / driver dedicated pins.
Six pins can be used at a time. Therefore, when the composition ratio of the I / O pins, input pins, and output pins of the DUT 1 is equal to that of the above-described example of the tester pin configuration, the maximum is 1024 (= 51).
It can measure up to 2 + 256 × 2) pin DUT1.

The number of pins can be increased by increasing the number of mounting pins per board.

When each pin electronics card in the present invention is replaced with the time chart of FIG.
Both the time b and the time Tac in the comparator-dedicated pin electronics card 11 become longer, but neither causes a problem in measurement due to the correction function.

On the other hand, in the case of the pin electronics card 4 for the I / O pin, the transmission time Tab from the driver 10 to the DUT 1 and the transmission time Tac from the DUT 1 to the comparator 11 can be reduced as compared with the conventional case, so that the comparator in the I / O mode can be reduced. Driver open state (H
(i-impedance) setting time can also be reduced. This means that when the driver 10 → the comparator 11 → the driver 10 is used, the open state of the driver 10 can be shortened, and a higher frequency signal can be applied to the DUT 1.

Referring to FIG. 3 showing the basic structure of the test head according to the second embodiment of the present invention, the pin electronic card mounted in the test head 8
It is separated into a pin electronics card (PE) 4 for I / O pins and a pin electronics card (PE) 5 dedicated to a driver and a comparator, and the pin electronics card 4 for I / O pins is mounted at a position close to the DUT 1. The pin electronics card (PE) 5 dedicated to the driver and the comparator is an example mounted outside the pin electronics card 4 for I / O pins mounted inside (center side).

As in the first embodiment, the pin electronics card 4 for the I / O pin can shorten the transmission distance from the DUT 1 and shorten it. Further, the present embodiment has an advantage that it is not necessary to increase the thickness of the test head.

[0030]

As described above, the semiconductor integrated circuit inspection apparatus according to the present invention is a driver which is radially mounted on a cylindrical test head built in the inspection apparatus and inputs / outputs signals to / from the DUT. The three types of pin electronics cards, dedicated, dedicated to comparator, and driver / comparator, are separated into two card groups, one dedicated to driver and comparator, and the other dedicated to driver and comparator. Is designed to be mounted closer to the DUT than other pin electronics cards. Therefore, even if the wiring length between the DUT and these pin electronics cards is reduced and the number of pins is increased, Driver open state (Hi Impedance) can be kept to a minimum, it is possible to realize a high-frequency measurement, which contributes to improved reliability.

[Brief description of the drawings]

FIG. 1A is a schematic diagram of a basic structure of a test head according to a first embodiment. (B) is a horizontal sectional view of the test head taken along a cutting line XX ′.

FIG. 2A is a schematic diagram of a pin electronics card for I / O pins according to a second embodiment. (B) It is the schematic of the pin electronic card only for a comparator. (C) is a schematic diagram of a pin electronics card dedicated to a driver.

FIG. 3 is a schematic diagram of a basic structure of a test head according to a second embodiment.

FIG. 4 is a basic configuration block diagram of a conventional general tester.

FIG. 5A is a basic structural view of a conventional test head. (B) It is the schematic of the conventional pin electronics card.

FIG. 6 is a basic circuit configuration diagram of a conventional pin electronics card.

FIG. 7A is a schematic view of a conventional DUT connection. (B) It is a basic operation time chart of the conventional general tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 DUT 2 IC socket 3 Test board 4 Pin electronics card for I / O pins 5 Pin electronics card for driver or comparator 6 Connector 7 Cable 8 Test head 9 Pogo pin 10 Driver circuit 11 Comparator circuit 12 Tester body 13 Tester CPU section 14 Level Generation unit 15 Timing generation unit 16 Pattern memory unit 17 Level selection unit 18 Format control unit 19 Pin electronics unit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G01R 31/26 G01R 31/28 H01L 21/66

Claims (3)

(57) [Claims] 1. A pin electronics card in a by driver dedicated to be mounted radially on the test head in the form of a cylinder which is built in the apparatus for inspecting a semiconductor integrated circuit to input and output signals to the tested semiconductor integrated circuit , comparator dedicated, in the inspection apparatus of a semiconductor integrated circuit which incorporates the test head constructed by any combination of three types of pin electronics card group of drivers and comparators combined, and mounting the pin electronics card group, the 3 Types of cards are divided into two card groups , a card group dedicated to the driver and the comparator and a card group dedicated to the driver and the comparator, and the pin electronics card group also serving as the driver and the comparator is replaced with another pin electronics card. Said test than the group An inspection apparatus for a semiconductor integrated circuit having a structure mounted close to the semiconductor integrated circuit. The method according to claim 2, wherein each of the card group for the driver only and comparator dedicated <br/>, a structure of the L-shaped connector that implements the card group of the driver only and for comparator to the test head And a connector for mounting the driver and comparator card group on the test head has a two-stage structure in which the upper and lower connectors are arranged in two stages. Are arranged so as to surround the test head support and in parallel with the support, and the connector of the driver / comparator card group surrounds the support and is perpendicular to the support. disposed stepped on one of the two-stage structure Te, the driver and comparator serves to these connectors car In a state where the group and the driver only and comparator dedicated card group were respectively mounted,
Claim 1, L-shaped said driver only and card group of the space in which the recess of the card group to form driver Contact <br/> preliminary comparators and for the comparator dedicated for are mounted so as to surround said post An inspection apparatus for a semiconductor integrated circuit according to the above. 3. The driver / comparator-dedicated card group and the driver-dedicated / comparator-dedicated card group have substantially the same shape and structure, and the connection positions of the respective connectors are separated in the horizontal direction. has the structure, connector of the card group of the driver contact and the comparator and for are arranged at right angles and relative to the supports so as to surround the test head struts, the card group for the driver only and comparator dedicated connector is disposed at right angles to and the supports so as to surround the connector of the card group of the driver Contact and comparators and for the card group and said driver-only and the driver and comparator serves to these connectors in a state in which the card group of comparator dedicated to each implementation, the driver you Card group of comparator and and inspection apparatus of a semiconductor integrated circuit according to claim 1, wherein the card group is mounted for the driver only and comparator dedicated to surround the implemented outside to surround the strut.