JP2821121B2 - Display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device that controls the display of an image display device, and more particularly to a display control device that divides a display screen into a plurality of display areas and displays the display screen on a display. [Prior Art] Using a CRT display as a display device, information such as sentences (hereinafter referred to as text) and figures / images (hereinafter referred to as graphics) stored in a display memory (for example, a display memory using a dynamic memory). Is one of the important functions of the display processing device. Conventionally, in a display device of this type, information to be displayed on a screen such as text or graphics is stored in a display memory, and sequentially read out in synchronization with a scanning timing of the CRT, converted into a video signal, and converted into a video signal. The method of supplying it to is adopted. Recently, new media-related devices such as personal computers, word processors, and captain systems have spread to ordinary households. Furthermore, the importance of display processing as a man-machine interface, including in fields related to business such as OA devices, has been increasing. Are growing more and more,
At the same time, screen display forms have also been diversified. In particular, in a diversifying screen display mode, displaying a text screen or a graphic screen by dividing it into a plurality of areas can be achieved by simultaneously displaying sentences and graphs or pictures simultaneously, or by using a single console. It is an indispensable function for applications such as displaying the screen of each task at the same time when multiple tasks are executed, and a split screen display method that is easier to see and manages each screen is desired. . In such a background, when editing, such as insertion, deletion or change, from the keyboard or the like to the display information on the display screen, a cursor movable by a pointing device is displayed on the display screen to perform editing. It is common to specify and confirm the location, but recently, in addition to simply displaying the cursor pattern, the split screen currently being edited (hereinafter referred to as the active screen) is distinguished from other split screens. To make the editing location more clear,
There is also adopted a method in which only the active screen is displayed on the outer periphery thereof. FIG. 10 is a block diagram showing an example of a conventional display control device for distinguishing an active screen by the above-described border display. The microprocessor 1 controls the operation of the entire system via the system bus 2. The main memory 3 stores a program executed by the microprocessor 1 and processing data. The display memory 4 forms a frame memory for storing display data. The display control circuit 5 generates an address for the display memory 4 in synchronization with the display timing generated by itself, and outputs the read display data to the video signal generation circuit 6. The video signal generation circuit 6 converts the display data sent from the display control circuit 5 from parallel to serial to generate a serial video signal (video signal),
To supply. The cursor display circuit 8 displays a cursor pattern at predetermined X coordinate positions and Y coordinate positions on the display screen of the CRT 7 based on cursor movement instruction information input from the keyboard 9 via the peripheral control circuit 10. The peripheral control circuit 10 interfaces the keyboard 9 and the disk device 11 as external storage under the control of the microprocessor 1. In this device, the display of the divided screen is performed by allocating a display memory area (hereinafter, referred to as a frame buffer) corresponding to the screen of the CRT 7 on a one-to-one basis on the display memory 4 and dividing the display memory area into a plurality of memory areas. This can be realized by transferring desired display data to each of the memory areas into which the frame buffer is divided. At this time, as a method for easily recognizing which screen is the active screen among the displayed divided screens, conventionally, as shown in FIG. A memory area corresponding to the outer periphery of the frame is secured, and in this memory area, the display data of the border composed of control bits for designating display or non-display of the border display pattern is stored, and an active screen switching instruction input from the keyboard 9 is input. Then, as shown in FIG. 11 (b), a process of rewriting control bits of the display data of the border is performed. In FIG. 11, “1” indicates the border display pattern by setting the control bit to “1”, and “0” indicates the border display pattern by setting the control bit to “0”. Not mean. [Problems to be Solved by the Invention] In the conventional display control device for distinguishing the active screen by the border display described above, every time there is an instruction to switch the active screen, all the control bits of the display data of the corresponding border are displayed. Since it is necessary to execute the rewriting process, there is a problem that the processing data amount increases as the screen size or the number of divided screens increases, and the time required for rewriting the memory increases. For example, in the case where a screen of 80 characters × 25 lines is divided into two screens and displayed, the minimum instruction execution time is converted by a microprocessor instruction having a 1 μS, and the execution time required for rewriting one border data is 4.5 μS. Then, about 1.6 per screen
It takes mS processing time. Such an increase in the data rewriting time imposes a heavy burden on the original processing of the microprocessor and, at the same time, lowers the response speed of the screen. In addition, since it is necessary to allocate an area for displaying the border data on the display screen, for example, when a screen of 80 characters × 25 lines is divided into two screens and displayed, the outer periphery of the two screens requires 36
It is necessary to secure a display area for two characters, and the area for displaying the original data is limited by that much, so that the screen area of the display cannot be used effectively. On the other hand, as a display memory, there is a disadvantage that an extra memory other than the original display data for 362 characters needs to be provided. Furthermore, the discriminating effect of the border itself may not be high depending on the shape of the border data or the shape of the original display data, and the discrimination of the active screen is not always good. SUMMARY OF THE INVENTION The present invention has been made to solve such a problem in the conventional active screen display at the time of split screen display, and does not involve a large amount of memory access at the time of active screen switching. To provide a highly economical display control device which can reduce the burden on the user and improve the screen response speed, and which has high discrimination of the active screen and can efficiently use the screen area and the memory of the display. With the goal. [Means for Solving the Problems] A display control device according to the present invention includes a display memory for storing display information, a display timing generation circuit for generating a display timing signal of the display information on a display and a synchronization signal. In a display control device including a video signal generation circuit for converting the display information into a video signal by the display timing signal and the synchronization signal, and a cursor display circuit, the following flags and the display mode of the display information are changed. And means for rewriting the flag. The flag stores information that specifies the display mode of the display information, such as black-and-white inverted display, half-brightness display, and normal display, and the content thereof can be rewritten. The means for changing the display form of the display information, based on the output of the flag, when changing the display information to a video signal,
For example, the display mode of the display information is changed by performing logical processing on the video signal. Means for rewriting the flag, when the display screen of the display is composed of a plurality of divided screens, based on the display timing signal, the display position information of the cursor, and the area designation information of the divided screen, The display period of the active screen) and the display periods of the other divided screens are identified, and the flag is rewritten so that the contents of the flag are different between the two periods. [Operation] According to the present invention, the divided screen where the cursor is located can be designated based on the area designation information of the divided screen and the display position information of the cursor, and this screen is detected as the active screen. If the display timing signal indicates the display timing of the active screen, the flag is set, for example, and if the display timing signal indicates the display timing of another divided screen, the flag is reset, for example. Is done. When the display information is converted into a video signal, the display form of the display information is changed according to the value of the flag. As described above, according to the present invention, the display form of the active screen is made different from the display form of the other divided screens without changing the data in the display memory at all and changing the display form at the time of conversion to the video signal. I am trying to do it. Therefore, since no memory access is involved when the active screen is switched, the load on the processor can be reduced, and the response speed of the screen increases. Further, since the display form of the display information of the active screen changes over the entire active screen, the identifiability of the active screen is improved as compared with the conventional bordering method. Further, since the display memory does not particularly have data for identifying the active screen, the use efficiency of the display screen area and the display memory is increased. Example Next, an example of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a block diagram showing a display control apparatus according to a first embodiment of the present invention, in which an active screen is identified by reverse display of a screen. The microprocessor 21, which controls the entire system,
It is connected to a program memory 24 and a data memory 25 via an address bus 22 and a data bus 23. The program memory 24 stores a program executed by the microprocessor 21, and the data memory 25 stores the program
21 processing data is stored. The display timing generation circuit 26 synchronizes with a display timing signal generated by itself, and displays a display address REA, a raster address LUA, a dot clock DCK, a character clock CCK, a synchronization signal SYS, and a character counter output CCN.
And a line counter output LCN. Display address REA from display timing generation circuit 26 and address bus 2
The address AD on 2 is selected by the multiplexer 27 and specifies the address of the display memory 28. The multiplexer 27 switches the address of the display memory 28 to the address AD on the address bus 22 during the blanking period of the synchronizing signal SYS, makes the data of the display memory 28 rewritable. The display address is switched from the generation circuit 26 to the display address REA. The display memory 28 stores character code data accessed by the microprocessor 21 via the data bus 23 as display information. The character code data CD read from the display memory 28 is a character generator.
Supplied to 29. The character generator 29 outputs a character pattern CP based on the character code data CD from the display memory 28 and the raster address LUA from the display timing generation circuit 26. This character pattern CP is supplied to the video signal generation circuit 30. The video signal generation circuit 30 generates a video signal VS based on the input character pattern CP and the dot clock DCK and the character lock CCK from the display timing generation circuit 26, and sends the video signal VS to the CRT 31. The video signal generation circuit 30 also receives the cursor display pattern CRP from the cursor display circuit 32 and the display data modification signal RDS from the control flag 33, and modifies display data for cursor display and active screen identification. The address decoder 34 supplies strobe signals ST1, ST2, ST2 to the display timing generation circuit 26, the cursor display circuit 32, and the control flag 33 according to the address on the address bus 22, respectively.
Output ST3 and ST4. FIG. 2 is a detailed block diagram of the display timing generation circuit 26 shown in FIG. OSC41 is character pattern C
P is converted to serial data by the video signal generation circuit 30 and C
Generate dot clock DCK to send to RT31.
The dot counter 42 counts the number of horizontal dots of one character based on the dot clock DCK. The character counter 43 counts the number of characters in one horizontal scanning line based on a character clock CCK which is a carry signal of the dot counter 42. The raster counter 44 counts the number of vertical rasters of one character based on the carry of the character counter 43. The carry output of the raster counter 44 is supplied to the microprocessor 21 as an interrupt signal INT. The line counter 45 counts the number of character lines on one display screen based on the carry of the raster counter 44, and is readable by the microprocessor 21 via the peripheral data bus 35, selected by the strobe signal ST1. The address generation circuit 46 is a character counter 43
The display address REA is generated from the output CCN of the line counter 45 and the output LCN of the line counter 45 and supplied to the display memory 28. The output CCN of the character counter 43 and the output LCN of the line counter 44 are also supplied to the cursor display circuit 32. The output of the raster counter 44 is supplied to the character generator 29 as a raster address LUA. The synchronization signal generation circuit 47 generates a horizontal scanning and vertical scanning synchronization signal SYS based on the dot clock DCK, and supplies it to the CRT 31. Next, control regarding modification of display data output to the CRT 31 will be described. FIG. 3 is a detailed block diagram of the control flag 33, the cursor display circuit 32, and the video signal generation circuit 30 shown in FIG. The control flag 33 is a 1-bit register that stores designation information of the display mode of the display data, that is, information indicating whether the display is normal display or inverted display, and outputs a display data modification signal RDS.
The control flag 33 is writable from the microprocessor 21 and is selected by the strobe signal ST4. The cursor Y position register 51 stores the Y coordinate position of the screen on which the cursor is to be displayed, is readable and writable by the microprocessor 21, and is selected by the strobe signal ST2. The output of the cursor Y position register 51 is input to the Y comparator 53 together with the output LCN of the line counter 45, and the cursor Y position coincidence signal CYA
Activate The cursor X position register 52 stores the X coordinate position of the screen on which the cursor is to be displayed, is readable and writable by the microprocessor 21, and has a strobe signal ST.
Selected by 3. The output of the cursor X position register 52 is output to the X comparator 54 together with the output CCN of the character counter 43.
, And activates the cursor X position coincidence signal CXA when the two coincide with each other. The cursor pattern generation circuit 55 generates a cursor display pattern CRP by driving both the cursor Y position coincidence signal CYA and the cursor X position coincidence signal CXA at an active timing. Further, the shift register 61 performs parallel-serial exchange of the character pattern CP loaded therein at the timing of the character clock CCK at the timing of the dot clock DCK, and outputs serial data SD. The serial data SD is input to the exclusive OR gate 62 together with the display data modification signal RDS. When the control flag 33 is “0”, the display data modification signal
RDS becomes “0”, the serial data SD is output as it is, and when the control flag 33 is “1”, the display data modification signal RD
S becomes “1”, and the serial data SD is output with “0” / “1” inverted. The output of the exclusive OR gate 62 is input to the OR gate 63 together with the cursor display pattern CRP, and the two are combined and output to the CRT 10 as the video signal VS. Next, in the case where the display screen is divided into two areas, the interrupt signal INT from the raster counter 44 causes 1
FIG. 4 shows a flowchart of an interrupt program process of the microprocessor 21 which is started every time the display of a line is completed, and a control flag 33 for displaying an active screen in reverse video.
Update processing will be described. The total number of lines obtained by keyboard input etc. as variables to be processed by the program in the data memory 25
TN, active screen start line AS, active screen end line AE, screen A start line LA and screen B start line
LB is assigned. First, the line count value LCN, which is the content of the line counter 45, is read (step 70), and the total line number TN is read.
(Step 71), and if they match, the cursor Y position register 51 is read (Step 72), and the cursor Y position is compared with the screen A start line LA and the screen B start line LB, respectively. The located split screen is determined (step 73). Here, the cursor Y position is on the screen A
Area, the screen A is added to the active screen start line AS
After setting the value of the start line LA (step 74) and setting the value of the screen B start line LB-1 in the active screen end line AE (step 75), the interrupt program processing is ended and the processing returns to the main program processing. . Also step
If the cursor Y position is in the area of the screen B in the comparison of 73, the value of the screen B start line LB is set to the active screen start line AS (step 76), and the value of the total number of lines TN is set to the active screen end line AE. After the setting (step 77), the interrupt program processing ends, and the processing returns to the main program processing. On the other hand, if the line count value LCN does not match the total line number TN in the comparison in step 71, then the line count value is compared with the active screen start line AS (step 78). The control flag 33 is set (step 79). Further, the line count value is compared with the active screen end line AE (step 8).
0) If they match, the control flag 33 is reset (step 81). Thereafter, the interrupt program processing ends, and the process returns to the main program processing. By the above series of processing, when the cursor is located in the area of the screen A as shown in FIG. 5 (a) in the two divided screens shown in FIG. Is done. When the cursor is positioned in the area of the screen B as shown in FIG.
The whole is similarly displayed inverted. As described above, according to the present embodiment, since the entire predetermined divided screen is displayed in reverse, an active screen display with extremely high discrimination can be realized without using special display data or a screen area. . At this time, the processing of the microprocessor 21 does not require a large amount of memory access, it is only necessary to detect the position of the cursor on the screen in real time, determine the predetermined screen area, and rewrite the flag, It is only a simple comparison, operation and transfer by interruption. For example, when a screen of 80 characters × 25 lines is divided and displayed on two screens, a processing time of about 250 μS per screen is sufficient when converted by a microprocessor instruction having a minimum instruction execution time of 1 μS. The processing time is extremely short, 1/6 to 1/7. Next, as a second embodiment of the present invention, a display control device that distinguishes an active screen by half-brightness display of the screen will be described. The configuration of the display control device of the second embodiment is the same as that of the display control device except that the exclusive OR gate 62 inside the video signal generation circuit 30 of FIG. 3 is replaced with an AND gate 64 of FIG. This is the same as the block diagram of the first embodiment shown in FIGS. 1, 2 and 3, and its operation is also the same as that of the first embodiment. A detailed description of the lever is omitted. Here, control regarding modification of display data output to the CRT 31 of the present embodiment will be described. FIG. 6 is a detailed block diagram of the control flag 33, the cursor display circuit 32, and the video signal generation circuit 30 of the present embodiment. In FIG. 6, the serial data SD output from the shift register 61 is input to the AND gate 64 together with the display data modification signal RDS which is the output of the control flag 33.
When 33 is “1”, the display data modification signal RDS becomes “1”, the serial data SD is output as it is, and the control flag
When 33 is "0", the display data modification signal RDS becomes "0", the serial data SD is masked, and "0" is always output. The output of the AND gate 64 is ORed with the cursor display pattern CRP output from the cursor pattern generation circuit 55.
The signals are input to the gate 63, and the two are combined and output to the CRT 31 as the video signal VS. The configuration and operation other than the AND gate 64 are the same as those of the first embodiment. Next, in the case where the display screen is divided into two areas, the interrupt signal INT from the raster counter 44 causes 1
FIG. 7 shows a flowchart of the interrupt program processing of the microprocessor 21 which is started each time the display of a row is completed. The update processing of the control flag 33 for half-bright display other than the active screen will be described. The total number of lines obtained by keyboard input etc. as variables to be processed by the program in the data memory 25
TN, an active screen start line AS, an active screen end line AE, a screen A start line LA, a screen B start line LB, and a half-brightness flag HT are assigned. First, the line count value, which is the content of the line counter 45, is read out (step 80) and compared with the total number of lines TN (step 81).
After inverting "0" / "1" of HT (step 82), the cursor Y position register 51 is read (step 83), and the cursor Y position is compared with the screen A start line LA and the screen B start line LB, respectively. Then, the divided screen where the cursor is located is determined (step 84). Here, the cursor Y position is on the screen A
Area, the screen A is added to the active screen start line AS
After setting the value of the start line LA (step 85) and setting the value of the screen B start line LB-1 in the active screen end line AE (step 86), the interrupt program processing is ended and the processing returns to the main program processing. . Also step
If the cursor Y position is in the area of the screen B in the comparison of 84, the value of the screen B start line LB is set to the active screen start line AS (step 87), and the value of the total number of lines TN is set to the active screen end line AE. After setting (step 88)
The interrupt program processing ends, and the process returns to the main program processing. On the other hand, if the line count value does not match the total line number TN in the comparison in step 81, then the line count value is compared with the active screen start line AS (step 89). The control flag 33 is set (step 90). Further, the line count value is compared with the active screen end line AE (step 91).
If they match, the value of the half-brightness flag HT is set in the control flag 33 (step 92). Thereafter, the interrupt program processing ends, and the process returns to the main program processing. In the above-described program processing, as shown in FIG. 8, the value of the half-luminance flag HT is inverted for each field.
In contrast to the 100% luminance display, the value of this flag thins out the output of the display data to a half interval so that a display of 50% luminance can be performed. With the above series of processing, when the cursor is positioned in the area of the screen A as shown in FIG. 9A, the screen A is displayed in the two divided screens shown in FIGS. 9 (a) and 9 (b). Normal full brightness display is performed, and the entire screen B is displayed at half brightness. When the cursor is positioned in the area of the screen B as shown in FIG. 9 (b), the screen B is displayed in a normal full brightness display, and the screen A is displayed in a half brightness. As described above, according to the present embodiment, the screen other than the predetermined divided screen is displayed at half-brightness. Can be realized. Further, the brightness control as in the present embodiment is very effective as a display method in a CRT display without a high brightness designation input terminal or a flat panel display such as an LCD or a plasma. At this time, the processing time of the microprocessor 1 is extremely short, 1/6 to 1/7 of the conventional case, as in the first embodiment. In the above-described embodiment, an example of the reverse display of the active screen or the half-bright display of the inactive screen in the monochrome text screen divided into two regions has been described. If the present invention is applied to the underline display by determining only the raster address, the multi-gradation display by setting the time ratio for thinning out the display data in a programmable manner, or the graphic display, the same control can be easily performed. Can be realized. [Effects of the Invention] As described above, according to the present invention, an active screen display can be performed only by performing a process of determining a predetermined screen area and rewriting a flag without rewriting the display memory. Therefore, the load on the microprocessor can be extremely reduced as compared with the related art, and high-speed screen display can be realized. Also, by changing the shape of the display data, it is possible to perform an active screen display with extremely high discrimination without using special display data or a screen area.
It is possible to improve the performance of the active screen display at the time of the conventional split screen display, and to provide a display control device having an efficient split screen display function. In addition, simple processing by the microprocessor enables advanced display processing to be realized without the need for complicated dedicated hardware for that purpose. Hardware is shared, and inexpensive flexibility with minimal hardware Also, there is an effect that a display control device having a high level can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a display control device according to a first embodiment of the present invention. FIG. 2 is a detailed block diagram showing a display timing generating circuit in the device. FIG. 3 is a detailed block diagram of a control flag, a cursor display circuit, and a video signal generation circuit in the apparatus, FIG. 4 is a flowchart of an interrupt program process in the apparatus, and FIGS. FIG. 6 is a diagram showing a display example by a device, FIG. 6 is a detailed block diagram of a control flag, a cursor display circuit and a video signal generation circuit in a display control device according to a second embodiment, and FIG. FIG. 8 is a flowchart of the processing, FIG. 8 is a timing chart of the half-brightness display control in the same device, and FIG.
(B) is a diagram showing a display example by the same device, FIG. 10 is a configuration diagram of a conventional display device, and FIGS. 11 (a) and (b) are diagrams showing border display of a divided screen in the conventional display device. is there. 1,21; microprocessor, 2; system bus, 3; main memory, 4,28; display memory, 5; display control circuit, 6,30; video signal generation circuit, 7,31; CRT, 8,32; cursor Display circuit,
9; keyboard, 10; peripheral control circuit, 11; disk device, 2
2; address bus, 23; data bus, 24; program memory, 25; data memory, 26; display timing generation circuit, 2
7; multiplexer, 29; character generator, 33; control flag, 34; address decoder, 35; peripheral data bus

Claims (1)

(57) [Claims] A processor that stores display information to be displayed in a display memory, a display timing generation circuit that generates a display timing signal and a horizontal and vertical synchronization signal of the display,
Video signal generating means for converting the display information stored in the display memory into a video signal based on the display timing signal and sending the video signal to the display; and displaying a cursor on the video signal based on display position information of the cursor A cursor display circuit for adding a signal; a rewritable flag for storing information designating a display mode of the display information; and a display information converting unit that converts the display information into the video signal based on an output of the flag. Means for changing a display mode, wherein the processor receives the display timing signal as an interrupt request, and in the interrupt process activated by the processor, when the display screen of the display is divided into a plurality of divided screens, the display timing Signal, display position information of the cursor, and area designation information of the split screen Display control device characterized by rewriting the flag in order to identify the display period of the display period and the other split screen specified split screen different contents of the flag in the both periods by the cursor based on. 2. The means for changing the display mode of the display information reverses the split screen specified by the cursor and changes the mode so that the other split screen is normally displayed. The display control device according to claim 1. 3. The means for changing the display mode of the display information is to change the display mode so that the divided screen specified by the cursor is normally displayed, and the other divided screen is displayed in half-brightness. Claim 1
A display control device according to the item.