JP2817752B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2817752B2 JP2817752B2 JP4174359A JP17435992A JP2817752B2 JP 2817752 B2 JP2817752 B2 JP 2817752B2 JP 4174359 A JP4174359 A JP 4174359A JP 17435992 A JP17435992 A JP 17435992A JP 2817752 B2 JP2817752 B2 JP 2817752B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring layer
- metal wiring
- metal
- forming
- connection hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】図３は、従来の半導体装置の製造方法を
説明するための断面図である。シリコン基板７上に、酸
化シリコン膜６が形成されており、この酸化シリコン膜
６上に第１金属配線層１がパターニングされている。さ
らに、第１金属配線層１及び酸化シリコン膜６の上に、
絶縁膜３が形成されている。第１金属配線層１の上方の
絶縁膜３が選択的に除去されて接続孔４が形成され、こ
の接続孔４を埋める埋め込み金属５と絶縁膜３上に第２
金属配線層２がパターニングされている。2. Description of the Related Art FIG. 3 is a cross-sectional view for explaining a conventional method for manufacturing a semiconductor device. A silicon oxide film 6 is formed on a silicon substrate 7, and the first metal wiring layer 1 is patterned on the silicon oxide film 6. Further, on the first metal wiring layer 1 and the silicon oxide film 6,
An insulating film 3 is formed. The insulating film 3 above the first metal wiring layer 1 is selectively removed to form a connection hole 4, and a buried metal 5 filling the connection hole 4 and a second
The metal wiring layer 2 is patterned.
【０００３】図３に示す様に、接続孔４は、埋め込み金
属５が良好に埋め込まれるために、順テーパーにエッチ
ングして形成されている。As shown in FIG. 3, the connection hole 4 is formed by etching into a forward taper so that the buried metal 5 can be buried well.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、このよ
うに製造された半導体装置においては、図４に示すよう
に、装置の集積度を上げるために接続孔の面積を小さく
しようとした場合、接続孔面積と接続孔抵抗は、反比例
の関係にあるため、接続孔抵抗が増大し、半導体装置の
特性を劣化させるという問題点があった。特に、接続孔
は順テーパーに形成されるため、絶縁膜３の膜厚を厚く
して層間容量を低減させようとした場合第１の金属配線
層１と埋め込み金属５の接触面積が小さくなり接続孔抵
抗が著しく増大した。However, in the semiconductor device manufactured as described above, as shown in FIG. 4, when the area of the connection hole is reduced in order to increase the degree of integration of the device, the connection hole needs to be reduced. Since the area and the contact hole resistance are in an inverse relationship, there is a problem that the contact hole resistance increases and deteriorates the characteristics of the semiconductor device. In particular, since the connection hole is formed in a forward taper, when the thickness of the insulating film 3 is increased to reduce the interlayer capacitance, the contact area between the first metal wiring layer 1 and the buried metal 5 is reduced, and the connection hole is formed. Pore resistance increased significantly.
【０００５】そこで、本発明の技術的課題は、上記欠点
に鑑み、多層金属配線の配線間接続孔の抵抗低減化を図
った半導体装置を、少ない製造工程で容易に得ることが
できる半導体装置の製造方法を提供することにある。In view of the above-mentioned drawbacks, the technical problem of the present invention is to provide a semiconductor device in which the resistance of a connection hole between wirings of a multilayer metal wiring is reduced with a small number of manufacturing steps. It is to provide a manufacturing method.
【０００６】[0006]
【課題を解決するための手段】本発明によれば、半導体
基板上に第１の金属配線層を形成する工程と、該第１の
金属配線層を覆う絶縁膜を形成する工程と、前記第１の
金属配線層上の前記絶縁膜に選択的に接続孔を形成する
工程と、前記接続孔を埋設金属で埋め込む工程と、前記
該接続孔に埋め込んだ埋設金属を介して前記第１の金属
配線層と接続される第２の金属配線層を形成する工程と
を有する半導体装置の製造方法において、前記第１の金
属配線層を形成する工程中で、前記第１の金属配線層を
パターニングすると同時に、前記第１の金属配線層にお
ける前記埋設金属との接続部に凹部を形成し、前記接続
孔を埋設金属で埋め込む工程で同時に前記凹部を埋設金
属で埋め込むことを特徴とする半導体装置の製造方法が
得られる。According to the present invention, a step of forming a first metal wiring layer on a semiconductor substrate, a step of forming an insulating film covering the first metal wiring layer, Selectively forming a connection hole in the insulating film on the first metal wiring layer, filling the connection hole with a buried metal, and forming the first metal through the buried metal buried in the connection hole. Forming a second metal wiring layer connected to the wiring layer, wherein the first metal wiring layer is patterned during the step of forming the first metal wiring layer. A step of forming a concave portion at a connection portion of the first metal wiring layer with the buried metal, and burying the concave portion with the buried metal in the step of burying the connection hole with the buried metal. A method is obtained.
【０００７】この製造方法で得られた半導体装置は、第
１の金属配線層と絶縁膜を介して上層に形成した第２の
金属配線層と第１の金属配線層と第２の金属配線層を電
気的に接続するために絶縁膜に形成した接続孔と接続孔
を完全に埋め込む埋め込み金属を有し、第１の金属配線
層の表面を接続孔下部において凹状に形成し、埋め込み
金属と第１の金属配線層の接触面積を大きくしている。The semiconductor device obtained by this manufacturing method includes a second metal wiring layer, a first metal wiring layer, and a second metal wiring layer which are formed above the first metal wiring layer and an insulating film. And a buried metal completely filling the connection hole formed in the insulating film in order to electrically connect the buried metal and the buried metal with the surface of the first metal wiring layer formed in a concave shape below the connection hole. The contact area of the first metal wiring layer is increased.
【０００８】[0008]
【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【０００９】図１は本発明の製造方法によって得られる
半導体チップの断面図である。FIG. 1 is a sectional view of a semiconductor chip obtained by the manufacturing method of the present invention.
【００１０】まず、本発明の製造方法を説明する前に、
本発明の基となる製造方法を図１を参照して説明する。First, before explaining the manufacturing method of the present invention,
The manufacturing method on which the present invention is based will be described with reference to FIG.
【００１１】本発明の基となる製造方法は、従来例と同
様に、シリコン基板７上に膜厚が約１μｍの酸化シリコ
ン膜６を形成し、さらに第１金属配線層１を約５００ｎ
ｍのアルミニウム膜で形成しパターニングする。The manufacturing method based on the present invention is, as in the prior art, formed with a silicon oxide film 6 having a thickness of about 1 μm on a silicon substrate 7 and further with a first metal wiring layer 1 having a thickness of about 500 n.
An aluminum film is formed and patterned.
【００１２】次に、絶縁膜３を１μｍの膜厚で形成し平
坦化する。第１金属配線層１の上部には、選択的に接続
孔４をエッチングで形成する。この時接続孔４の下部の
第１金属配線層１が凹状になる様にエッチングする。Next, an insulating film 3 is formed to a thickness of 1 μm and flattened. A connection hole 4 is selectively formed on the first metal wiring layer 1 by etching. At this time, the etching is performed so that the first metal wiring layer 1 below the connection hole 4 becomes concave.
【００１３】次に、例えばＣＶＤ法で形成したタングス
テンなどの埋め込み金属５で接続孔を完全に埋め込み、
エッチバックした後最後に、第２の金属配線層２を膜厚
１．０μｍで形成しパターニングする。Next, the connection hole is completely buried with a burying metal 5 such as tungsten formed by a CVD method, for example.
Finally, after the etch back, a second metal wiring layer 2 is formed with a thickness of 1.0 μm and patterned.
【００１４】次に本発明の製造方法を図１に加えて図２
をも参照して本発明の製造方法を説明する。本発明の製
造方法は、以下に述べる点以外は、上述した本発明の基
となる製造方法と同様である。Next, the manufacturing method of the present invention is added to FIG.
The production method of the present invention will be described with reference to FIG. The manufacturing method of the present invention is the same as the above-described manufacturing method based on the present invention, except for the following points.
【００１５】上述した本発明の基となる製造方法では、
第１金属配線層１に凹状部を形成する方法として、接続
孔形成時に、第１金属配線層１の表面をエッチングする
方法を用いたが、本発明の製造方法では、第１金属配線
層１に形成される凹状部を、第１金属配線層１をパター
ニングする際に形成する方法を採用する。In the above-described production method based on the present invention,
As a method of forming a concave portion in the first metal wiring layer 1, a method of etching the surface of the first metal wiring layer 1 at the time of forming a connection hole is used. Is formed when the first metal wiring layer 1 is patterned.
【００１６】つまり、第１金属配線パターニングと同時
に凹部形成パターン８を０．５μｍ□以下で例えばフォ
トレジストで形成し、通常反応性イオンエッチングでエ
ッチングすれば、反応性エッチングガスの供給が少ない
ため、凹部形成パターン部８だけエッチング速度が遅く
なり第１金属配線層１を残存させることができる。That is, if the concave portion forming pattern 8 is formed of, for example, a photoresist with a thickness of 0.5 μm □ or less at the same time as the first metal wiring patterning and is usually etched by reactive ion etching, the supply of reactive etching gas is small. The etching rate is reduced only in the concave portion forming pattern portion 8, and the first metal wiring layer 1 can be left.
【００１７】本発明に従って第１金属配線層１をパター
ニング時に凹部を形成する方法は、接続孔形成時に凹部
を形成する方法に比較して容易に安定に形成できる利点
がある。The method of forming a concave portion when patterning the first metal wiring layer 1 according to the present invention has an advantage that it can be formed more easily and stably than the method of forming a concave portion when forming a connection hole.
【００１８】[0018]
【発明の効果】以上説明したように、本発明は、選択的
に形成された接続孔の下部の第１金属配線を凹状に形成
するため、第１金属配線と埋め込み金属の接触面積を増
加させることができる。As described above, the present invention increases the contact area between the first metal wiring and the buried metal because the first metal wiring below the selectively formed connection hole is formed in a concave shape. be able to.
【００１９】本発明によれば、半導体装置の高集積化、
及び配線層間容量の低容量化による高性能化を接続孔の
抵抗を増大させずに実現できる。According to the present invention, high integration of a semiconductor device,
In addition, high performance can be realized without reducing the resistance of the connection hole by reducing the capacitance between wiring layers.
【００２０】本発明に従って第１金属配線層１をパター
ニング時に凹部を形成する方法は、接続孔形成時に凹部
を形成する方法に比較して容易に安定に形成できる利点
がある。The method of forming a concave portion when patterning the first metal wiring layer 1 according to the present invention has an advantage that it can be formed more easily and stably than the method of forming a concave portion when forming a connection hole.
【図１】本発明の基となる製造方法及び本発明による製
造方法によって得られる半導体チップの断面図である。FIG. 1 is a cross-sectional view of a semiconductor chip obtained by a manufacturing method based on the present invention and a manufacturing method according to the present invention.
【図２】本発明による製造方法を説明するための図であ
り、凹部形成パターンを示す断面図である。FIG. 2 is a view for explaining a manufacturing method according to the present invention, and is a cross-sectional view showing a recess forming pattern.
【図３】従来の半導体装置の製造方法によって得られる
半導体チップの断面図である。FIG. 3 is a cross-sectional view of a semiconductor chip obtained by a conventional method for manufacturing a semiconductor device.
【図４】図３の半導体装置における接続孔抵抗の接続孔
面積依存性を示す相関図である。4 is a correlation diagram showing connection hole area dependence of connection hole resistance in the semiconductor device of FIG. 3;
１ 第１金属配線層 ２ 第２金属配線層 ３ 絶縁膜 ４ 接続孔 ５ 埋め込み金属 ６ 酸化シリコン膜 ７ シリコン基板 DESCRIPTION OF SYMBOLS 1 1st metal wiring layer 2 2nd metal wiring layer 3 insulating film 4 connection hole 5 buried metal 6 silicon oxide film 7 silicon substrate
Claims (1)
する工程と、該第１の金属配線層を覆う絶縁膜を形成す
る工程と、前記第１の金属配線層上の前記絶縁膜に選択
的に接続孔を形成する工程と、前記接続孔を埋設金属で
埋め込む工程と、前記該接続孔に埋め込んだ埋設金属を
介して前記第１の金属配線層と接続される第２の金属配
線層を形成する工程とを有する半導体装置の製造方法に
おいて、 前記第１の金属配線層を形成する工程中で、前記第１の
金属配線層をパターニングすると同時に、前記第１の金
属配線層における前記埋設金属との接続部に凹部を形成
し、 前記接続孔を埋設金属で埋め込む工程で同時に前記凹部
を埋設金属で埋め込むことを特徴とする半導体装置の製
造方法。A step of forming a first metal wiring layer on a semiconductor substrate, a step of forming an insulating film covering the first metal wiring layer, and the insulating film on the first metal wiring layer. Forming a connection hole selectively, burying the connection hole with a buried metal, and a second metal connected to the first metal wiring layer via the buried metal buried in the connection hole. Forming a wiring layer. In the method of manufacturing a semiconductor device, the step of forming the first metal wiring layer includes the step of patterning the first metal wiring layer and the step of forming the first metal wiring layer. A method of manufacturing a semiconductor device, comprising: forming a recess at a connection portion with the buried metal; and burying the recess with a buried metal at the same time as filling the connection hole with the buried metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4174359A JP2817752B2 (en) | 1992-07-01 | 1992-07-01 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4174359A JP2817752B2 (en) | 1992-07-01 | 1992-07-01 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0621235A JPH0621235A (en) | 1994-01-28 |
| JP2817752B2 true JP2817752B2 (en) | 1998-10-30 |
Family
ID=15977251
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4174359A Expired - Lifetime JP2817752B2 (en) | 1992-07-01 | 1992-07-01 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2817752B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100248805B1 (en) * | 1996-12-30 | 2000-03-15 | 김영환 | A method for forming metal wire in semiconductor device |
| JP2003115535A (en) * | 2001-10-04 | 2003-04-18 | Hitachi Ltd | Semiconductor integrated circuit device |
| JP4648284B2 (en) * | 2006-10-16 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device |
| CN111613726A (en) * | 2020-06-28 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Thin film metal resistor and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS495283A (en) * | 1972-04-28 | 1974-01-17 | ||
| JPS63137941U (en) * | 1987-03-04 | 1988-09-12 |
-
1992
- 1992-07-01 JP JP4174359A patent/JP2817752B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0621235A (en) | 1994-01-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980722 |