JP2817638B2 - Error correction code decoder resynchronization device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code decoder used in the field of data communication.
An apparatus for re-establishing synchronization of an error correction code decoder.

[0002]

2. Description of the Related Art As a forward error correction method, an error correction code capable of correcting a data error by itself is known. Various codes have been proposed as these error correction codes. For example, Hamming codes, BCH codes, and RS (Reed-Solomon) codes are used as block codes, and Iwanappa codes, Hagebarge codes are used as convolutional codes.
An r code and the like have been proposed.

Generally, redundant bits are added to an error correction code. For example, a 1-bit redundant bit (of course, the redundant bit is not limited to 1 bit) is added to the (n-1) -bit data to form an n-bit error correction code. On the decoding side, the n-bit data is decoded and the original n-
Reproduce 1-bit data.

[0004]

As described above, it is necessary to input data to the error correction code decoder n bits at a time. Has a problem that decoding cannot be performed.

[0005] Whether or not decoding has been correctly performed can be known by monitoring the syndrome in time series. In other words, if the decoding has been performed correctly, 0s appear in the syndrome continuously, but if the decoding has not been performed correctly, 1 appears in the syndrome. The number of 1s increases as the decoding cannot be performed correctly.

[0006] In the simplest case, it is conceivable to shift the data series so that the syndrome continues to zero. However, since the syndrome is changed by shifting the data series by one, there is a problem that it takes time until the syndrome is stabilized after shifting one bit, and it takes time until it can be determined whether or not the synchronization has really been recovered. . This is because the register used for syndrome calculation and the register used for error correction are shared, so that the previous correction result affects the syndrome.

As another method, n error-correcting code decoders are used, and a data sequence shifted by 1 bit is input. Then, among the syndromes of the respective error correction code decoders, the decoded output of the error correction code decoder with the least occurrence of 1 is selected and used. In this method, although a synchronization error can be corrected instantaneously, there is a problem that n error correction code decoders are required and the circuit scale becomes large.

[0008] The present invention has been made in view of the above,
An object of the present invention is to provide a resynchronization device for an error correction code decoder that can quickly resynchronize with a relatively simple configuration.

[0009]

According to a first aspect of the present invention, there is provided a resynchronizing apparatus for an error correction code decoder, comprising: decoding means for decoding an n-bit error correction code of a received sequence; Storage means having a storage sequence of 2n-1 sequences for storing a received sequence shifted by a predetermined bit;
A syndrome calculating means for calculating an n-sequence syndrome for a received sequence shifted by one bit on the basis of the data stored in the -1 series storage means, and the most one of the n-sequence syndromes based on the calculation result of the syndrome calculating means. Bit shift means for determining a sequence with a small number of bits and bit-shifting the received sequence, wherein the storage means shares n-1 storage sequences in the calculation of one syndrome and the calculation of the next syndrome It is characterized by:

According to a second aspect of the present invention, in the resynchronization apparatus for an error correction code decoder according to the first aspect, the bit shift means includes a sequence determined by the syndrome calculation means to be the least one. , The received sequence is bit-shifted by the number of bit shifts from the original received sequence.

[0011]

[0012]

According to the first aspect of the present invention, an n-sequence syndrome is created for each of n-sequences shifted by 1 bit from the original received sequence, and the most one of the n-sequence syndromes is generated.
Is determined, and which sequence is synchronized is determined. From the bit shift between the synchronized sequence and the original received sequence, it is immediately known how many bits of the original received sequence should be shifted to achieve synchronization. Then, the bits of the original received sequence are shifted by the number of bits, and resynchronization can be immediately performed. Since only the syndrome needs to be calculated, the circuit scale can be reduced as compared with the case where n decoders are used.

When an n-bit error correction code is used, it is necessary to determine whether or not synchronization has been achieved and to achieve resynchronization,
It is necessary to calculate n syndromes for a sequence shifted by one bit. However, when calculating only the syndrome, n-1 storage sequences can be shared between the calculation of one syndrome and the calculation of the next syndrome. Therefore, it is not necessary to use n × n storage sequences to calculate n syndromes, and it is sufficient to have 2n−1 storage sequences.

According to a second aspect of the present invention, when it is determined that the error of this sequence is the least from the syndrome of the sequence shifted by m (0 ≦ m <n) bits, the bit shift means converts the original received sequence to m ( Or nm) to resynchronize by shifting the bits.

[0015]

An embodiment of the present invention will be described with reference to the drawings. In this embodiment, the present invention is applied to an Iwadare code having a coding rate of 7/8. The coding rate of 7/8 means that the original data of 7 bits is converted into an 8-bit code. Therefore, n = 8, and at the time of decoding, 8-bit data is decoded into 7-bit data.

Generally, when transmitting a code sequence W of a convolutional code of a parity check matrix H at a coding rate of k / n, an error sequence E, E = (E1 (D),..., En ( D)) is added, and the received sequence Y, Y = (Y1 (D),..., Yn (D)) is received (D represents a delay operator).

[0017] In this case, S = (S1 (D) , ·····, Sn-k (D)) = YH T to become n-k-dimensional vector sequence S is called syndrome. Code sequence W is, meet the ^{WH T = 0, S = (} W +
E) H ^T, since the EH ^T, the syndrome S, the transmission sequence is determined by the error sequence regardless of what the was. If there are no errors, the syndrome will always be zero.

In actual communication, an error may occur due to noise, jitter, and the like on the channel, and the syndrome may become one. In such a case, the syndrome only temporarily becomes one. However, when the synchronization is out of sync, 1 is continuously generated in the syndrome, and a state in which 1 is generated with a probability of 50% in chronological order continues.

FIG. 1 shows a circuit configuration of an error correction code decoder and a resynchronizing device therefor according to the embodiment. The reception sequence is sent to the serial / parallel (S
/ P) is input to the converter 2. The serial / parallel converter 2 converts the received sequence into 8-bit parallel data Y1 to Y.
8 and output to the Iwadare code decoder 3. The Iwadare code decoder 3 decodes the 8-bit Iwadare codes Y1 to Y8 into 7-bit data W1 to W7. Note that S is the syndrome of the decoder 3. The details of the decoder 3 will be described later. The parallel / serial (P / S) converter 3 converts 7-bit parallel data W1 to W7 into serial data and outputs it.

The syndrome calculation unit 5 includes a series of shift registers (hereinafter simply referred to as registers) for R1 to R15. Each register row has as many stages (42 stages in this embodiment) as necessary to calculate the syndromes S0 to S7. The registers R1 to R8 store the data Y of the reception sequence.
1 to Y8 are input as they are. Registers R2 to R9 store data Y2 to Y8 and Y1 ′ (“′”
Indicates the data of the next block). Registers R3 to R10 store data Y3 further shifted by one bit.
To Y8 and Y1 'to Y2' are input. Thus, the register groups R4 to R11, R5 to R12, R6 to R13,
Data shifted one bit at a time is sequentially stored in R7 to R14 and R8 to R15.

The syndrome calculator 5 includes registers R1 to R1.
Syndrome S0 based on the data stored in R8
Is calculated. Then, the obtained syndromes S0 are sequentially stored in the syndrome register SR0. Similarly,
The syndrome calculation unit 5 includes registers R2 to R9, R3 to
R10, R4 to R11, R5 to R12, R6 to R13,
Based on the data stored in R7 to R14 and R8 to R15, respectively, the syndromes S1, S2, S3, S4
S5, S6, S7 are calculated, and the syndrome registers SR1, SR2, SR3, SR4, SR5, SR, respectively
6, stored in SR7.

Each of the syndromes S0, S1, S2,..., S
7 are 0, 1, and 1, respectively, for the original data Y1 to Y8.
.. Represents a syndrome for a sequence shifted by 7 bits. Syndrome registers SR0, SR1, S
R2,. The SRs 7 each have the number of stages required to determine synchronization. In this embodiment, the number of stages is 32, but is not limited to this.

Each of the syndrome registers SR0, SR1,
SR2,..., SR7 are weight counting means C0, C
1, C2,..., C7. Weight counting means C
, C7 are the syndrome registers S
The number of 1 in R0, SR1, SR2,..., SR7 is counted and output to the comparison / determination unit 6.

The comparing and judging section 6 comprises weight counting circuits C0, C
The smallest one is selected from the counting results of 1, C2,..., C7, and the contact point of the switch SW is switched so that the data of the reception sequence is shifted by the number of bit shifts corresponding thereto. For example, when shifting the reception sequence by one bit, the comparison determination unit 6
Switches SW to the b side, and inputs the previous data Y8 to the serial / parallel converter 2 again. After that, the comparison determination unit 6
Switches the switch SW to the a side, and sets the subsequent data Y
1 ′ to Y7 ′ are input to the serial / parallel converter 2. The serial / parallel converter 2 outputs data Y8, Y
1 ′ to Y7 ′ are converted into parallel data and output to the decoder 3. By repeating this operation, it is possible to resynchronize the decoder 3 by shifting any bit data.

The syndrome calculator 5 calculates the syndrome by the same calculation as that of the decoder 3. Here, the decoder 3
Will be described with reference to FIG. 11 is a 35-stage register, 12 is a 28-stage register, 13 is a 22-stage register, 14 is a 17-stage register, 15 is a 13-stage register, 1
6 is a 10-stage register and 17 is an 8-stage register. Registers 11, 12, 13, 14, 15, 16, 17 have
Received sequence data Y1, Y2, Y3, Y4, Y
5, Y6, and Y7 are input.

Reference numeral 19 is a seven-stage register, 20 is a six-stage register, 21 is a five-stage register, 22 is a four-stage register, 23 is a three-stage register, 24 is a two-stage register, and 25 is a one-stage register. Each of the registers 19 to 25 includes a register 11 to 1
7 output. Registers 33, 34, 35, 3
6, 37, 38 and 39 are single-stage registers.

26 is a (10000001) pattern detector, 27 is a (1000001) pattern detector, 28 is a (100001) pattern detector, and 29 is a (10000001) pattern detector.
1) A pattern detector, 30 is a (1001) pattern detector, 31 is a (101) pattern detector, and 32 is a (11)
It is a pattern detector.

40 is an 8-stage register, 41 is a 15-stage register, 42 is a 21-stage register, 43 is a 26-stage register, 4
4 is a 30-stage register and 45 is a 33-stage register. The outputs of the registers 40, 41, 42, 43, 44, 45 are decoded data W2, W3, W4, W5, W6, W7.

(10000001) Pattern detector 2
6, (1000001) pattern detector 27, (100
(001) pattern detector 28, (10001) pattern detector 29, (1001) pattern detector 30, (10
1) Pattern detector 31, (11) Pattern detector 32
Is a bit pattern detector for detecting errors of Y1 to Y7 in one group of parallel inputs Y1 to Y8.

(11) The pattern detector 32 receives the syndrome S and the output of the one-stage shift register 33, and outputs "1" when both are "1". This output is added to the series of Y7, that is, the output of the eight-stage register 17 by an adder. Then, the decoded output W7 is obtained after being delayed by the 33-stage register.

On the other hand, (11) The output of the pattern detector 32 is added to the input of the one-stage register 33 through the adder. Then, the input of the one-stage register 33 is set to “0”, and the input of the one-stage register 34 is set to “0” by the adder on the input side of the one-stage register 34, and “11” of the syndrome series is set to “00”. To

(101) The pattern detector 31 receives the syndrome S and the output of the one-stage register 34, and outputs “1” when the output of the syndrome S is “1” and the output of the one-stage register 34 is “1”. Is output. Originally, it is necessary to detect when the output of the first-stage register 33 is “0”.
When the output of the stage shift register 33 is 1, (1
1) Since the error has been corrected by the pattern detector 32, there is no need for this. (101) Pattern detector 31
Is added to the output of the 10-stage register 16 by the adder. Then, the decoded output W6 is obtained after being delayed by the 30-stage register 44.

Similarly, the (1001) pattern detector 3
, (10000001) pattern detector 26 corrects errors in series Y5,. And
The decoded outputs W5 to W1 are obtained through the 26-stage register 43,..., The 8-stage register, and the adder 46.

The syndrome calculation unit 5 also calculates the syndromes S0 to S7 in the same manner as the decoder 3. However, the syndrome calculation unit 5 does not need to correct the data stored in the registers R1 to R15.

In the above embodiment, the present invention is constituted by hardware using a shift register. However, the present invention can be implemented by high-speed software processing using a digital signal processor (DSP). In this case, a random access memory (RAM) will be used as the storage means.

Further, in the above embodiment, the case where the present invention is applied to the decoding of the Iwadare code having a coding rate of 7/8 has been described. However, the type of the error correction code is not limited to the Iwadare code. The present invention can be applied to resynchronization of various error correction code decoders using a syndrome pattern decoding method such as a BCH code and an RS code.

[0037]

As described above, the resynchronizing apparatus for an error correction code decoder according to the present invention includes a decoding means for decoding an error correction code of a received sequence, and a plurality of means for storing the received sequence shifted by a predetermined bit. Storage means having a storage sequence of, a syndrome calculation means for calculating a syndrome based on data stored in the storage means, and a bit shift means for bit-shifting the reception sequence based on a calculation result of the syndrome calculation means. Therefore, there is an advantage that the synchronization of the decoder can be quickly restored with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an Iwadare code decoder including a resynchronization device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a circuit configuration of a decoder applied to the Iwadare code decoder.

[Explanation of symbols]

2 ... serial / parallel converter, 3 ... Iwadare code decoder, 4 ... parallel / serial converter, 5 ...
Syndrome calculation unit, 6... Comparison judgment unit, R1 to R1
5 shift register, SR0-7 syndrome register, C0-7 weight counting circuit

Claims (2)

(57) [Claims] 1. A decoding means for decoding an n-bit error correction code of a reception sequence, a storage means having a 2n-1 sequence storage sequence for storing the reception sequence shifted by a predetermined bit,
Based on the data stored in the storage means of the 2n-1 series ,
A syndrome calculating means for calculating an n-sequence syndrome with respect to the received sequence shifted by one bit , and an n-sequence syndrome based on a calculation result of the syndrome calculating means .
Ri to determine the most 1 small series, the received sequence have a bit shifting means for bit shifting said storage means,
Calculation of one syndrome and calculation of the next syndrome
A resynchronization device for an error correction code decoder , wherein n-1 storage sequences are shared . 2. The apparatus according to claim 1, wherein said bit shift means comprises a syndrome.
The series determined to be the least by the calculation means and the original
Bit shift the received sequence by the number of bit shifts from the signal sequence.
2. The resynchronization of the error correction code decoder according to claim 1,
apparatus.