JP2814683B2 - Instruction processing unit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction processing apparatus that uses an execution result of an instruction at a branch prediction destination to process an instruction further ahead.

(Prior Art) A conventional instruction processor fetches and decodes an instruction at a branch prediction destination (for example, IBM360 / 91 instruction processor: DWAndreson, FJSparacio, FMTomasulo: “The IB
M System / 360 Model 91: Machine Philosophy and Instr
uction Handling ", IBM Hounal of Research & Develop
ment, pp. 8-24, No. 1, Mol. 1, Jan. 1967.) and instructions with all operands are executed even if the branch destination is not determined, but the execution result is the source operand of another instruction. What does not work (for example, "Shinkaze" instruction processor: Kuga, Murakami, Tomita: "High speed mechanism of" Shinkaze "processor", Proc. Of the 37th Annual Conference of IPSJ, 4N-2, 1988.) These instruction processors are, as shown in FIG.
An instruction storage means 10, a register write reservation means 20, an instruction issuing means 40 ', an operand access control means 50, an instruction execution means 60, a branch prediction destination instruction execution result storage means 70', and a register 80 are provided. There is no means for reading the operand from the branch prediction destination instruction execution result storage means of the apparatus.

(Problems to be Solved by the Invention) However, in the conventional instruction processing device, the execution of the instruction at the predicted branch destination is only the pre-processing before issuing the instruction,
Even if the instruction at the prediction destination is executed, the instruction using the execution result is not executed until the branch destination is determined. There is a problem that adding such a constraint causes an executable instruction to wait, thereby deteriorating performance.

SUMMARY OF THE INVENTION An object of the present invention is to provide an instruction processing apparatus that eliminates such a conventional problem and uses the execution result of an instruction at a branch prediction destination to further process the next instruction.

(Means for Solving the Problems) In order to solve the above-mentioned problems, a first invention of the present application is provided: a branch destination address is determined by an instruction to be processed in a branch prediction method without waiting for a branch destination being determined by a branch instruction. First means for storing, second means of a register for writing an execution result of an instruction, third means for pre-reserving writing to a register to be executed by the instruction obtained by the first means as an execution result, Fourth means for holding an instruction reserved by the third means and issuing the instruction, fifth means for executing the instruction issued by the fourth means, fifth means and second means A means for temporarily storing an execution result of an instruction at a branch destination which has been predicted but not determined, and a second means for storing an execution result held by the sixth means. A seventh means for transferring to the means; Eighth means in which the fourth means reads the execution result held by the sixth means as an operand, and ninth means in which the fourth means reads the execution result held by the second means as an operand. A fourth means for holding an instruction sequence before a branch instruction whose branch destination is undetermined;
The eleventh means for issuing the instruction held by the tenth means and the instruction reserved by the third means to the fifth means, and receiving the register write reservation by the third means, and performing the eleventh means A twelfth means for controlling the operand access performed by the eleventh means by receiving instruction issue history information and receiving branch destination determination information by the fifth means, It is characterized in that the processing of the further instruction is performed using the execution result of the instruction of the branch destination.

Further, the second invention of the present application is characterized by comprising two or more of the tenth means, and sequentially allocating instructions reserved by the third means to a plurality of the tenth means with a branch instruction as a delimiter. And

In addition, the third invention of the present application is a combination of the second means and the ninth means, instead of the second means, the sixth means, the seventh means, the eighth means and the ninth means. Means for transferring the values held in the plurality of second means to each other, and executing an execution result of an instruction at a branch destination which is predicted but not determined by a plurality of second means. It is characterized in that it is held in any of the means.

A fourth invention of the present application is characterized in that: by providing two or more of the eleventh means, it is possible to issue a plurality of instructions simultaneously.

(Operation) By taking such a means, while executing the instruction sequence before the branch instruction and the instruction sequence at the predicted branch destination at the same time as much as possible, the execution result by the predicted instruction at the branch destination before the decision is confirmed. Even if it is, it can be used as an operand. As a result, it is possible to suppress the delay of the instruction execution start due to the waiting for the determination of the branch instruction, thereby enabling high-speed processing.

(Embodiment) FIG. 1 is an apparatus configuration diagram showing an embodiment of the present invention.
In the figure, reference numeral 10 denotes an instruction storage means for storing an instruction to be processed. Reference numeral 20 denotes a register write reservation unit that reserves, in advance, writing to a register performed by the instruction obtained from the instruction storage unit 10 as an execution result. 30 is a register write reservation means 20
Is an instruction holding unit having a first-in first-out function capable of holding a plurality of instructions processed by the above, and holds an instruction sequence whose branch destination is determined and which is determined to be executed. Reference numeral 40 denotes an instruction issuing means for issuing an instruction held by the instruction holding means or an instruction which has been processed by the register write reservation means 20 and whose execution has not been determined. 50 is instruction issuing means
This is an operand access control means for adding control to the operand access performed by 40. Reference numeral 60 denotes an instruction executing means for executing the instruction issued by the instruction issuing means 40. Reference numeral 70 denotes a branch prediction destination instruction execution result storage unit that temporarily holds an execution result of an instruction whose execution has not been determined among the results output from the instruction execution unit 60. 80 is the instruction execution means 60
Is a register for holding an execution result of an instruction whose execution has been determined, among the results output from.

FIG. 2 shows a main part of the operand access control means 50. Reference numeral 510 denotes a register set by the register write reservation means 20 as a write history flag, which considers a block from an instruction branch to the next branch instruction as one block. Indicates whether there was. Reference numeral 520 denotes a register write reserved flag which is set by the register write reservation means 20 and indicates whether or not a write reservation has been made for the register in the block at the present time. Reference numeral 530 denotes an instruction issued flag set by the instruction issuing means 40, and indicates whether or not an instruction which is currently reserved for writing to the register in the block is issued. The register write history flag 510, the register write reserved flag 520, and the instruction issued flag 530 have the same format and have flags corresponding to each element of the register, as shown in FIG. And two types of flag sets for instructions not determined. In order to distinguish the two types of flag registers, the terms A side and B side are used. One block from the A side or the B side is assigned to one block from the instruction branch to the next instruction branch. This allocation is released at the end of all instructions included in the block, and can be allocated to the next block. Reference numeral 540 denotes a finalized instruction sequence flag indicating which side of the two types of flag sets, the register write history flag 510, the register write reserved flag 520, and the instruction issued flag 530, is for which instruction is finalized. In other words, it indicates which side of the currently executed A or B side is the instruction sequence whose execution has been determined. Thus, if the side to which the block is assigned matches the side specified by the fixed instruction sequence 540, it can be determined that the execution of the block is fixed. Reference numeral 550 denotes an operand read determination circuit that gives information to operand access performed by the instruction issuing means 40, and information of a read source that performs operand read from either the branch prediction destination instruction execution result storage means 70 or the register 80; Information on whether or not reading is permitted is created from the values of the register write history flag 510, the register write reserved flag 520, the instruction issued flag 530, and the fixed instruction sequence flag 540. FIG. 4 shows a flowchart for determining the read information. In FIG.
The register write history flag 510 is set to WH, the register write reserved flag 520 is set to WB, the instruction issued flag 530 is set to IB, the fixed instruction sequence flag 540 is set to FP, the block side is Blk, and the other side of the block is rBlk. The register number is represented by Reg. In particular, for the register write history flag 510, the register write reserved flag 520, and the instruction issued flag 530, for example, the "flag indicated by the register number of the flag set on the block side of the register write reserved flag 520" , WB (Blk, Reg).

In order to explain the contents of the present invention in the instruction processing device having the above-described configuration, first, an operation when processing an instruction that is determined to be executed will be described. The instruction is read from the instruction storage means 10, and writing to the register performed by the instruction as an execution result is reserved by the register write reservation means 20. In the reservation operation of register write reservation,
For both the register write history flag 510 and the register write reserved flag 520, the flag indicated by the write register number in the block side flag set is set. Of the flags set here, the register write history flag 51
0 is released at the end of the block, that is, when all instructions up to the next branch instruction are completed, and the register write reserved flag 520 is released when the instruction is completed. The instruction whose reservation has been completed by the register write reservation means 20 is
The instruction is held in the instruction holding means 30 and waits for an instruction to be issued. The instruction held in the instruction holding means 30 is accessed by the instruction issuing means 40 for operand access, and a successful instruction is transferred to the instruction executing means 60. In the operand access performed here, information on reading is received from the operand access control means 50. At this time, the operand access control means 50 makes a determination according to the flowchart of FIG. First, the block is compared with the determined instruction sequence flag 540 (step 101), and since they match, it is known that the block is determined to be executed. Then, the flag indicated by the read register number of the block side flag set of the instruction issued flag 530 is determined (step 102). If the flag is released, the operand access to the register 80 is permitted. . At the same time as issuing the instruction from the instruction issuing means 40, the flag indicated by the write register number in the block side flag set of the instruction issued flag 530 is set. The instruction issued from the instruction issuing means 40 performs the operation specified by the instruction in the instruction executing means 60, and generates an execution result. The execution result generated by the instruction execution means 60 is stored in the register 80, and the execution ends. At the end of the execution of the instruction, the flag indicated by the write register number in the block side flag set is canceled for both the register write reserved flag 520 and the instruction issued flag 530.

Next, an operation in the case of executing an instruction whose execution has not been determined and predicted by the branch prediction mechanism will be described.
The instruction is read from the instruction storage means 10, and writing to the register performed by the instruction as an execution result is reserved by the register write reservation means 20. In the register write reservation operation, the flag indicating the write register number on the block side is set in both the register write history flag 510 and the register write reserved flag 520. Of the flags set here, the register write history flag 510 is released when all instructions up to the next branch instruction are completed, and the register write reserved flag 520 is released when the instruction is completed. The instruction whose reservation has been completed by the register write reservation unit 20 performs operand access in the instruction issuing unit 40, and the instruction execution unit 60
Is forwarded to In the operand access performed here, information of a read source indicating whether the operand is read from the branch prediction destination instruction execution result storage means 70 or the register 80 and information of whether or not the read can be read are stored in the operand. Received from access control means 50. At this time, the fourth operand access control means 50
The determination is made according to the flowchart in the figure. First, the block is compared with the fixed instruction sequence flag 540 (step 10).
1) Since this does not match, it can be seen that the block is not determined to be executed. Next, the flag indicated by the read register number of the block side flag set of the register write history flag 510 is determined (step 10).
3) If the flag is cleared, the operand access is performed from the register 80 if the flag is cleared, and if the flag is set, the operand access is performed from the branch prediction destination instruction execution result storage means 70.
To the instruction issuing means 40. Further, based on the operand read source information, the operand access control unit 50 creates operand access permission information to be transmitted to the instruction issuing unit 40. That is, if the register
In the case of reading from the block 80, the flag indicated by the read register number in the flag set opposite to the block of the register write reserved flag 520 is determined (step 10).
4) If this flag is cleared, register 80
Access to the operand. If reading from the branch prediction destination instruction execution result storage means 70,
A flag indicated by the register number of the block side flag set of the instruction issued flag 530 is determined (step 105).
If this flag is released, access to the branch prediction target instruction execution result storage means 70 is permitted. At the same time as issuing the instruction from the instruction issuing means 40, the flag indicated by the write register number in the block side flag set of the instruction issued flag 530 is set. Instruction issuing means
The instruction issued from 40 performs the operation specified by the instruction in the instruction executing means 60, and generates an execution result. The execution result generated by the instruction execution means 60 is temporarily stored in the branch prediction destination instruction execution result storage means 70. At this point, it is considered that the instruction has been completed, and the flag indicated by the write register number on the block side is released for both the register write reserved flag 520 and the instruction issued flag 530.

Next, the operation when the branch destination by the branch instruction is determined and coincides with the predicted branch destination will be described. When the branch destination of the branch instruction is determined, the execution result temporarily stored in the branch prediction target instruction execution result storage means 70 is transferred to the register 80 after the execution of the instruction before the branch instruction is completed. After all transfers are completed, branch prediction destination instruction execution result storage means
Unlock all 70 elements. Register write history flag 510
Then, all the elements of the flag set defined by the fixed instruction sequence flag 540 are released. After that, the fixed instruction sequence flag 540 is inverted.

Next, the operation when the branch destination is determined by the branch instruction but does not match the predicted branch destination and the branch prediction fails will be described. When the branch prediction failure is detected, the instruction from the instruction storage unit 10 of the instruction of the branch prediction failure is stopped, and the execution of the instruction of the branch prediction failure already input to the instruction execution unit 40 is terminated. All elements of the branch prediction destination instruction execution result storage means 70 are released. Register write history flag 51
0, Register write reserved flag 520, Instruction issued flag
In all of 530, the determined branch destination instruction is input from the instruction storage 10 for releasing all elements of the flag set on the side opposite to the side defined by the determined instruction series flag 540, and execution is continued as an instruction whose execution is determined. .

Next, an operation example of the program shown in FIG. 5 will be described. It is assumed that the branch instruction in the program is predicted to be the one that does not cause a branch. Also, it is assumed that the fixed instruction series flag 540 indicates the A side as an initial value.
That is, from the first instruction to the next branch instruction, the A side is used from among the two flag sets of A and B in the register write history flag 510, the register write reserved flag 520, and the instruction issued flag 530. . First, in the first cycle, the instruction (1) is read from the instruction storage 10, and the register write history flag 510 corresponding to the write register r2 of the instruction (1) is read through the register write reservation means 20.
And the second flag on the A side of both the register write reserved flag 520 is turned ON. In the second cycle, the instruction (2) is read from the instruction storage means 10 and is passed through the register write reservation means 20 to the register write history flag 510 and the register write reserved flag 520 corresponding to the write register r4 of the instruction (2). The flag No. 4 on the A side of both is turned ON. At the same time, the instruction (1) is held by the instruction holding means 30. In the third cycle, the instruction (3) is read from the instruction storage means 10, but since the instruction (3) has no register write, the register write reservation means 20 does not make a write reservation. At the same time, the instruction (2) is held by the instruction holding means 30. At the same time, in the instruction issuing means 40, the instruction (1) reads the operands r0 and r1 and issues the instruction. At this time, the 0th and 1st flags on the A side of the instruction issued flag are checked, and since both are OFF, the operand access succeeds. When the instruction is issued, the second flag on the A side of both the instruction issued flags 530 corresponding to the write register r2 of the instruction (1) is turned ON. In the fourth cycle, the instruction (4) is read from the instruction storage means 10 and is passed through the register write reservation means 20 to the register write history flag 510 and the register write reserved flag corresponding to the write register r5 of the instruction (4). Turn on the No. 5 flag on the B side of both 520s. At the same time, the instruction (3) is the instruction holding means.
Held by 30. At the same time, the instruction (2) tries to read the operands r2 and r3 in the instruction issuing means 40, but the operand access fails because the second flag on the A side of the instruction issued flag is ON. Stay in the instruction issuing means 40. FIG. 6 shows a snapshot in the fourth cycle.

In the fifth cycle, the instruction (1) continues to execute the operation, the instruction (2) is kept in the instruction issuing means 40, and the instruction (3) is kept in the instruction holding means 30. The instruction (5) is read from the instruction storage means 10 and passed through the register write reservation means 20.
The B-side No. 6 flag of both the register write history flag 510 and the register write reserved flag 520 corresponding to the write register r6 of the instruction (5) is turned ON. Instruction (4) is
First, the numbers 0 and 3 on the B side of the register write history flag 510 corresponding to the read registers r0 and r3 of the instruction (4) are determined, and since both are OFF, the operand is read from the register 80. Then, No. 0 and No. 3 on the A side of the register write reserved flag 520 are determined. Since both are OFF, the operand access succeeds and the instruction issuing means 40 issues the instruction (4). In the sixth cycle, the instruction (6) is input from the instruction storage means 10. At the same time, in the instruction issuing means 40, the instruction (5) is changed to the operands r2 and r3.
However, since the second flag on the A side of the instruction issued flag is ON, the operand access fails and the instruction issuing means 40 remains. In the seventh cycle, the instruction (7) is about to be input from the instruction storage means 10, but
Since the instruction (6) remains in the register write reservation means 20, it cannot be input. There is no change in the eighth cycle. FIG. 7 shows a snapshot in the eighth cycle.

In the ninth cycle, the register 80 of the execution result of the instruction (1) is used.
Write to register, register write reserved flag 520
And the 2nd on the A side of the instruction issued flag is turned off. As a result, the operand access of both the instruction (2) and the instruction (5) in the instruction issuing means 40, which has been waiting for the instruction issued flag 2 on the A side to be turned off, succeeds. In the example, since only one instruction can be issued at a time, only the instruction (2) on the definite series side is issued. In the tenth cycle, issuance of the instruction (3) is attempted, but operand access fails because instruction # 2 of the instruction issued flag is turned ON by the instruction (2), and the instruction remains in the instruction issuing means 40. In the tenth cycle, the instruction (5) held in the previous cycle is issued. As a result, in the eleventh cycle, the instruction (6) is
Then, the instruction (7) proceeds to the register write reservation means 20. Further, the execution result of the instruction (4) is written into the branch prediction destination instruction execution result storage means 70, and the register write reserved flag 520 and the instruction issued flag 530 on the B side are turned off. As a result, the operand access to the instruction (6) in the instruction issuing means 40 succeeds as described below, and the instruction (6) is issued. That is, the register write history flag 510
Is turned on from the B-side No. 5 of the operand read, and it is known from the operand read branch prediction destination instruction execution result storage means 70 that the B-side No. 5 of the instruction issued flag 530 is turned off. Operand access is permitted. FIG. 8 shows a snapshot in the eleventh cycle.

No change occurs between the 12th and 14th cycles. In the 15th cycle, the register of the execution result of instruction (2)
A write to 80 occurs and the register write reserved flag 52
0 and the instruction issue flag 530 on the A side 4 are turned off. As a result, the instruction (3) in the instruction issuing means 40, which has been waiting for the A-side No. 4 of the instruction issued flag being turned OFF, is issued. In the 16th cycle, the instruction (2) and the 17th cycle
In the cycle, the execution result of the instruction (6) is written into the branch prediction destination instruction execution result storage means 70, and the register write reserved flag 520 and the instruction issued flag 530 on the B side are turned OFF. . Thus, in the seventeenth cycle, the instruction (7) in the instruction issuing means 40, which has been waiting for the B-side of the instruction issued flag to be turned off, is issued. No.
There is no change in 18 cycles. In the nineteenth cycle, the execution of the instruction (3) is completed and the predicted branch destination is determined.
Transfer to. At this time, in the branch prediction destination instruction execution result storage means 70, there are execution results r5, r6, and r7 by the instructions (4), (5), and (6), and the transfer is performed for these three. After the transfer, the branch prediction destination instruction execution result storage means 70 is released. Then, all elements of the register write history flag A are released, and the value specified by the fixed instruction sequence flag 540 is changed to A.
From the side to the B side. As a result, the A side can be newly used in the next 20th cycle.
Is input from the instruction memory 10. FIG. 9 shows a snapshot in the 20th cycle.

In the 21st cycle, the execution of the instruction (7) ends, and the predicted branch destination is determined. However, at this time, since no writing has occurred in the branch prediction destination instruction execution result storage means 70,
The transfer from the branch prediction destination instruction execution result storage means 70 to the register 80 is not performed. Then, all elements on the B side of the register write history flag are released, and the value specified by the fixed instruction sequence flag 540 is inverted from the B side to the A side. The instruction (8) is issued in the 21st cycle, ends in the 26th cycle, and the program ends. A time chart from the start to the end of the program is shown in FIG.

In the foregoing, the instruction processing process in the instruction processing device according to the present invention has been described.

Next, another embodiment of the present invention in which two instruction holding units 31, 32 are used instead of one instruction holding unit 30 in FIG. 1 will be described with reference to FIG.

FIG. 11 shows an embodiment of the instruction processing apparatus according to the present invention. In the drawing, the configuration is the same as that of the above-described embodiment of the instruction processing apparatus according to the present invention shown in FIG. 1 except that two instruction holding units 31 and 32 are provided. In this configuration, an instruction whose reservation has been completed by the register write reservation unit 20 is held in the instruction holding unit A or B with a branch instruction as a delimiter. For example, in the instruction sequence initially held in the instruction holding unit A, the instruction following the branch instruction is stored in the instruction holding unit B, and the instruction following the next branch instruction is stored in the instruction holding unit A. To keep. Thus, in the example of the program shown in FIG. 5, the instruction (7) could not be issued from the instruction storage 10 until the tenth cycle, but in the present invention using two instruction holding means, it can be issued in the sixth cycle. Become. Still another embodiment of the present invention when two registers are used will be described with reference to FIG.

The instruction processing apparatus according to the present invention shown in FIG.
2 and a transfer means 90 between them, except that the branch prediction destination instruction execution result storage means 70 is omitted, and has the same configuration as that of the above-described embodiment of the instruction processing apparatus according to the present invention shown in FIG. I have. In this configuration, the result obtained by the instruction execution means 60 is written in both the registers A and B if the result is due to the instruction belonging to the determined series, but if the result is based on the undetermined series. Are held in either the register A or the register B with the branch instruction as a delimiter. For example, when the result of a certain undetermined instruction sequence is held in the register A, the result of this sequence is stored in the registers A and B from the moment when the preceding branch prediction is successful and the instruction sequence is determined. Write to both. Then, the result after the instruction following the branch instruction is held only in the register B until the execution is determined, and the result of the instruction sequence is written into both the registers A and B from the moment the instruction sequence is determined. The result after the next instruction following the next branch instruction is held in the register A until execution is determined, and this is repeated thereafter. The inter-register transfer means 90 is provided with a plug register of the format shown in FIG. 3 called a register written flag, and when the result is written into only one of the registers in the above operation procedure, the corresponding side (ie, Then, the register write completion flag of the register number of the register A is turned ON. When the branch instruction that determines whether or not the instruction sequence can be executed branches to the successful prediction side, the register of the register number of the block whose register write completion flag is ON is replaced with the same register number of the opposite side. Copy to The register write completion flag is
F. On the other hand, when branching to the prediction failure side,
The register of the register number on the opposite side of the block whose register write completion flag is ON is copied to the same register number of the block side whose register write completion flag is ON. The register write completion flag is turned OFF after the copying. As a result, the execution result of the branch prediction destination is written to one register before the branch destination is determined, and when the branch is successful, the result is copied to the other side, and when the branch prediction fails, the value on the other side is copied. Restores the original value.

In the embodiment of FIG. 12, whether or not register reading is possible,
FIG. 13 shows a flowchart for determining which register should be read. The symbols used are the same as in FIG.

Next, the operation of the embodiment shown in FIG. 12 will be described with reference to the program shown in FIG. Only the operations of operand reading and execution result writing are different from those in the case of FIG. 1 described above, so only this part will be described. First, the instruction (1) is on the definite series side (FIG. 13, step
201), since the instruction for writing r2 is not being executed (step 204), the r2 on the A side is changed to the third according to the flow chart of FIG.
It is possible to read in a cycle. The instruction (1)
Is written in the registers on both sides since it is a definite series at the time of writing. Since the next instruction (2) is also on the definite sequence side, the operand is read from the register on the block side, that is, the A side according to the flowchart of FIG. At this time, since the preceding instruction (1) has already reserved the writing of r2 (that is, IB (Blk, Reg) is ON), the operand reading is suspended until the ninth cycle at which the instruction (1) ends. You.
The instruction (5) attempts to read r2 in the same manner as the instruction (2), but is on the undetermined side (FIG. 13, step 20).
1) Since the block has not been written to r2 (step 202), an attempt is made to read the operand from the other side of the block, that is, the register on the A side. However, since instruction (1) has already reserved writing of r2 (step 203), operand reading is suspended until instruction (1) ends (in the ninth cycle, instruction (2) is issued. Instruction (5) is issued in the tenth cycle). Further, since the instruction (5) is a sequence side that has not been determined at the time of writing, the result is written only to the block side, that is, the register on the B side. Similar operations are performed for other instructions.

Next, an embodiment in which two instruction issuing means are used will be described with reference to FIGS. 14 and 15. FIG. FIG. 14 shows an embodiment of the instruction processing apparatus according to the present invention. In the figure, two instruction issuing means 41 and 42 are provided, and a plurality of instructions can be issued simultaneously. To cope with this, operand access control means 150, instruction execution means 160, branch prediction destination instruction execution result storage means 170, The configuration is the same as that of the above-described embodiment of the instruction processing apparatus according to the present invention shown in FIG. FIG. 15 shows a main part of the operand access control means 150. In the figure, the configuration is the same as that of FIG. 2 except that each flag can be accessed simultaneously and two operand read determination circuits are provided.

Next, the operation of the embodiment shown in FIG. 14 will be described with reference to the program shown in FIG. Only the operation timing of the instruction issuing means differs from the case of FIG. 1 described above, so only this part will be described. In the ninth cycle, the execution result of the instruction (1) is written to the register 80, and the register write reserved flag 520 and the instruction issue completed flag A side are turned off. As a result, operand access of both the instruction (2) and the instruction (5) in the instruction issuing means, which has been waiting for the instruction issued flag to be turned off on the second side of the A side, succeeds. In the embodiment of FIG.
Since only one instruction can be issued, only the instruction (2) on the fixed sequence side is issued. However, in the embodiment shown in FIG. 14, since two instruction issuing means are provided and two instructions can be issued simultaneously. , Instruction (2) and instruction (5) in the ninth cycle
Issue both. The operation of other instructions is the same as in the embodiment of FIG.

Note that, in each of the embodiments of FIGS. 11, 12, and 14, the instruction processing device may be configured by appropriately combining them. That is, a plurality of instruction holding units A and B, registers
The instruction processing device may be configured to include at least two of A and B and instruction issuing means A and B.

(Effects of the Invention) As is apparent from the above description, according to the present invention, the instruction sequence before the branch instruction and the instruction sequence at the predicted branch destination are executed as simultaneously as possible, while the predicted branch destination before the decision is made. Can be used as an operand even if the execution result of the instruction is not used, the delay of the instruction execution start due to the waiting for the determination of the branch instruction can be suppressed, and high-speed processing can be performed.

[Brief description of the drawings]

FIG. 1 is an apparatus diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing an embodiment of the operand access control means in the figure;
FIG. 3 is a diagram showing a configuration of a register write history flag, a register write reserved flag, an instruction issued flag of FIG. 2, and a register write completed flag of the inter-register transfer means of FIG. FIG. 4 is a flow chart for determining read permission in the operand access control means of FIG. Fifth
The figure shows a program used to show an operation example. Sixth,
Figures 7, 8, and 9 are the program operation examples shown in Figure 5 respectively.
It is a snapshot of 4,8,11,20 cycles. FIG. 10 is a time chart of an example of the program operation according to FIG. FIG. 11 is an apparatus diagram showing an embodiment of the second invention of the present application. FIG. 12 is an apparatus diagram showing an embodiment of the third invention of the present application. FIG. 13 is a flow chart for determining read permission in the operand access control means of FIG. No.
FIG. 14 is an apparatus diagram showing an embodiment of the fourth invention of the present application, FIG. 15 is a diagram showing an embodiment of the operand access control means of FIG. 14, and FIG. FIG. In the figure, 10 is instruction storage means, 20 is register write reservation means, 30, 3
1, 32 are instruction holding means, 40, 41, 42 are instruction issuing means, 50 is operand access control means, 60 is instruction execution means, 70 is branch prediction destination instruction execution result storage means, 80, 81, 82 are registers,
90 is an inter-register transfer unit, 150 is an operand access control unit, 160 is an instruction execution unit, 170 is a branch prediction destination instruction execution result storage unit, 180 is a register, 510 is a register write history flag, 520 is a register write reserved flag, 530 is an instruction issued flag, 540 is a definite instruction sequence flag, 550 is an operand read determination circuit, 561 is a signal line that transmits branch information of a branch instruction, 562 is a signal line that transmits the end of each instruction, and 563 is an instruction register. 56, a signal line for transmitting write reservation information of
4 is a signal line for transmitting the issue information of each instruction, 565 is a signal line for transmitting whether the operand can be read, 1510 is a register write history flag, 1520 is a register write reserved flag, 1530 is an instruction issued flag, and 1540 is a definite instruction sequence. This is a flag.

Claims (4)

(57) [Claims] In a branch prediction method for predicting a branch destination address without waiting for a branch destination to be determined by a branch instruction, a first means for storing an instruction to be processed and a register for writing an execution result of the instruction. Means, a third means for reserving in advance a write to a register performed by the instruction obtained by the first means as an execution result, and holding the instruction reserved by the third means and issuing the instruction. Fourth means for executing, instructions for executing an instruction issued by the fourth means, and a predicted and fixed state disposed between the fifth means and the second means. Temporarily holds the execution result of the instruction at the branch destination that has not been taken
Means, the seventh means for transferring the execution result held by the sixth means to the second means, and the fourth means transfers the execution result held by the sixth means as an operand. Eighth means for reading, and ninth means for the fourth means to read the execution result held by the second means as an operand, wherein the fourth means further comprises: Tenth means for holding an instruction sequence before an instruction, eleventh means for issuing the instruction held by the tenth means and the instruction reserved by the third means to the fifth means, By receiving the register write reservation by the third means, the history information of the instruction issuance performed by the eleventh means, and the branch destination determination information by the fifth means, the operand access performed by the eleventh means is Control An instruction processing apparatus comprising: a twelfth means for obtaining a predicted instruction and executing a further instruction using a predicted execution result of the instruction at a branch destination before the determination. 2. The apparatus according to claim 1, further comprising at least two of said tenth means,
2. The instruction processing apparatus according to claim 1, wherein instructions reserved by said means are sequentially distributed to a plurality of tenth means with a branch instruction as a delimiter. 3. In place of the second means, the sixth means, the seventh means, the eighth means and the ninth means, two or more sets of the second means and the ninth means are provided. And means for transferring the values held in the plurality of second means to each other, and executing an execution result of an instruction at a branch destination which is predicted but not determined by any of the plurality of second means. 2. The instruction processing device according to claim 1, wherein the instruction processing device stores the instruction. 4. The instruction processing apparatus according to claim 1, wherein a plurality of instructions are issued simultaneously by providing two or more of said eleventh means.