JP2813182B2 - Multiprocessor computer multifunction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a multiprocessor computer multifunction device, and particularly to a system requiring high reliability, and
The present invention relates to a multiprocessor / computer multifunction peripheral suitable for a system in which data communication frequently occurs between computers.

[Conventional technology]

Attempts to increase the throughput of the entire system or improve reliability by combining a plurality of computers have been widely performed. In such a system, some communication means is required on the computer side. In the systems disclosed in JP-A-58-18760 and JP-A-58-137065, a global shared memory shared by each computer is provided. Communication between computers is being performed. Further, JP-A-57-189257, JP-A-62-10
In the system disclosed in No. 59, only a memory is physically provided for each computer.However, by making the contents always match, a memory commonly accessed as a result is formed to perform the above communication. ing.

[Problems to be solved by the invention]

In the above-mentioned prior art, in a system in which a global shared memory is physically provided, when two or more computers access the memory at the same time, one of the computers is kept waiting until the other access is completed, and the overall throughput is reduced. There was a problem. In general, a memory commonly accessed by each computer is often placed at a distance from each computer. For this reason, the wiring delay time increases, and the access speed itself decreases, which is an obstacle to speeding up the calculation.

On the other hand, in a system in which the contents of memories provided for each computer always match, each computer has a single processor. When each computer is a multiprocessor, a shared memory by multiple processors is provided for each computer.However, such matching control between shared memories is not taken into consideration. Was not applicable. For this reason, for example, a multi-processor computer complex is configured, and each multi-processor computer writes information in the middle of processing in their shared memory, and when one multi-processor computer fails, the other multi-processor computer fails. It has been difficult to realize a highly reliable and high-speed system in which information is read from the processor computer and processing is continued.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor-computer multifunction device capable of exchanging data between multiprocessor computers at high speed.

[Means for solving the problem]

It is an object of the present invention to provide a multiprocessor computer composite device in which a plurality of multiprocessor computers are connected via a bus, wherein each multiprocessor computer comprises: (a) a global area (global shared memory area) and a local area (local shared memory area) (B) a plurality of processors, each having a cache memory, and when accessing the local area of the shared memory provided in its own multiprocessor computer, a cache memory attached to itself. And a plurality of processors performing direct access without using the cache memory when accessing the global area, and (c) between the cache memories included in the respective processors in the multiprocessor computer of itself. And means to match d) When any of the processors writes data to the global area, the processor writes data to the global area of the shared memory of its own multiprocessor computer and shares the data in another multiprocessor computer via the bus. And memory control means for writing the data also in the global area of the memory.

(Operation)

When accessing the shared memory, the processor outputs, at the same time as the address, information (address space) indicating whether the access is to the global shared memory area.

When the processor reads data from the shared memory, the data may be read from the shared memory of the computer to which the processor belongs, whether or not the data is in the global shared memory area. It has no effect on other computers. Therefore, there is no read contention between the computers for the shared data, and the data is read from the shared memory of the computer to which the computer belongs.

When the processor writes data to shared memory,
The operation is different for the global shared memory area and when it is not. The memory control means connected to the shared memory determines whether the access is the global shared memory area by looking at the address space signal output from the processor. When not in the global shared memory area, the data is independently written into the shared memory of the computer to which the processor belongs, similarly to the reading. When writing to the global shared memory area, the matching bus connected between the memory control means of each computer is dedicated, and then simultaneously writing to the shared memory of all computers through the matching bus,
Match the content.

In addition, RMW (Read-Mod
ify-Write) instruction is possible. The RMW reads the memory, manipulates the read data, and writes the result to memory.
These instructions are executed continuously without interruption by the RMW.
When this instruction is issued, it first occupies the match bus and continues to occupy the match bus until the RMW has completed. As a result, interruption by the RMW of another processor can be prevented.

Further, since the access to the local area is performed via the cache memory, high-speed access is possible. Since the access to the global area is directly performed without using the cache memory, it is not necessary to perform the matching process between caches of different computers. .

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is an overall configuration diagram of an embodiment of a multiprocessor computer multifunction peripheral according to the present invention. In the figure, multiprocessor computers (hereinafter simply referred to as computers) 11 to 13 are connected to each other by a matching bus 14. The configuration of computer 11 (as well as others)
Processors 114 to 116 are connected by a multiprocessor bus (hereinafter simply referred to as a bus) 113 and a storage control unit 112 (SCU; hereinafter simply referred to as a control unit).
, The shared memory 111 is shared.

The shared memory 111 stores programs executed by the processors 114 to 116 and data processed by the programs. The shared memory 111 is provided with a global shared memory area which is a feature of the present invention.
The shared data is also stored in the 12, 13 processors. On the other hand, a storage part of data accessed only by the processor of the computer 11 is called a local shared memory area.

Hereinafter, the operation of the memory access will be described. First, at the time of reading, the control unit 112 receives a read request from one of the processors 114 to 116 through the multiprocessor bus 113, reads data from the shared memory 111, and passes it to the requesting processor.

On the other hand, the operation of writing to the global shared memory area differs from that of writing to the local shared memory area.
When the processor requests a write, an address space (ASP), which is information on which address space the address belongs to, is output together with the address. As shown in Table 1, "001" indicates that the access is to the local shared memory area, and "110" indicates that the access is to the global shared memory area. Except for these and “000”, I / O of disk etc. in other cases
It is shown assuming an address space related to the bus to which the device is connected. However, since these are not directly related to the present invention, the description is omitted.

The control unit 112 determines whether to write to the global shared memory area or the local shared memory area by looking at the address space. When writing to the local shared memory area, data is written only to the shared memory 111 as in reading. When writing to the global shared memory area, the control unit 112 occupies the matching bus 14 and then broadcasts data to be written to all the control units of the computers 11 to 13 and write destination addresses through the matching bus. Each control unit writes the received data to the shared memory of the respective computer, and thus the contents of the data in the global shared memory area are matched between the computers.

RMW TA Motorola Microprocessor 68030
These instructions are well known as S instructions and CAS instructions. Processor 11
The operation when the RMW 4 executes the RMW on the shared memory 111 will be described. During the execution of the RMW, the processor outputs a signal to the bus 113. The control unit 112 detects this signal and knows that the command is RMW. Further, it is determined from the address space whether the RMW instruction is for the local shared memory area or the global shared memory area.

First, when executing the RMW instruction on the local shared memory area, the processor 114 first outputs the RMW signal and outputs the RMW signal.
Occupies 113. This is to prevent the other processors 115 and 116 from accessing the same address as the RMW during the execution of the processor 114. Then processor 11
4 outputs the address of the first read of the RMW and the address space "001" to the bus 113. The control unit 112
When it is known from the address space that the RMW is for the local shared memory area, data is read in the same procedure as that for reading data from the shared memory. The operation of the next data is performed in the processor 114, and the bus 113 continues to be occupied during this operation. The last write is the same as the write to the local shared memory area described above. After the writing is completely completed, the processor 114 releases the bus 113.

Next, the processor 114 performs RMW on the global shared memory area.
Is executed until the processor 114 outputs the read address and the address space “110” to the bus 113, as in the case of the local shared memory area. When the control unit knows that the RMW is for the global shared memory area, it uses signal line 220 to occupy match bus 14. This is to prevent the processors of the computers 12 and 13 from executing the RMW on the global shared memory area simultaneously with the processor of the computer 11. Data reading and operation are the same as in the local shared memory area. During this time, the matching bus 14 is continuously occupied. The writing is the same as the writing to the global shared memory area described above. After the writing is completed, the matching bus 14 and the bus 113 are released.

Next, a disconnection operation such as a backup operation when a failure occurs will be described. One computer breaks down,
When you want to operate one computer separately from another computer, such as when maintaining a failed computer while continuing processing of another computer, or when developing or testing a program using one computer, is there. In this case, the control unit 11
2 disconnects the signal line 220. As a result, the connection with the matching bus 14 is cut off, so that even when writing or RMW is executed in the global shared memory area in the computer, the control unit performs the same processing as in the local shared memory area. That is, the computer can be operated in a disconnected state.

When the disconnected computer is reconnected to another computer, the contents of the global shared memory area of the computer are different from those of the other computers, and therefore, it is necessary to match the contents. This matching operation will be described assuming that the computer 12 has been disconnected. First, one of the processes of the computer 12 makes a request to one of the processors of the computer 11 or 13 to copy the contents of the global shared memory area by interruption.
Assuming that the processor 114 has received the interrupt, the processor 114 starts a process of copying the global shared memory area. This process sequentially executes the next RMW for the global shared memory area. The RMW is an instruction for reading data from an address or writing the read data back to the same address. When the RMW is executed, the data read from the shared memory 111 is written to the shared memory of all the computers 11 to 13, so that the data is copied to the separated shared memory of the computer 12. The use of RMW means that if a combination of normal read and write is used, when the data read is completed and the write is not yet performed, the other processor updates the address content of the read data. It is because there is a possibility that it will be.

By the operation described above, data communication between each computer can be performed via the global shared memory area, and a complex of multiprocessor computers can be realized. The configuration and operation of each unit for realizing it are as follows. explain. FIG. 2 shows a configuration of a storage control unit (control unit). In the figure, the signal line 200 is connected to the multiprocessor bus, the signal line 210 is connected to the shared memory 111, and the signal line 220 is connected to the matching bus 14. The write buffer 23 is a first-in first-out buffer (queue) for speeding up writing to the global shared memory area, and includes a data queue 232 for temporarily storing write data, an address queue 233 for temporarily storing write destination addresses, and It consists of a buffer controller 231 (BC) that controls both queues. In addition, various buffers 24, 25, 27, 36, 37, selectors 30 to 34, decoder 2
6, a flip-flop 28, an arbitration circuit 29, and a switch 35 are used.

At the time of reading from the local shared memory area, the processor sets the address space 202 to “001” from the bus 113 and
“1” indicating readout of R / W signal 203, memory access request
204 is turned on to “1”, and a read address is given to the address 205. Decoder 26 has address space 202 and R / W signal
The contents of 203 are decoded, and it is determined that the reading is of the local shared memory area, and the selectors 31 to 34 select the left input through the arbitration circuit 29. As a result, the R / W signal 203, the access request 204, and the address 205 are sent to the shared memory 111 as signals 212, 213, and 215, and reading is performed. However, at this time, it is assumed that no address request has been input from the matching bus 14 to the arbitration circuit 29. The data 211 read from the shared memory 111 is output as data 201 via the buffer 24 and the selector 30, and is sent to the processor which has output the request via the bus.

When reading from the global shared memory area, the address space 201 becomes "110", but the operation is almost the same as reading from the local shared memory area. However, in this case, data previously written to the same address may not be written to the shared memory 111 yet, but may be stored in the write buffer 23. For this, the address to read
If 205 exists in the address queue 233, the corresponding data is sent from the data queue 232 to the selector 30, and
At the same time, the selector 30 receives a signal from the controller 231.
To the right input. This operation allows buffer 23
The desired data can be read out without waiting for the data in the shared memory 111 to be written.

When writing to the local shared memory area, the processor sets the address space 202 to “001” and sets the R / W signal 20
3 is set to “0” indicating writing, the memory access request 204 is turned on, the write destination address 205 is sent out, and then the write data 201 is sent out. Similarly to reading from the local shared memory area, the selector 31 is instructed by the instruction of the decoder 26.
34 selects the left input, and the signals and data from the processor are shared as the signals and data 212 to 215 by the shared memory 11.
Sent to 1 for writing.

Writing to the global shared memory area is the same as that for the local shared memory area except that the address space 202 from the processor is "110". decoder
26 inputs the address space 202 and the R / W signal 203,
When it is determined that the access is to write to the global shared memory area, the selectors 31 to 34 send the address and data to the write buffer 23 without sending them directly to the shared memory.
And the buffer controller 231. When the data 201 and the address 205 are input to the data queue 232 and the address queue 233 in this way, the buffer controller 231 outputs a matching bus use request 224 to occupy the matching bus 14. If the matching bus can be occupied, a matching bus use permission 225 is obtained. This causes the controller 231 to queue
The write data and the write address are output to the bus 14 via the switch 35 from the 232 and 233 via the switch 35, and the write signal 223 is output.
Are also output to the matching bus 14. The following operation is performed simultaneously for all the control units of the computers 11 to 13. That is, the address, data, and write signals output to the matching bus 14 are input to the corresponding control unit as data 221, address 222, and write signal 223. The write signal 223 controls the selectors 31 to 34 through the arbitration circuit 29, and switches the selectors 31 to 34 to input the right signal. Thereby, the address 221 and the data 222 are sent to the shared memory 111 and writing is performed.

Next, the execution of the RMW instruction for the local shared memory area is the same as the case where mere reading and writing are continued, and the operation of the control unit is only executed in order to perform these operations.

The runtime behavior of RMW for the global shared memory area is
First read, second data operation, and last write. First, data read from the memory is the same as data read from the global shared memory area except that the RMW signal 206 is input from the processors 114 to 116. The RMW signal 206 is input until the RMW ends. Upon receiving the RMW signal 206, the buffer controller 231 occupies the matching bus in the same manner as writing to the global shared memory area. The subsequent reading operation is the same as reading from the global shared memory area. Since the next data operation is performed inside the processor, the control unit only continues to occupy the matching bus 14. The last write is the same as a write to the global shared memory area, but the match bus 14 continues to occupy until the queues 232,233 in the write buffer 23 are empty. this is,
Matching bus 14 with write data accumulated in buffer
Is released, other processors may perform an RMW to the same address before the data is written to shared memory.

Finally, the operation of the control unit when the computer 11 is disconnected from the matching bus 14 will be described. The disconnection is performed by one of the processors 114 to 116 inverting the flip-flop 28 via the bus 113. That is, when the flip-flop 28 is inverted, the switch 35 turns off all the signal lines 220, and disconnects the computer 11 from the matching bus 14. At the same time, when flip-flop 28 is inverted, decoder 26 treats access to the global shared memory area as it would access the local shared memory area.

FIG. 3 is a block diagram of one of the processors 114 to 116 shown in FIG. 1, and includes a central processing unit (CPU) 120, an address converter (AT) 121 for converting a logical address to a physical address, and a cache memory 122. ing. The contents of the signal line 300 correspond to the signal line 200 in FIG. 2, but in addition, a signal 305 indicating that the cache memory is updated in order to match the cache memory between the processors.
And a signal 306 indicating that the cache memory has the data of the address currently output to the bus 113.

The address converter 121 converts a logical address output by the central processing unit 120 into a physical address, and also calculates an address space (ASP) from the logical address. The cache memory 122 is a high-speed memory, and stores data of the shared memory 111 recently accessed by the central processing unit 120 and its physical address. When the stored physical address is accessed again, the cache memory is accessed instead of the shared memory. In a multiprocessor computer, different cache memories may have different data for the same address. Many methods for solving this problem are known, and in this example, matching is performed by signals 305 and 306.

However, since it is not possible to guarantee cache memory consistency between computers, data in the global shared memory area is
It is not stored in the cache memory 122.

RMW instruction also uses shared memory without using cache memory 122
Access 111 directly.

〔The invention's effect〕

According to the present invention, if the intermediate information of each multiprocessor computer is stored in the global shared memory area, which is a common area, when one multiprocessor computer fails, the non-failed multiprocessor computer will Since the processing can be continued by reading the intermediate information of the multiprocessor computer, there is an effect that a highly reliable computer system can be realized, and parallel processing can be performed between the multiprocessor computers if the common area is used as a data transfer means. This is effective for speeding up the calculation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a multiprocessor computer multifunction peripheral according to the present invention, and FIGS. 2 and 3 are diagrams showing specific embodiments of respective parts applied to the present invention. 11 to 13 Multiprocessor computer, 14 Matching bus, 23 Write buffer, 26 Decoder, 28
... flip-flops, 31-34 ... selectors, 35 ... switches, 111 ... shared memory, 112 ... storage control units, 113 ... multiprocessor buses, 114-
116: Processor, 121: Address converter, 122:
Cache memory, 120 Central processing unit.

Continuation of the front page (72) Inventor Tadaaki Bando 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-563 (JP, A) JP-A-53-104138 (JP) JP-A-59-22154 (JP, A) JP-A-63-239551 (JP, A) JP-B-63-26903 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB Name) G06F 15/16

Claims (1)

(57) [Claims] 1. In a multiprocessor computer multi-function apparatus in which a plurality of multiprocessor computers are connected via a bus, each multiprocessor computer comprises: (a) a shared memory having a global area and a local area; Processors each having a cache memory, and when accessing the local area of the shared memory provided in its own multiprocessor computer, access is performed using a cache memory attached to the processor, and the global area is accessed. A plurality of processors performing direct access without using the cache memory when accessing the cache memory; (c) means for matching the cache memories included in the processors in the multiprocessor computer itself; and (d) Any of the processors is in the global region When writing data, a memory control that writes data to the global area of the shared memory of the own multiprocessor computer and also writes the data to the global area of the shared memory of another multiprocessor computer via the bus A multiprocessor computer composite device comprising: