JP2808303B2 - IC device test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC device test apparatus, and more particularly, to an IC device test apparatus capable of simultaneously testing a plurality of IC devices.

[Conventional technology]

With the dramatic improvement in integrated circuit manufacturing technology, various IC devices have been put into practical use. Recently, significant demand for IC cards is also expected. Since such IC cards and other IC devices are products having extremely complicated functions, strict tests must be performed before shipment. As a conventional general test method, a test data consisting of a predetermined logical pattern is given to a device as an input signal, and data output from the device in accordance with the test data is compared with logically expected pattern data. The method is adopted. As a result of the comparison, if the two match, it can be determined that the test has passed, and if they do not match, it can be determined that the test has failed.

[Problems to be solved by the invention]

However, the conventional IC device test apparatus has a problem that only one device can be tested at a time. This is based on the reason that it is difficult to develop an apparatus for testing a plurality of devices at the same time, even when trying to test a plurality of devices simultaneously, because the timing of response output from the devices differs for each device. For devices such as IC cards,
A plurality of memories each composed of a capacitive element are formed, and even if a plurality of devices are operated with the same clock, a difference occurs in the time for accessing these memories for each device.

As described above, in the conventional IC device test apparatus, a test is performed for each device. However, this is a great obstacle in a manufacturing process of an IC card or the like which requires cost reduction by mass production.

Accordingly, an object of the present invention is to provide an IC device test apparatus capable of simultaneously testing a plurality of devices.

[Means for solving the problem]

A first invention of the present application is an IC device test apparatus, comprising: a data supply unit that supplies a plurality of n pieces of IC device test data; and n data supply units that detect that data according to the test data is output from each IC device. An output detection unit; a memory for storing data for each device output from each IC device independently for each device; and n addresses for accessing the data for each device with respect to this memory. And n comparison units for checking whether data for each device read from the memory matches predetermined expected data. Further, a corresponding output detection unit detects an output. A write counter that starts counting at a predetermined cycle from the time point, a read counter that counts at a predetermined cycle from the time point when all of the n output detection units detect the output, A write function provided in each address section to write output data from a corresponding IC device to the memory at a predetermined cycle according to the address indicated by the write counter, and reading data from the memory at a predetermined cycle according to the address indicated by the read counter And a reading function.

According to a second aspect of the present invention, in the above-described IC device test apparatus, a data input unit for inputting test data, a check code generating unit for generating a check code to be added to the input test data, A data supply unit is constituted by a parallel / serial conversion unit that converts the data into serial data composed of codes, adds the generated check code thereto, and outputs the result.

According to a third invention of the present application, in the above-described IC device test apparatus, a memory having n data development areas is provided in a device supply unit, test data is input to one of the data development areas, and the test data is input to the memory. A function of copying to another data development area is provided, and test data can be supplied to n IC devices from each of the n data development areas.

(Operation)

According to the first aspect of the present invention, data output from each IC device is temporarily stored in the memory independently. That is, when data is output from an IC device, a write counter corresponding to the device starts counting, and output data is sequentially written to an address corresponding to the count value of the write counter. Then, all the read counters to which data has been output from all the IC devices start counting, and data is read from the address corresponding to the count value of the read counter. After all,
Even if the timing to start outputting data differs for each IC device, the data from the device that started output earlier is temporarily stored in memory, and the data is read all at once when the slowest device starts output. Will be For this reason, simultaneous testing of a plurality of devices becomes possible.

According to the second aspect of the present invention, the data supply unit of the above-described test apparatus has a function of adding a check code to the test data and a function of converting the test data into serial data composed of a binary code. Become like
Therefore, it is possible to cope with a case where an IC device requests serial data as test data.

Further, according to the third aspect of the present invention, a memory having n data development areas is provided in the data supply unit of the above-described test apparatus. In addition, the test data input to one data development area is copied to another data development area. Therefore, the operator can input the same test data to n IC devices all at once simply by inputting one set of test data.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. FIG. 1 is a block diagram showing a configuration of an IC device test apparatus according to one embodiment of the present invention. This embodiment is specifically an apparatus for testing an IC card. Here, for convenience of explanation, an apparatus capable of simultaneously performing tests on three IC cards will be described. However, in practice, it is more efficient to simultaneously perform tests on eight or more IC cards. It is.

This device is composed of three large blocks: a data supply unit 10, a device mounting unit 20, and an output data processing unit 30. The data supply unit 10 includes a data input unit 11 for inputting data provided by an operator, a data conversion unit 12 for converting the input data, and a data expansion unit 13 for expanding the converted data into data for three devices. ing. Three IC cards A, B, and C are mounted on the device mounting section 20, and test data developed by the data developing section 13 is given to each IC card. The response output from each IC card is processed in the output data processing unit 30 for each device. For this reason, three processing systems are prepared in the output data processing unit 30. One processing system includes an output detection unit 31, an address unit 32, a storage unit 33, and a comparison unit 34. In the drawing, A, B, and C are assigned to the codes of these components for each processing system. It is additionally shown. In addition, in addition to the above, an AND gate 35 having a logical input of the output from the output detection units 31A, 31B, 31C is provided. The basic configuration of the IC device test apparatus has been described above. And the operation thereof will be described together. This device has a function of simultaneously performing tests on three IC cards as described above. First, it is necessary to set three IC cards in the device mounting section 20 before starting the test. The device mounting section 20 has a function of connecting input / output electrodes to external terminals of each of the IC cards while supporting and fixing the IC mounting sections at predetermined positions of the three IC cards. The input / output electrodes are connected to the data developing unit 13 and the output detecting unit 31, and the test data given from the data developing unit 13 is input to the IC card, and is output from the IC card in response to the test data. It has a function of giving data to the output detection unit 31. If a transport mechanism is provided in the device mounting section 20, a test can be performed for every three cards while transporting a large number of IC cards.

The operator inputs test data and expected data from the data input unit 11. Here, the test data is
The test pattern data to be given to the IC card, and the expected data is an output pattern expected when the test pattern is given to the IC card and the IC card is normal. For example, as shown in FIG. 2, these data are given in hexadecimal. In this example, if "B1" is given to the IC card as test data, "D4" will be output if the IC card is normal.

As described above, the test data and the expected data input by the data input unit 11 are converted by the data conversion unit. The reason why such data conversion is necessary is that the IC card has only one data line for input and output, and can only exchange data by serial data composed of binary codes. On the other hand, the operator uses parallel data which is convenient for input (in this case, as shown in FIG. 2).
Hexadecimal), and give each data. Therefore, parallel data (hexadecimal) is converted to serial data (2
Hex). FIG. 3 shows a data converter.
12 is a block diagram showing the internal configuration of Twelve. Data input section 11
Are supplied to the check code generation unit 121, where a check code is generated. Subsequently, the parallel data is converted to a parallel / serial converter.
At 122, it is converted to serial data. That is, a hexadecimal number as shown in FIG. 2 is converted into a binary number. Here, the generated check code is added to the converted data. In this way, the serial data with the check code is output. In addition,
Information necessary for conversion is set in the conversion information setting section 123, and the check code generation operation and the parallel / serial conversion operation are performed based on the information set here. For example, information such as the number of clocks for each bit, the data transmission order (whether to transmit from MSB or LSB), selection of vertical parity, and check code generation method (CRC, horizontal parity, etc.) are set.

Subsequently, the data developing unit 13 performs data developing for the three IC cards. The data expanding section 13 is provided with a memory having three data expanding areas, and the serial data output from the data converting section 12 is input to one of the data expanding areas, and then is transferred to another data expanding area. Copied to the data development area. This operation is specifically described as shown in FIG. In the figure, 13A, 13B, and 13C indicate each data development area. Now, for example, assuming that the parallel data "B1" given by the operator is converted into serial data "10110001", this serial data is input to the data development area 13A in the data development unit 13 and temporarily stored. You. Thereafter, the same data is copied to the other data development areas 13B and 13C, and the single data is developed into three systems. When the data development is completed, the same test data is simultaneously provided to each IC card of each system. Note that the expected data input by the operator is similarly converted into serial data by the data conversion unit 12 and then converted into the data expansion unit.
It is developed into three systems at 13. The expanded expected data is given to the comparison units 34A, 34B, 34C, respectively.

Now, the IC cards A, B, and C simultaneously input the developed test data and start arithmetic processing according to a predetermined logic.
The resulting data is output. As described above, the timing at which this data is output differs for each IC card. The output detection unit 31 has a function of detecting that data has been output from the IC card.
In the IC card of this embodiment, the output terminal of the IC card is in the high impedance state during the arithmetic processing, and the voltage detected by the output detection unit 31 is an intermediate voltage between the high level and the low level. When the IC card starts outputting data, it is designed to always output low-level data as the first bit as a start bit. Therefore, the output detection unit 31 can detect that the IC card has started output by detecting the low-level data. For example, when a voltage as shown in FIG. 5 is output from the IC card, it is detected at the moment indicated by the arrow S that the IC card has started outputting data. The bit following the first start bit is output data (in this example, “11010100...”).

When the output detection unit 31 detects the data output from the corresponding IC card, the output detection unit 31 supplies a signal indicating that to the AND gate 35. In the AND gate 35, the AND condition is satisfied when all the output detection units 31A to 31C detect the data output. When the AND condition is satisfied, a signal indicating that is provided to all the address units 32A to 32C. The operation in this case will be described later.

The data output from the IC card is output to the output detector
Through 31, it is given to the address section 31. That is, a signal as shown in FIG. The address section 32 is provided with a write counter and a read counter. The write counter starts counting when output data from the IC card is given. Then, writing to the storage unit 33 is performed based on the count value. The count of the write counter is performed at a predetermined cycle. Generally, when the period of one bit of the output data shown in FIG. 5 is D, the counting should be performed at a period of about D / 512. In this case, for 1-bit data,
512 tests will be performed. However, here, for convenience of explanation, the counting cycle of the counter is a one-bit cycle D.
The following operation will be described by taking as an example a case in which. That is, only one test is performed on 1-bit data. Therefore, when the output data as shown in FIG. 5 is obtained, "110101"
The data "00 ..." is written into the storage unit 33 bit by bit.

So, to make the explanation easier, IC card A
The output from the IC card B is obtained when the output from the IC card B is obtained first, and then the output from the IC card B is obtained when the time D has elapsed, and the operation when the output from the IC card C is obtained when the time D has elapsed thereafter. Think. As a result, the output data of the IC card B is delayed by 1 bit (time D) and the output data of the IC card C is 2 bits (time D) as compared with the output data of the IC card A.
2D) You are late. Here, it is assumed that the output of each IC card is data as shown in FIG. First, when the output detection unit 31A detects an output from the IC card A, data “1” is given to the address unit 32A, and the write counter WA starts counting. Then, this data “1” is written to the storage unit 33A. Here, the states of the data in the storage units 33A to 33C are shown in FIGS.
This is shown in a table as shown in FIG. A, B, C in column of table
Correspond to the storage units 33A, 33B, 33C, respectively, and 1 to
Reference numeral 6 corresponds to an address in each storage unit.
Assuming that the write counter starts counting from 1, the first data "1" from the IC card A is written to the address 1 indicated by the write counter WA in the storage unit 33A. FIG. 6A shows this state. The symbol “W” at the right shoulder of the written data “1” indicates that this data has just been written. Since the other IC cards B and C have not yet output data, the columns B and C of the table are still blank.

Now, when the time D elapses, the IC card B starts to output data. Therefore, the write counter WB in the address section 32B starts counting from 1. Therefore, the first data “1” from the IC card B is written to the address 1 indicated by the write counter WB in the storage unit 33B. On the other hand, IC
The card A outputs the second bit “1”, and the count value of the write counter WA in the address section 32A is “2”. Therefore, the second bit “1” of the IC card A is written to the address 2. This state is shown in FIG. 6 (b).

Further, when the time D elapses, the IC card C starts to output data. Therefore, the write counter WC in the address section 32C starts counting from 1. Therefore, the first data “1” from the IC card C is written to the address 1 indicated by the write counter WC of the storage unit 33C. On the other hand, the IC card B outputs the second bit “1”, and the count value of the write counter WB in the address section 32B is 2.
Therefore, the second bit “1” of the IC card B is written to the address 2. The IC card A outputs the third bit “0”, and the count value of the write counter WA in the address section 32A is three. Therefore, IC card A
Is written to address 3.
This state is shown in FIG. 6 (c).

By the way, at this point, since all the IC cards have started to output data, the AND condition of the AND gate 35 is satisfied. When the address sections 32A to 32C are notified of the satisfaction of the AND condition, the read counters RA, RB, and RC start counting from 1 at a time, and the read operation starts. In practice, this read operation follows the aforementioned write operation.
That is, the address section 32 performs the writing operation in the first half cycle, and performs the reading operation in the second half cycle. Since the count values of the read counters RA, RB, and RC are all 1, the data stored at the address 1 of the storage units 33A, 33B, and 33C are read all at once, and the comparison units 34A, 34B, and 34C are read.
Given to. This state is shown in FIG. 6 (d). Here, the symbol "R" at the right shoulder of the data "1" stored at the address 1 indicates that this data is the data that has just been read. Eventually, the write as shown in FIG. 6C is performed in the first half cycle, and the read as in FIG. 6D is performed in the subsequent second half cycle.

By the way, when the time D further elapses, writing as shown in FIG. 6E is performed in the first half cycle,
It can be easily understood that the read operation as shown in FIG. As a result, the output data is supplied to the comparison unit 34 in synchronization with each bit. As described above, the comparison unit 34 is provided with the expected data developed by the data development unit 13, so that the IC
An operation of comparing output data from the card with the expected data is performed. As a result of the comparison, if the two match, the IC card can be determined to be passed, and if not, the IC card can be determined to be rejected.

As described above, one embodiment illustrating the present invention has been described, but the present invention is not limited to this embodiment. As described above, this embodiment is an apparatus for testing three IC cards at the same time. However, an apparatus for simultaneously testing an arbitrary number of IC cards such as eight or sixteen can be realized. . Further, it is preferable that the counting cycle of the counter be shorter than the one-bit cycle D of the output data (for example, D / 512 as described above) so that a more strict test is performed. Here, the embodiment has been described as an IC card test apparatus, but the present invention can be applied to devices other than the IC card.

〔The invention's effect〕

As described above, according to the present invention, in an IC device test apparatus, test data is provided to a plurality of IC devices and the output corresponding thereto is detected according to the slowest device, so that simultaneous testing of a plurality of devices is possible. become.

Further, since a function of converting test data into serial data composed of binary codes is provided, it is possible to cope with a case where an IC device requests serial data as test data.

Further, since a memory having n data development areas is provided in the test data supply unit and data development is performed, the same test can be performed on a plurality of IC devices by inputting a single set of test data by an operator. Data can be provided all at once.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an IC card test apparatus according to an embodiment of the present invention, FIG. 2 is a view showing an example of test data and expected data given to the apparatus of FIG. 1, and FIG. FIG. 4 is a block diagram showing a configuration of a data conversion unit of the apparatus of FIG. 1, FIG. 4 is a diagram showing a configuration of a data development area in a memory in a data development unit of the apparatus of FIG. 1, and FIG.
FIG. 6 is a diagram showing an output signal from the IC card detected in the device shown in FIG. 6, and FIG. 6 is a diagram for explaining the operation of the output data processing unit of the device shown in FIG. 10 Data supply unit, 20 Device mounting unit, 30 Output data processing unit, 35 AND gate.

────────────────────────────────────────────────── (5) References JP-A-60-169778 (JP, A) JP-A-59-23265 (JP, A) JP-A-61-133872 (JP, A) JP-A-60-169778 211375 (JP, A) JP-A-57-151874 (JP, A) JP-A-58-182566 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G01R 31/28

Claims (3)

(57) [Claims] A data supply unit for providing a plurality of n IC device test data; an n output detection unit for detecting that data according to the test data is output from each of the IC devices; A memory for storing data for each device output from each IC device independently for each device; n address units for accessing the data for each device with respect to the memory; and the memory And n comparison units for confirming whether or not the data for each device read from the device matches predetermined expected data, and wherein each of the address units detects an output from a corresponding output detection unit. A write counter that starts counting at a predetermined cycle from a time point, and a read counter that counts at the predetermined cycle from a time point when all of the n output detection units have detected outputs. A write function of writing output data from a corresponding IC device to the memory at the predetermined cycle by an address indicated by the write counter; and a memory function by an address indicated by the read counter at the predetermined cycle. An IC device test apparatus configured to perform a reading function of reading data from a device. 2. The IC device test apparatus according to claim 1, wherein: a data input unit for inputting test data; a check code generation unit for generating a check code to be added to the input test data; And a parallel / serial converter for converting the data into serial data consisting of binary codes, adding the check code generated by the check code generator to the serial data, and outputting the data. Test equipment. 3. The IC device test apparatus according to claim 1, wherein the data supply unit includes a memory having n data development areas, and inputs test data to one of the data development areas. An IC device test having a function of copying data to another data development area, wherein test data can be given to n IC devices from each of the n data development areas. apparatus.