JP2806376B2 - Image processing apparatus and image processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for performing texture mapping.

[0002]

2. Description of the Related Art When performing texture mapping in a conventional image processing apparatus, in an apparatus that does not have dedicated hardware for texture mapping, a CPU corresponds to an address of a graphic to be drawn from a texture storage area on a main memory. In this case, the address of the graphic to be drawn is directly specified and written in the frame buffer memory. FIG. 2 is a diagram showing a state of a display screen when line drawing is performed. The bus connecting the CPU and the image processing device has a bus width of 32 bits and a pixel depth of 8 b
Consider the case of it. When the CPU directly accesses the frame buffer memory, the area of 4 pixels horizontally and 1 line vertically indicated by the solid line in FIG. 2 can be simultaneously accessed. However, the line drawing indicated by the hatched lines in FIG.
Only one pixel can be drawn by one access from the PU to the image processing device.

On the other hand, when dedicated hardware for texture mapping is provided, a memory for storing texture is prepared, and the address of the texture corresponding to the address of the graphic to be drawn is calculated by the image processing LSI. The texture data is read from the memory for storing textures and is drawn in the frame buffer memory.

[0004]

In a conventional apparatus which does not have dedicated hardware for texture mapping, all the calculation of the lines for performing texture mapping is performed by C
Since the processing is performed by the PU, the load on the CPU is heavy, and the data is written to the frame buffer memory one pixel at a time. Therefore, there is a problem that the efficiency of data transfer on the bus from the CPU to the image processing apparatus is low.

Further, in a conventional apparatus having dedicated hardware for texture mapping, it is necessary to prepare a memory for storing textures, so that there is a problem that the apparatus becomes expensive.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image processing apparatus which can draw a graphic to be texture-mapped at high speed without requiring special hardware for texture mapping.

[0007]

According to the present invention, there is provided a mode selecting means for switching between drawing one figure with the same color value or drawing with a color value designated corresponding to one pixel, and a frame buffer memory. Address generating means for generating an address of a figure to be newly written, a color value storing means for storing a color value of the figure sent from the host processor, and a mode for drawing a color value designated for each pixel Is selected by the mode selection means,
Control means for synchronizing the setting of the color value and the generation of the address of the pixel to be drawn; drawing data storage means for storing the set plurality of color values and the addresses corresponding thereto; Means for writing the data to the frame buffer memory.

In the image processing apparatus according to the present invention, a graphic address is generated when a color value is set, and a plurality of drawing data are stored while associating the set color value with the address. Therefore, it is possible to rapidly draw a figure on which texture mapping which needs to draw a different color value for each pixel has been performed.

[0009]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, a HOST bus 1 is a bus that connects a CPU (not shown) and an image processing LSI 2, and
The bus width is 32 bits. The image processing LSI 2 is connected to a frame buffer memory (FRB) 4 via an FRB bus 3 having a width of 32 bits. The depth of one pixel of the FRB4 is 8 bits.

The image processing LSI 2 includes a HOST bus interface 201, a mode register 202, a graphic address generator 205, a color value register 206, a counter 203, a graphic address controller 204, a data selector 207, and a pixel FIFO 208. , A FIFO write pointer 209 and a FIFO read pointer 210
And an FRB interface 211.

The HOST bus interface 201
When a request is input from the HOST bus 1, H
The address signal on the OST bus 1 is decoded, and it is determined whether the address is an address designating the mode register 202, the graphic address generator 205 or the color value register 206.
This part sets the value of the data signal on the HOST bus 1 to the value specified by this address.

When a request to the color value register 206 is input, data is set in the color value register 206 and, at the same time, "4" is set in the counter 203. The mode register 202 is a register for setting whether or not to perform texture mapping. When "0", it indicates that texture mapping is not to be performed, and when "1", it indicates that texture mapping is to be performed. The counter 203 indicates the number of drawable data set in the color value register 206 in the mode for performing texture mapping.

The data width of the HOST bus 1 is 32 bits
When the depth of one pixel of the FRB 4 is 8 bits, the content of the counter 203 becomes “4” (32 bits / 8 bits = 8 bits) when data is set in the color value register 206.
4), and the graphic address generation unit 205 decrements the address of the graphic by one each time one pixel is calculated. When the mode register 202 is “1”, the graphic address control unit 204 detects that the value of the counter 203 is “0” and outputs a stop signal for stopping the graphic address generation unit 205.

The color value register 206 has the same number of registers as the data width of the HOST bus 1.
The color value set in each access is temporarily stored. The data selector 207 selects a color value corresponding to the address output from the graphic address generation unit 205 from the color values set in the color value register 206 with reference to the value of the counter 203.

The pixel FiFo 208 is a part for storing a plurality of addresses output from the graphic address generator and data output from the data selector 207 as pixel data. The Fifo write pointer 209 indicates the position where the next pixel data is written to the pixel Fi208, and the Fifo read pointer 210 indicates the position where the pixel data is read from the pixel Fi208.

The FRB interface 211 is a part for converting the graphic address received from the pixel Fi208 into an address of the FRB 4 corresponding to the graphic address and writing data to the FRB 4.

FIG. 2 is a diagram showing a state of a display screen when line drawing is performed. FIG. 3 is a timing chart showing an operation when performing line drawing in the present embodiment. With reference to these figures, an operation when performing line drawing using texture mapping according to the present embodiment will be described.

In FIG. 3, at the timing t1, the negative value of the request of the HOST bus 1 becomes LOW.
Since the address signal of the OST bus 1 is an address for specifying the mode register 202, the HOST bus interface 201 sets the mode register 202 to
The data input from the data signal of the OST bus is set.

Similarly, data is set in the graphic address generator 205 at timing t2, and in the color value register 206 at timings t3 and t9. At timing t1, "1" indicating the texture mapping mode is set in the mode register 202. At timing t2, the graphic address generator 205 sets the address of the line and sets the starting point P
Outputs a zero address. The counter 203 is set to “0” as an initial value.
Detects that the mode register 202 is "1" and the value of the counter 203 is "0", and outputs a stop signal for stopping the operation of the graphic address generation unit.

From timing t2 to t3, the stop signal is "1" and the graphic address generator is stopped. However, when color value data is set from the HOST bus 1 at timing t3, the HOST bus interface 201 becomes “4” is set in the counter 203 and the color value register 206 is set.
Set color value data. At this time, the stop signal is set to “0”.

When the stop signal becomes "0", the graphic address generator 205 generates an address to be drawn next,
The Fifo write pointer 209 also operates at the same time. At timing t4, the color value of P0 is selected by the data selector 207 from the value of the address of P0 from the graphic address generation unit 205 and the color values of four pixels output from the color value register 206, and the write pointer of the pixel FiFo208 indicates. It is stored at the position of “0”.

At the timing t4, the counter 203 is decremented, the output value of the graphic address and the data selector is updated to the data of P1, the value of the write pointer is incremented, and the pixel FiF at the timing t5.
The drawing data of P1 is stored at the position of "1" indicated by the write pointer of o208.

Similarly, at timings t6 and t7, the drawing data of P2 and P3 are stored in the pixel Fi208, and the operation by one color value data setting ends.
At timing t8, since the value of the counter 203 is "0", the stop signal becomes "1", and the graphic address generator 205 outputs the next address to be drawn until the next color value data is set. Has stopped.

When the second color value data is set at the timing t9, "4" is set in the counter 203 and the stop signal is set to "0" in the same manner as the setting of the first color value data. 205 and the Fifo write pointer 209 start operating.

At timing t10, the figure address generator 20
5 generates the address of P5, which is the end point of the line, and ends the operation. At timing t11, the Fifo write pointer 209 writes the drawing data of the end point to the pixel FiFo208 and ends the operation.

The drawing data at the starting point is a pixel FiFo20.
8, the FRB interface 211 reads out the drawing data sequentially from the position of the drawing data at the starting point indicated by the Fifo read pointer 210, and
Drawing is performed on FRB4 while calculating the address for FRB4 from the address stored in o208. The FRB interface 211 performs drawing on the FRB until the pixel FiFo208 becomes empty, and stops. When the drawing data of the end point is written into the FRB 4, the pixel FiFo208 becomes empty, and the drawing of one line is completed.

[0028]

As described above, according to the present invention, when a line to be subjected to texture mapping is drawn, a conventional C
Since the calculation of the address of the line performed by the PU is performed by the image processing device, and the drawing data from the CPU to the image processing device can be efficiently transferred, the effect that the line for performing the texture mapping can be drawn at high speed can be obtained. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a state of a display screen when line drawing is performed.

FIG. 3 is a timing chart showing an operation of the exemplary embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 HOST bus 2 Image processing LSI 3 FRB bus 4 Frame buffer memory 201 HOST bus interface 202 Mode register 203 Counter 204 Graphic address control unit 205 Graphic address generation unit 206 Color value register 207 Data selector 208 Pixel FiFo 209 Fifo Write pointer 210 Fifo read Pointer 211 FRB interface

Claims (2)

(57) [Claims] 1. A frame buffer memory means for storing image data to be displayed, wherein one figure to be displayed is drawn with the same color value or
Mode selection means for selecting whether to draw with a color value designated for each pixel, address generation means for generating an address of a figure to be newly written to the frame buffer memory, and figures sequentially sent from a higher-level device Color value storage means for storing a predetermined number of color values for each of the plurality of color values, reading out the predetermined number of color values stored in the color value storage means, and the address generating means for generating an address of a pixel indicated by the color value Synchronization with the
While storing the new predetermined number of color values in the color value storage means, counter means for suppressing address generation of the address generation means, and the color values sequentially read from the color value storage means, An image processing apparatus comprising: a writing unit that writes data to the frame buffer based on an address from the address generation unit. 2. A storage step of storing image data to be displayed in a frame buffer memory means, wherein one figure to be displayed is drawn with the same color value or
A mode selection step of selecting whether to draw with a color value designated for each pixel, an address generation step of generating an address of a figure to be newly written to the frame buffer memory, and a figure sequentially transmitted from a higher-level device. Storing a predetermined number of the color values in the color value storage means, reading out the predetermined number of color values stored in the color value storage means, and reading the address of the pixel indicated by the color value. A synchronization step of synchronizing with the generation by the address generation step; a suppression step of suppressing the address generation of the address generation means while the new predetermined number of color values are stored in the color value storage means; A writing method for writing the color values sequentially read from the color value storage means to the frame buffer based on the address generated by the address generation. An image processing method which comprises the steps.