JP2806084B2 - Automatic equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic equalizer for automatically equalizing a digitized signal, and more particularly, to a signal having nonlinear distortion in both a precursor component and a postcursor component in an impulse response signal. The present invention relates to an automatic equalizer for automatically equalizing.

[0002]

2. Description of the Related Art As a conventional automatic equalizer for equalizing a signal subjected to nonlinear distortion, there is a decision feedback type automatic equalizer using a RAM.

FIG. 8 is a diagram showing an example of a conventional RAM decision feedback type automatic equalizer. Here, an explanation will be given assuming that “001” which has been subjected to nonlinear distortion has already been input as an input signal and “0” is a signal currently input. Further, the determination result “001” determined so far is input to the shift register 30.

[0004] First, the lower 1
Other than the bits, “001” is supplied from the shift register 30, and “0” is supplied from the bit generator 31 to the lower one bit. As a result, the RAM 25 outputs an estimated value assuming that "0" is input as an input signal. Subtractor 2
In step 7, the output of the RAM 25 is subtracted from the input signal to obtain "0".
Output an error signal with respect to the time when it is assumed that is input. The output of the subtracter 27 is temporarily stored in the register 28.

Next, "1" is supplied from the bit generator 31 to the lower 1 bit of the RAM 25, and the RAM 25 outputs an estimated value assuming that "1" is input as an input signal. Similarly, the output of the RAM 25 is subtracted from the input signal by the subtracter 27, and an error signal is output when the input of "1" is assumed.

In the comparator 29, the output of the register 28 which is an error signal of "0" and the subtracter 2 which is an error signal of "1"
7 are compared with each other to determine which error signal is smaller. If the error signal corresponding to “0” is smaller than the error signal corresponding to “1”, “0”
Is determined to be correct, "0" is output as the determination value. Then, the content of the RAM 25 corresponding to the address “0010” of the RAM 25 is determined by using the error signal
, A correction signal is calculated and output to the RAM 25 for correction. Then, "0" is newly input to the shift register 30, and the whole is shifted to "010". Equalization is performed by repeating these operations.

However, as can be understood from the above description, in the RAM decision feedback type automatic equalizer having such a configuration, the intersymbol interference is assumed to be only the postcursor component in the impulse response. Cannot be equalized. Therefore, a method is used in which a transversal type automatic equalizer capable of equalizing a precursor component is combined with a RAM decision feedback type automatic equalizer. FIG. 9 shows a configuration diagram thereof.

In FIG. 9, an input signal is input to a delay unit 32. The input signal and each output signal of the delay unit 32 are output after being multiplied by a tap coefficient at each tap 33. The output of each tap 33 is added by an adder 34 and input to a RAM decision feedback equalizer 35. RAM
The decision feedback equalizer 35 equalizes the postcursor component of the input signal, and outputs a signal for correcting the tap coefficient to the tap 33 so as to equalize the precursor component of the input signal. Thus, the precursor component can be equalized by the transversal type automatic equalizer, and the postcursor component can be equalized by the RAM decision feedback type automatic equalizer 35.

[0009]

The transversal automatic equalizer operates effectively for linear distortion, but cannot perform sufficient equalization for nonlinear distortion. Therefore, in a state where the nonlinearity of the precursor component in the impulse response of the input signal cannot be approximated to linear distortion, it is not possible to obtain a sufficient equalization capability by the method shown in FIG.

[0010]

According to the present invention, there is provided an automatic equalizer provided with a digital input signal subjected to intersymbol interference distortion and a corresponding N (where N is 1).
The above-mentioned (integer) estimated signals are received, and an error detector for obtaining and outputting N errors respectively is compared with the absolute values of the N outputs from the error detector, and the digital input signal is obtained before distortion. A comparator for estimating and outputting a value; a correcting unit for receiving the digital input signal and an estimated signal having an absolute value of the N errors being the minimum and outputting a correction signal; and an impulse for the digital input signal. An estimated signal storage that outputs N estimated signals that are the number of states of the precursor component of the response;
An address generator for generating an address signal of the estimated signal storage when receiving the output of the comparator and reading the estimated signal from the estimated signal storage and writing the output of the corrector. It is characterized by the following.

[0011]

The non-linear distortion including the precursor component can be equalized by making the decision system in the RAM decision feedback type automatic equalizer a consideration in consideration of the precursor component in the impulse response. In the present invention, equalization is performed by performing a tentative decision on all of the states corresponding to the temporal lengths of the components of the precursor, and selecting a tentative decision signal having the smallest decision error from the tentative decision signals as the decided decision signal. ing.

[0012]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention.

Here, it is assumed that the length of the intersymbol interference, which is a problem, is 2 bits for the precursor component and 3 bits for the postcursor component in the impulse response. The input “0” will be described as the current input and “1010” will be the signal to be input in this order.

The address generator 3 stores 6 bits of "010011" of the result of the judgment made so far. The equalization of the postcursor component is performed by the lower three bits “011” of the above six bits.

First, at the time of reading the estimated signal, the address generator 3 shows the state of the current signal and the precursor component as 2 ^3.
“111” is generated from the signals “000”. The upper 3 bits “011” of the determination result are supplied to the upper 3 bits of the 6 bits of the address of the estimated signal storage 1, and the lower 3 bits represent the eight current signals and the precursor components described above, which indicate the precursor components. It operates so that bit signals are sequentially supplied. Thereby, for example, the lower three bits are set to “00”.
If it is "0", an estimated value is output from the estimated signal storage 1 as an input signal, assuming that the current is "0", "0" is input next, and "0" is input next.

The error detector 4 subtracts the eight outputs of the estimated signal storage 1 sequentially output from the input signal to output error signals corresponding to the lower 3 bits of the estimated signal storage 1 respectively. You. The absolute value of each of the eight error signals is further obtained, and is temporarily stored as an error signal corresponding to the lower address “000” of the estimated signal storage 1.

Next, when the lower three bits of the estimated signal storage unit 1 become "001", it is assumed that the current input signal is "0", then "0", and then "1". The estimated value is output, and the error detector 4 calculates the difference between the estimated signal and the input signal, and further obtains the absolute value to obtain an error signal for “001”. It is temporarily stored as an error signal corresponding to “001”.

The comparator 5 compares the eight kinds of error signals temporarily stored in the error detector 4, and compares which error signal is the smallest. Assuming that the absolute value of the error signal stored in the register corresponding to the signal of the lower address “010” of the estimated signal storage 1 is the smallest, the determination value of the input signal at this time is determined to be “0”. And
The past determination result signal stored in the address generator 3 is inputted with “0” and shifted by one bit to “10”.
0110 ".

The same operation is performed when the next data is input. The lower three bits “110” of the determination result “100110” of the address generator 3 are input to the upper address of the estimated signal storage 1, and the state of the current signal and the precursor component are stored in the lower address of the estimated signal storage 1. "111" from the 2 ^three signal "000" indicated is sequentially supplied from the address generator 3, the comparator 5 and the error detector 4, a determination of the input signal. Lower 3 bits of the estimated signal storage 1 "10"
Assuming that the absolute value of the error signal stored in the register corresponding to the signal of "1" is the smallest, the determination value of the input signal at this time is determined to be "1". The past judgment result signal is inputted with "1" and shifted by 1 bit to obtain "001101".
Becomes

The same operation is performed when the next data is input, and "0" is obtained as the judgment value, and the value of the address generator 3 becomes "011010".

Estimated signal storage 1 for the first input signal
Can be corrected only after a determination result of two bits is obtained later. Therefore, the correction is performed using the delayed input signal corresponding to the length of the precursor component of the intersymbol interference and the output signal of the estimated signal storage 1. The correction value write address of the estimated signal storage 1 is the determination value of the past 6 bits stored in the address generator 3, that is, “011010”, and the estimation signal storage 1 estimates the input signal corresponding to the address. A signal is output. The input signal delayed by the length of the precursor length and the output of the correction estimation storage unit 1 are processed by the correction unit 2, and the updated estimation signal is written to the estimation signal storage unit 1. That is, the update of the content of the estimated signal storage 1 is delayed by three timings as compared with the determination of the input signal in the comparator 5. For example, the following equation is used as a method of updating in the corrector 2. D ₀₁₁₀₁₀ ← (1−α) XD ₀₁₁₀₁₀ + α × X D ₀₁₁₀₁₀ is the address “01101” of the estimated signal storage 1
Where 0 is the correction factor (α <1) and X is the input signal.

By repeating the above operation, non-linear distortion including not only the post-cursor component but also the precursor component can be equalized.

FIG. 2 is a diagram showing a specific example of the address generator 3 when the estimated signal storage 1 is constituted by one. The output signal of the comparator 5 is input to the lower shift register 7 for serial-parallel conversion, and the output of the last stage of the lower shift register 7 is input to the upper shift register 8 for serial-parallel conversion. When the estimated value is read from the estimated signal storage 1 in order to obtain an error signal by the error detector 4, the selector 9
The output of the read address generator 6 is selected as the lower address of the estimated signal storage 1, and the parallel output of the lower shift register 7 is selected as the upper address. When writing the output signal of the corrector 2 into the estimated signal storage 1, the selector 9 outputs the parallel output of the lower shift register 7 as the lower address of the estimated signal storage 1 and the parallel output of the upper shift register 8 as the upper address. Is selected.

FIG. 3 is a diagram showing a specific example of the error detector 4 when the estimated signal storage 1 is constituted by one. After the difference between the estimated signal from the estimated signal storage 1 and the input signal is determined by the subtractor 10 as an error signal, the absolute value calculator 11 determines the absolute value of the error signal. The output signal of the absolute value calculator 11 is written to the register 12 corresponding to the read address generator 6, and is temporarily stored.

FIG. 4 is a diagram showing a specific example of the corrector 2 when the estimated signal storage 1 is constituted by one. The delay unit 13 delays the input signal until the precursor component of the estimated signal output from the estimated signal storage unit 1 is determined. The arithmetic unit 14 corrects the estimated signal from the output signal of the delay unit 13 and the output signal of the estimated signal storage 1 and outputs the corrected signal to the estimated signal storage 1.

FIG. 5 is a diagram showing a specific example of the estimated signal storage 1 and the address generator 3 when the estimated signal storage 1 is composed of eight storage units 15. The lower shift register 16 of FIG. 5 stores “011” for three symbols as a result of the determination made so far. These three symbols correspond to the equalization of the postcursor component.

Lower 3 addresses of each estimated signal storage unit 15
The bits are given “000” to “111”, respectively, and correspond to the equalization of the respective states of the precursor components.

The upper shift register 17 stores three symbols of the final stage output data overflowed by the shift operation of the lower shift register 16. here,
It is assumed that “010” is stored.

First, the selector 18 selects the upper three bits out of the six bits of the eight addresses of the estimated signal storage unit 15 so as to be supplied from the lower shift register 16. As a result, eight types of estimated values corresponding to the number of states of the precursor are output from the estimated signal storage unit 15 as input signals.

FIG. 6 is a diagram showing a specific example of the error detector 4 when the estimated signal storage 1 is composed of eight storage units. The subtractor 19 in FIG. 6 subtracts the output of each estimated signal storage 20 from the input signal and outputs an error signal. Subtractor 1
The absolute value of the output of the subtractor 19 is obtained by the absolute value calculator 20 from the output of the register 9.

The comparator 5 compares the absolute values of the error signals corresponding to the eight lower bits of the address of the estimated signal storage unit 15 from "000" to "111", and determines which error signal is the smallest. Compare. Assuming that the absolute value of the error signal corresponding to the signal “010” is the smallest, the determination value of the input signal at this time is determined to be “0”.
Then, the value of the lower shift register 16 becomes “110” by inputting and shifting “0”, and the value of the upper shift register 17 becomes “100”.

The same operation is performed when the next data is input. "110" is input from the lower shift register 16 to the upper address 17 of the estimated signal storage unit 15, "000" to "111" is input to the lower address 16 of each estimated signal storage unit 15, and the absolute value Arithmetic unit 2
The output of 0 is compared by the comparator 5. At this time, since “1” is obtained as the determination value, the value of the lower shift register 16 becomes “101” and the value of the upper shift register 17 becomes “001”.

The same operation is performed when the next data is input. At this time, "0" is obtained as a judgment value.
The value of the lower shift register 16 is “010”, and the value of the upper shift register 17 is “011”. That is, the decision value for the first input signal and the precursor component due to intersymbol interference are obtained in the lower shift register 16, and the postcursor component due to intersymbol interference is obtained in the upper shift register 17.

FIG. 7 is a diagram showing a specific example of the correction unit 2 when the estimated signal storage unit 1 is composed of eight storage units. The delay unit 21 shown in FIG. 7 functions to delay the input signal by three symbols required to determine the precursor component.

Estimated signal storage unit 1 for the first input signal
The correction of the content of 5 is performed using the output of the delay unit 21 and the estimated signal of the estimated signal storage unit 15. As the address of the estimated signal storage unit 15, the upper shift register 1 already determined
7 is selected by the selector 18, and the read selector 23 and the write selector 24 select the estimated signal storage unit 15 whose lower three bits of the address are “010”. Therefore, the address “011010” of the estimated signal storage unit 15
Is output as the estimated signal of the first input signal corresponding to. On the other hand, the first input signal is output from the delay unit 21, the output of the delay unit 21 and the estimated signal output from the estimated signal storage unit 15 are processed by the arithmetic unit 22, and the updated estimated signal is stored in the estimated signal storage unit 15. Written to That is, the update of the content of the estimated signal storage unit 15 is delayed by three timings as compared with the determination of the input signal in the comparator 5. As a method of updating in the arithmetic unit 22, for example, the following equation is used. D ₀₁₁₀₁₀ ← (1−α) × D ₀₁₁₀₁₀ + α × X D ₀₁₁₀₁₀ is the address “0110” of the estimated signal storage unit 15.
10 is a value for 10 ″, α is a correction coefficient (α <1), and X is an output signal of the delay unit 21.

By repeating the above operation, non-linear distortion including not only the post-cursor component but also the precursor component can be equalized.

[0037]

As described above, by adding the function of assuming the decision value for the precursor component of the input signal to the RAM decision feedback equalizer to the non-linear signal including the precursor component, as described above. Can be equalized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram showing a specific example of an address generator when an estimation signal storage device according to the present invention is configured by one storage unit.

FIG. 3 is a configuration diagram showing a specific example of an error detector when an estimation signal storage device according to the present invention is configured by one storage unit.

FIG. 4 is a configuration diagram showing a specific example of a corrector when the estimation signal storage device according to the present invention is configured by one storage unit.

FIG. 5 is a configuration diagram illustrating a specific example of an address generator when the estimation signal storage device according to the present invention is configured by eight storage units.

FIG. 6 is a configuration diagram illustrating a specific example of an error detector when the estimated signal storage device according to the present invention is configured by eight storage units.

FIG. 7 is a configuration diagram illustrating a specific example of a corrector when the estimated signal storage device according to the present invention includes eight storage units.

FIG. 8 is a configuration diagram showing an example of a conventional post-cursor equalization RAM decision feedback type automatic equalizer.

FIG. 9 is a configuration diagram showing an example of a conventional RAM decision feedback type automatic equalizer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Estimation signal memory 2 Corrector 3 Address generator 4 Error detector 5 Comparator 6 Read address generator 7 Lower shift register 8 Upper shift register 9 Selector 10 Subtractor 11 Absolute value calculator 12 Register 13 Delayer 14 Operation Unit 15 estimated signal storage unit 16 lower shift register 17 upper shift register 18 selector 19 subtractor 20 absolute value calculator 21 delay unit 22 calculator 23 read selector 24 write selector 25 RAM 26 modifier 27 subtracter 28 register 29 Comparator 30 shift register 31 bit generator 32 delay unit 33 tap 34 adder 35 RAM decision feedback equalizer

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-14125 (JP, A) Proceedings of the 1991 IEICE Autumn Conference, Volume 5 (1991-9), pp. 5-17 IEICE Technical Report, Vol. 91, No. 385 [MR91-54 to 64] (Magnetic storage) (1991-12-17) 23-28 (58) Fields surveyed (Int. Cl. ⁶ , DB name) H04B 3/00-3/18 H04B 7/005-7/015 H03H 15/00-21/00 JICST file (JOIS)

Claims (3)

(57) [Claims] 1. An error detector that receives a digital input signal subjected to intersymbol interference distortion and N (N is an integer of 1 or more) estimated signals corresponding thereto and obtains and outputs N errors, respectively. A comparator for comparing the magnitudes of the N outputs from the error detector and estimating and outputting a value before distortion of the digital input signal; and wherein the absolute value of the digital input signal and the N errors is minimum. A corrector that receives a certain estimation signal and outputs a correction signal, and outputs N estimation signals that are the number of states of a precursor component of an impulse response to the digital input signal, and outputs an output signal of the correction device. An estimation signal storage unit to be inputted and stored; and receiving an output of the comparator, generating an address signal of the estimation signal storage unit when reading the estimation signal from the estimation signal storage unit and writing the output of the correction unit. Do Automatic equalizer, characterized in that is composed of a dress generator. 2. The read address generator, wherein the address generator generates an address signal corresponding to each state of a precursor component in the impulse response when reading an estimated value from the estimated signal storage, and an output of the comparator. To serial-to-parallel conversion
An address signal for generating an address signal corresponding to a state of a postcursor component when generating an address signal for reading an estimated value from the estimated signal storage, and writing an output signal of the corrector to the estimated signal storage. And a lower shift register for generating an address signal corresponding to the state of the precursor component when generating the output of the corrector. When generating an address signal for writing a signal, an upper shift register that generates an address signal corresponding to the state of a postcursor component, and when reading an estimated value from the estimated signal storage, as an address signal of the estimated signal storage. The output of the read address generator and the output of the lower shift register,
When writing the output signal of the corrector to the estimated signal storage, the selector includes an selector for selecting an output of the lower shift register and an output of the upper shift register as an address signal of the estimated signal storage. A delay unit for delaying the digital input signal, an operation of receiving the estimated signal of the estimated signal storage unit selected by the delay unit and the address generator and outputting a new estimated signal to the estimated signal storage unit 2. The automatic equalizer according to claim 1, wherein said automatic equalizer comprises a corrector. 3. The estimation signal storage device includes N storage units, and the address generator receives an output of the comparator and performs serial-parallel conversion.
A lower shift register for generating an address signal when a read operation is performed on each of the N storage units; and a serial-to-parallel conversion upon receiving the final stage output of the lower shift register to the estimated signal storage. An upper shift register that generates an address signal when performing a write operation; and a selector that selects the lower shift register as an address signal during a read operation of the estimation signal device and the upper shift register as an address signal during a write operation. A read selector for selecting N output signals from the estimated signal storage by a signal from the lower shift register; a delay device for delaying the digital input signal; and the delay device And the estimation signal of the estimation signal storage selected by the readout selector. A calculator for outputting a new estimated signal, 1 an output signal of the arithmetic unit of the storage unit consisting of the N determined by the output signal of the low-order shift register
2. The automatic equalizer according to claim 1, further comprising a write selector that outputs the data to one of the plurality of write registers.