JP2803459B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
More particularly, the present invention relates to a semiconductor memory device having a high-speed and redundancy circuit.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional semiconductor memory device has inverter circuits 11 and 12 which receive address signals Y0 and Y1, Y0 and Y1 and output inverted output signals NY0 and NY1, respectively. Or N
A decoder circuit 13 for inputting Y0 and Y1 or NY1 and outputting a selection signal; fuses F0, F1, F2 and F3 for connecting outputs of the decoder circuit to main storage blocks 22, 23, 24 and 25; Resistors R0, R1, R2 and R3 connecting the input of the block and the highest potential, and the lowest potential Y0 or NY according to the program
A switching circuit 26 having a switch for selecting 0 and a switch for selecting the lowest potential, Y1 or NY1;
It has a redundant decoder circuit 27 that receives the output of the switching circuit 26 and outputs a selection signal, and a redundant storage block 28 that receives the output.

Considering that there are no bad blocks,
The fuses (F0 to F3) are all connected. Both inputs of the redundant decoder circuit 27 are at a low level (hereinafter referred to as L). At this time, the high level (hereinafter, referred to as H) of the output of the redundant decoder 27 is input to the redundant storage block 28, and the redundant storage block 28 is in a non-selected state. On the other hand, an address signal Y0 or NY0 and Y1 or NY1 are connected to an input of the decoder circuit 13 composed of a two-input NAND circuit.
A main storage block (22 to 25) is selected according to the address signal.

Next, consider a state in which there is a bad block. When there is only one defective block, the semiconductor storage device can be made non-defective by replacing the defective block with a redundant storage block 28 prepared in advance. If it is found from the test that only BLOCK022 has a defect, the fuse F corresponding to BLOCK022 is
Cut 0. Further, the input of the redundant decoder 27 is connected to the address signals NY1 and NY0 to which the decoder of the BLOCK 022 is connected by using the switching circuit 26. As a result, BLOCK 022 is replaced by the redundant storage block 28, and when the signal (Y0, Y1) = (L, L) is input to the decoder circuit 13 and the redundant decoder circuit 27 thereafter, the main storage blocks (22 to 25) are replaced. The redundant storage blocks 28 are all in the non-selected state. on the other hand,
When an address other than (Y0, Y1) = (L, L) is input, a main storage block (22 to 25) which is a non-defective block
Is selected.

[0005]

However, in this conventional semiconductor memory device, since a fuse exists in a signal path, it is necessary to use a low-resistance first polysilicon layer for the fuse. Since the first polysilicon layer is below the second polysilicon layer, the first aluminum wiring layer, and the second aluminum wiring layer, it has been difficult to control the position and energy of the laser for cutting the fuse. The first polysilicon layer has a lower resistance than the second polysilicon layer, but has a resistance several hundred times that of the first and second aluminum wirings. It was slow.

[0006]

A semiconductor memory device according to the present invention comprises a plurality of memory cells arranged in an array in both row and column directions, and a plurality of bit lines connecting these memory cells in common for each column. A plurality of main storage blocks each including a word line commonly connected to each row; an address buffer receiving an address signal; a decoder circuit for decoding an output of the address buffer and selecting the plurality of main storage blocks; A plurality of fuse circuits connected between the decoder circuit and the plurality of main storage blocks; a redundant storage block having the same configuration as the main storage block; a redundant decoder circuit for selecting the redundant storage block; The address input to a decoder circuit for selecting the main storage block that does not operate electrically among the main storage blocks A fuse circuit having a transfer gate, wherein the fuse circuit has a transfer gate, and the decoder circuit is connected to the main storage block via the transfer gate. .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing a configuration of a semiconductor memory device according to a first embodiment of the present invention, a semiconductor memory device according to the present invention receives an address signal (Y0, Y1) and each address signal. Inverter circuits 11 and 12 for outputting inverted output signals (NY0, NY1);
A decoder circuit 13 for inputting Y0 and Y1 or NY1 and outputting a selection signal; a fuse circuit (18-21) for connecting the output of the decoder circuit 13 to the main memory block (22-25); Potential or Y0 or NY0, and lowest potential or Y1 or N
It has a switching circuit 26 for outputting Y1, an output signal of the switching circuit 26, a redundant decoder circuit 27 for outputting a selection signal, and a redundant storage block 28 for inputting the output. The above-mentioned fuse circuits (18 to 21) are connected to the NMOS transistor 30 connecting the input and the output of the fuse circuit (P).
A transfer gate composed of a MOS transistor 29, a fuse F0 for giving a LOW potential to the gate of the PMOS transistor 29 of the transfer gate, a resistor R20 for giving a HIGH potential to the gate of the PMOS transistor 29 when the fuse is cut off, It comprises an inverter circuit 31 for applying a reverse logic potential to the gate of the PMOS transistor 29.

Now, consider a state in which there is no bad block. B
Fuse circuit F connected to the selection signal of LOCK022
The fuse F0 in C0 is in a connected state. Therefore, the LOW level is input to the gate of the PMOS transistor 29 constituting the transfer gate, and the HIGH level is input to the gate of the NMOS transistor 30. As a result, the transfer gate is turned ON, and B
The output of the decoder circuit 14 is connected to the selection signal terminal of LOCK022. Similarly, the outputs of the decoder circuits 15, 16 and 17 are connected to the BLOCKs 1, 2 and 3, respectively, and the main storage block 2 is connected in accordance with the address.
3, 24 and 25 are selected respectively. A low level is connected to the input of the redundant decoder 27 by the program of the switching circuit 26, and the H level is
The high level is input, and the state becomes a non-selection state.

Next, consider a state in which there is a bad block. When there is only one bad block, the device can be made non-defective by replacing the bad block with a redundant storage block 28 prepared in advance. If it is found from the test that only BLOCK022 has a defect, the fuse F0 in the fuse circuit FC0 corresponding to BLOCK022 is cut. As a result, the HIGH level generated by the resistor R20 is input to the gate of the PMOS transistor 29 constituting the transfer gate, and the NMO
The LOW level is input to the gate of the S transistor 30. As a result, the transfer gate is turned off, and the HIGH level generated by the resistor R10 is input to the selection signal terminal of the BLOCK 022.
K022 enters a non-selected state. BLOCKs 1, 2, and 3 are selected according to the address because the fuses are connected. Further, the input of the redundant decoder 27 is connected to the address signal to which the decoder 14 of the BLOCK 022 was connected by using the switching circuit 26. This allows BL
The OCK 022 is replaced by the redundant storage block 28. Thereafter, when a signal (Y0, Y1) = (L, L) is input to the decoder, all the BLOCK 022 are in the non-selected state and the redundant block 28 is in the selected state. (Y0, Y1) = (L,
When an address other than L) is input, the main storage blocks 23, 24, and 25, which are non-defective blocks, are selected. When there is a defect in BLOCKs 1, 2, and 3, the redundant storage block 28 can be used in the same manner.

The fuse circuit 18 of the present invention connects the input and output of the block selection signal with a transfer gate. The state of the gate is determined when the power is turned on. There is no gate delay during the actual operation, and the impedance of the transfer gate can be extremely lower than the polysilicon used for the fuse F0. Can communicate. Main memory block (22-2
Since a steady current does not flow through the selection signal input terminal of 5), the resistance R10 for setting the main memory block (22 to 25) to the non-selection state when the transfer gate is in the OFF state can be increased. Do not hinder. Further, since a steady current does not flow through the input of the transfer gate and the input terminal of the inverter, the resistance R20 for turning off the gate when the fuse F0 is in the OFF state can be increased. Similarly, the fuse F0 may have a large resistance, and a second polysilicon layer which can be easily blown by a laser can be used.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG.

In the semiconductor memory device of this embodiment, the PMOS transistor 29 and the NMOS transistor 30, the inverter 31, the fuse F0, and the resistors R10 and R20 which constitute the transfer gate of the fuse circuit 18 of the first embodiment are deleted. Outputs of circuits (14 to 17) and main storage blocks (22 to 25)
NMO that constitutes a transfer gate connected to the input of
S transistor 32 and NM of this transfer gate
A fuse F30 for applying a HIGH potential to the gate of the OS transistor 32; and N when the fuse F30 is cut.
Except for a resistor R40 for applying a LOW potential to the gate of the MOS transistor 32 and a resistor R30 for setting the block selection signal to a non-selected state of HIGH when the transfer gate is OFF, the same configuration and the same as the first embodiment. The components have the same reference numerals.

Next, consider a state in which there is no bad block.
The fuse F30 in the fuse circuit 38 connected to the selection signal of BLOCK022 is in a connected state. Therefore, the HIGH level is input to the gate of the NMOS transistor 32 that forms the transfer gate. As a result, the transfer gate is turned ON, and BLOCK
The output of the decoder circuit 14 is connected to the selection signal terminal 022. Similarly, the outputs of the decoder circuits 15, 16 and 17 are connected to BLOCKs 1, 2 and 3, respectively.
A main storage block (22 to 25) is selected according to the address. The switching circuit 26 is connected to the input of the redundant decoder 27.
The LOW level is connected by the program described above, the High level is input to the redundant block 27, and the redundant block 27 is in the non-selected state as in the case of the first embodiment.

Next, consider a state in which there is a bad block. When there is only one bad block, the device can be made non-defective by replacing the bad block with a redundant storage block 28 prepared in advance. If it is found from the test that only BLOCK022 has a defect, the fuse F30 in the fuse circuit 38 corresponding to BLOCK022 is cut. As a result, the LOW level generated by the resistor R40 is input to the gate of the NMOS transistor 32 forming the transfer gate. As a result, the transfer gate is turned off and BLOCK
HIGH made to the selection signal terminal of 022 by the resistor R30
The level is input, and as a result, BLOCK 022 is in a non-selected state. BLOCKs 1, 2, and 3 are selected according to the address because the fuses are connected. Further, the input of the redundant decoder 27 is connected to the address signal to which the decoder 14 of the BLOCK 022 was connected by using the switching circuit 26. As a result, BLOCK 022 is replaced by the redundant block 28. Thereafter, when a signal (Y0, Y1) = (L, L) is input to the decoder 13, all of the main storage blocks (22 to 25) are in a non-selected state and redundant storage. Block 28 is selected. (Y0, Y1) =
When an address other than (L, L) is input, the main storage blocks (22 to 25), which are non-defective blocks, are selected in the same manner as in the first embodiment.

When there is a defect in BLOCKs 1, 2, and 3, the redundant storage block 28 can be used in the same manner.

The fuse circuit 38 of this embodiment has no gate delay because the input and output of the block selection signal are connected by a transfer gate. Further, the transfer gate impedance can be made extremely lower than that of polysilicon, so that the block selection signal can be transmitted at high speed. Since a steady current does not flow through the selection signal input terminal of the block, the resistance R30 for setting the block to the non-selection state when the transfer gate is in the OFF state can be increased, and does not hinder normal signal transmission. In addition, since a steady current does not flow through the input of the transfer gate and the input terminal of the inverter, the fuse is turned off.
A resistor R40 for turning off the gate in the FF state
Can be large. Similarly, the fuse F30 may have a large resistance, and may be made of first polysilicon which is easily melted by a laser. Since the transfer gate in the circuit of FIG. 3 is formed of an NMOS, the source / drain potential rises near the maximum potential even when the HIGH potential is applied to the gate, and the potential difference from the gate becomes equal to or lower than the threshold voltage VT. Turn off. To prevent this, the output amplitude of the decoder circuit and the input level of the normal block are set to the lowest potential side. For example, the power supply is set to 5V and the input is set to 0 / 3V. This prevents the transfer gate from being turned off when the gate is at the HIGH level, and reduces the amplitude, thereby achieving higher speed and lower power consumption.

[0018]

As described above, the present invention has the effect of realizing a high-speed semiconductor memory device because the resistance of the transmission path of the block selection signal is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional semiconductor memory device.

FIG. 3 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention.

[Explanation of symbols]

11, 12 Address buffer 13, 14, 15, 16, 17 Decoder circuit 18, 19, 20, 21, 38, 39, 40, 41, F
C0, FC1, FC2, FC3, FC30, FC31,
FC32, FC33 Fuse circuit 22, 23, 24, 25, BLOCK0, BLOCK
1, BLOCK2, BLOCK3 Main memory block 26 Switching circuit 27 Redundant decoder circuit 28 Redundant memory block 29 PMOS transistor 30, 32 NMOS transistor 31 Inverter circuit F0, F1, F2, F3, F30 Fuses R0, R1, R2, R3, R10, R20, R30, R
40 Resistance Y0, Y1 Address signal NY0, NY1 Address inversion output signal

Claims (1)

(57) [Claims] A plurality of memory cells arranged in an array in both the row and column directions, a plurality of bit lines commonly connecting the memory cells for each column, and a word line commonly connected for each row. A plurality of main storage blocks, including an address buffer supplied with an address signal,
A decoder circuit for decoding the output of the address buffer and selecting the plurality of main storage blocks; a plurality of fuse circuits connected between the decoder circuit and the plurality of main storage blocks; A redundant storage block, a redundant decoder circuit for selecting the redundant storage block, and an output of the address buffer input to a decoder circuit for selecting the main storage block that is not electrically operated among the plurality of main storage blocks. A semiconductor memory device having a switching circuit connected to a decoder circuit, wherein the fuse circuit has a transfer gate, and the decoder circuit and the main memory block are connected via the transfer gate. Storage device.