JP2801260B2 - Code transmission method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a code transmission method, and more particularly, to a code transmission method for performing transmission by adding an error detection and correction code to a main information code.

2. Description of the Related Art Generally, in a system in which an information signal such as an image signal is digitized and transmitted to a transmission path such as a recording medium, information data is converted into a transmission code suitable for the transmission path before transmission.

Hereinafter, in this specification, a magnetic recording device such as a digital VTR will be described as a typical example of such a transmission device.

Normally, in this type of magnetic recording device, it is difficult to record and reproduce very low frequency and DC components due to the transmission characteristics of the magnetic recording system. Therefore, after converting the digital data to be recorded into a recording code with few low frequency components,
An operation of recording is generally performed.

As a conversion coding method for suppressing this low frequency component, a conversion coding method having a redundancy such as a method of converting 8-bit data into 9-bit data (8-9 conversion) is conventionally used. Have been. However, this method has a disadvantage that the redundancy is increased. With the increase in the data amount and the high-density recording, a coding method that does not increase the redundancy even from the background where recording and reproduction with a smaller number of codes is desired. Is desired.

Therefore, as a method that does not increase the redundancy, for example, nn which converts n-bit data into the same n-bit data is used.
A mapping coding scheme was considered. The nn mapping coding suppresses low-frequency components of a code sequence to be recorded by using a statistical property of an input code string, for example, a property that a correlation between adjacent codes is high in image information. Things.

As an example of this method, the input signal is differentially encoded, and by utilizing the fact that the differential code has a Laplace distribution concentrated near zero of the positive / negative quantization level, CDS is applied to a differential code having a high appearance frequency. A code with a small (Code word Digital Sum) is assigned, thereby reducing the DSV (Digital Sum Value) of the converted and coded code sequence. The low-frequency component of the code sequence to be recorded in this way is suppressed, and for example, a 4-4 mapping coding system that converts a 4-bit differential code into a 4-bit code can be used.

[Problems to be Solved by the Invention] By the way, in the mapping coding, as described above, for information codes such as image information having correlation between adjacent codes, it is possible to suppress a low frequency component of a coded code sequence. However, low-frequency components of codes having no correlation between codes cannot be suppressed.

For example, when an error detection / correction code for detecting or correcting a code error or a code sequence for recording additional information having no correlation is additionally inserted, the effect of suppressing low-frequency components of the code sequence is sufficient. I can't get it. As a result, the bit error rate at the time of decoding increases.

Hereinafter, this point will be further described with reference to FIG. FIG. 4 is a schematic diagram showing a configuration example of a general data frame as a format of a code sequence to be recorded;
In the figure, the information data sequence subjected to the mapping coding described above is arranged in the part shown as information data, and the inspection point such as a Hamming code or Reed-Solomon code is arranged in the part shown as a check point. . In addition, Sync.I
An additional information code such as a synchronization code or an ID code is arranged in a portion indicated as D or the like.

However, when a data frame as shown in FIG. 4 is formed, since there is no correlation between codes in a portion where the check points of the error detection and correction code are continuous, mapping coding cannot be performed, and the same code is not continuously used. It can be said that the situation is likely to occur. Therefore, a low-frequency component is easily generated in this portion, and the low-frequency component is not sufficiently suppressed as a whole of the code sequence to be recorded.

As one method for solving such a problem, the present applicant has proposed a technique of distributing additional information codes such as error detection and correction codes in a code sequence to be recorded (Japanese Patent Laid-Open No. Sho 62-30).
No. 436). In this method, the codes causing low frequency components are dispersed in the code sequence, so that the code error rate at the time of decoding can be significantly reduced. By the way, in this method, the low frequency component itself of the error detection and correction code itself is not changed.

The present invention provides a novel encoding method capable of suppressing the entire low-frequency component of an encoded sequence by suppressing the low-frequency component of the error detection and correction code itself in such a background. Aim.

[Means for Solving the Problems] Under such a purpose, according to the present invention, the code group used for the operation at the time of generating the error detection / correction check code includes a fraction bit associated with a fraction of the bit number of the main information code. A code transmission method in which the bit pattern of the calculated error detection / correction check code is detected and the value of the fractional bit is changed according to the detection result is presented.

As a preferred embodiment of the present invention, the main information code is composed of a plurality of symbols including a plurality of compression codes each of which compresses a sample value of the information signal, and the number of compression codes in the last symbol of each code group is set. Is less than the number of compression codes in other symbols.

[Operation] With the configuration described above, even when a continuous portion of the error detection and correction code exists in the code sequence to be transmitted, the low frequency component of the code sequence can be sufficiently suppressed, and Code transmission can be performed.

Also, as shown in the preferred embodiment of the present invention, the above-mentioned effects can be realized without increasing redundancy at all by using fractional bits in the main information code included in each code group as dummy codes.

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a diagram showing a main configuration of a recording apparatus to which the code transmission method of the present invention is applied, and shows a generation unit of a code sequence to be recorded.

In this embodiment, it is assumed that a Reed-Solomon code in which an irreducible polynomial on a Galois field (2 ⁸ ) is used as a generator polynomial as an error detection and correction code, and an 8-bit code is treated as one symbol. .

The format of the code sequence to be recorded is
Assume the data frame configuration shown in the figure. That is, as is apparent from FIG. 3, one data frame structure includes N symbols for the main information code to be transmitted,
The configuration is such that a sub information code of a symbol and parity bits for K symbols are added as an error detection and correction code.
The sub-information code includes a synchronization code (Sync) and an ID code.

Each symbol is 8 bits, and the last symbol in the main information code of the M symbols has 1 fractional bit. However, 1 is less than 8.

Here, the process of generating the fraction bits will be described below.

Normally, image information is sampled in 8 bits,
In order to reduce the amount of information, processing such as performing high-efficiency encoding such as DPCM and compressing a code for two pixels into, for example, four bits is generally performed. In such a device that compresses 8 bits into 4 bits and records (transmits),
When the information in one data frame to which the error detection / correction code is added corresponds to an odd number of samples, the number of main information codes in each data frame does not become an integral multiple of 8 bits, but is 4 times.
A fractional bit of bits occurs.

In such a case, as described above, when an error detection / correction code having 8 bits as one symbol is used, a dummy code is inserted into the generated fractional bits. In the present embodiment, the bits to be inserted into the fractional bits are used. The pattern is actively used so that the low-frequency component of the generated parity is suppressed.

Here, the following description will be made on the assumption that the fractional bits in FIG.

In FIG. 1, an information code sequence Di to be recorded and transmitted is input to a compression coding circuit 101, and a process of compressing an 8-bit code into 4 bits is performed by high-efficiency coding such as DPCM described above. .

The compressed information code sequence is input to a mapping encoding circuit 102, in which the above-described mapping code using the statistical properties of the compressed main information code sequence is performed, thereby increasing the redundancy at all. The information is converted into a main information code sequence in which low frequency components are suppressed and output.

The converted main information code is input to the memory 103,
The data is sequentially read according to the format shown in FIG.

Note that the parity bit as the error detection and correction code is generated by a parity calculation circuit or the like to be described later, and is inserted at a predetermined position in a data frame in a subsequent stage. or,
Here, for the fractional bits in the main information code described above, for example, a code of all 0s is inserted as an initial setting value before the parity calculation.

Now, in a state where the predetermined initial value is substituted for the fractional bit, the sub information code and the main information code are parity operation circuits 111, 121, 131 for error detection and correction, a latch 106 for latching a symbol including the fractional bit, and The data is supplied to the memory 104.

Here, an operation for parity generation will be described. Now, a code for generating a parity bit, that is, a main information code M symbol is represented by information = (i ₁ , i ₂ , i ₃ ...
i _M ), and the error detection / correction codeword is represented as = (i ₁ , i ₂ , i ₃ ... i _M , x ₁ , x ₂ ,... x _K ). Here, x ₁ ~x _K corresponds to the parity bit. Both of them can be expressed as = G using the generator matrix G. Here, G is a matrix as follows.

That is, parity bits are generated by an operation called matrix multiplication.

FIG. 2 shows a parity calculation circuit shown in FIG.
FIG. 3 is a diagram illustrating a configuration example of 111, 121, and 131. Generator matrix ROM20
1 stores the coefficients P _{1,1 to} P _{K, M} of the above-described generator matrix at addresses corresponding to the respective elements of the information, and the Galois pair multiplier 202 stores the respective elements of the information and the corresponding R
The output of the OM 202, that is, Galois field multiplication of each coefficient of the generator matrix is performed. Further, the multiplication is performed by a circuit including the Galois field adder 203 and a one-symbol delay circuit, and the above-described matrix operation is performed. Here, the addition of the Galois field is performed by EXOR (exclusive OR) for each bit.

Parity calculation circuit realized by the above configuration
Each parity generated by 111, 121, 131 is
2, 122, 132. On the other hand, the main information code is held in the memory 104 until the parity generation is completed.
In addition, in order to generate a symbol including the changed single bit when the above-described single bit is changed, the latch 106 holds only the symbol including the fractional bit.

Next, each parity calculated as described above is input to the bit pattern detection circuit 141, and the bit pattern is detected. Then, based on the detected bit pattern, the determination circuit 142 determines whether or not the calculated parity is one in which low-frequency components have been sufficiently suppressed. Specifically, the DSV of the parity part is calculated,
It may be determined whether or not the absolute value is smaller than a preset threshold.

If this absolute value is smaller than the threshold value, it is determined that the generated parity code portion is one in which the low-frequency component has been sufficiently suppressed, and the generated parity code portion is generated without changing the fractional bits. Latch each parity
At 4,124,134, they are respectively latched, added to the information as it is, and output.

On the other hand, when the DSV is larger than the threshold value, it is determined that the generated parity code portion has a low frequency component, and the parity is not output and is kept in a holding state. Also, a pulse is input to the counter 143, the bit pattern inserted in the fractional bit is incremented, and the inserted value of the fractional bit is sequentially updated. Then, the new bit pattern is used as a new fraction bit, parity is calculated again, and the determination circuit 142 determines again whether or not the new parity bit pattern has a low frequency component.
The above operation is repeated until a parity of the pattern in which the low frequency component is suppressed is generated.

At this time, the adder 107 adds the value generated by the counter 143 and the latched symbol as described above,
Correct symbols containing fractional bits. Of course, the addition at this time is performed only for a portion corresponding to a fractional bit, and in practice, the above correction is performed by addition of Galois fields (exclusive OR for each bit).

On the other hand, the correction of the parity can be realized as follows. Now, the symbols including the fractional bits, j th symbols on information, i.e. assuming that i was _j, may be redone only computation of terms related to the i _j during the aforementioned parity calculations. That is, P _{1, j} ,
P _{2, j} ···· P _K, conducted multiplication only fractional bits of _j and the information i _j, may be respectively added to the calculation result in the case of an all zero fraction bits Calculated earlier. Note that when the multiplication of fraction bits only information i _j, the other bits of the insertion value to information i _j may be performed multiplication as 0.

The parity ROM 144 in FIG. 1 stores the result obtained when the output value of the counter 143 is input and the above-described matrix operation is performed in accordance with the input value. Accordingly, the output of the parity ROM 144 is supplied to the adders 113, 123, and 133, and added to the parity when the already calculated fractional bits are all zero, thereby realizing the parity correction. Parity recalculated by such an operation is again
The optimum parity is selected by being input to the bit pattern detection circuit 141 and repeating the above-described determination-correction operation.

At this time, in the repetitive calculation, only when a parity pattern with less low frequency components than before is obtained,
The parity is latched by the latches 114, 124, and 134. At the same time, the symbol including the fractional bit changed by the insertion bit pattern at that time is also latched by the latch. With this configuration, the parity of the optimal pattern is finally latched in the latches 114, 124, and 134.

Here, when the unused bits are, for example, 4 bits, 00
Even if all bit patterns other than 00 are inserted and calculations are performed accordingly, only 15 calculations are required, and the pattern with the lowest low-frequency component suppressed is selected from the parity obtained at this time. Can be performed in a short time.

In this case, instead of selecting the pattern in which the low-frequency component is suppressed the most, the above-described repetitive arithmetic processing is terminated when a parity having a low-frequency component equal to or less than a predetermined threshold is obtained, and the parity at that time is changed. A configuration in which latch is performed can also be adopted. In this case, the operation time can be further reduced.

In addition, as a method of determining the low frequency component suppression state in the determination circuit 142, the size of the CDS value of each parity, the number of consecutive same level (0 or 1) check, or a condition determination combining them can be used. Can be considered.

The suppressed parity of the low frequency component determined as described above and the symbol whose fraction bit is changed are latched, respectively.
The information is latched at 108, 114, 124, and 134, and combined with other information i _a (a = 1,..., M, excluding j) outputted at the timing according to the data format shown in FIG. You. Then, a synchronization code or ID code for recording transmission is added to a predetermined position by the sub-information adding circuit 151 and output.

Note that the memory 103 performs an operation of delaying the stored data by the time required for the parity calculation.

By the above operation, it is possible to insert an appropriate bit pattern into the above-mentioned fractional bits and suppress low-frequency components of the parity part.

In this embodiment, an example in which the number of parities is 3 is shown, but the present invention is not limited to this. or,
It is also possible to adopt a configuration in which a dummy code is separately prepared. Furthermore, it goes without saying that the present invention can be applied to error detection and correction codes other than Reed-Solomon codes.

[Effects of the Invention] As described above, according to the code transmission method of the present invention,
Even when a continuous portion of the error detection and correction code exists in the code sequence to be transmitted, the low frequency component of the code sequence can be sufficiently suppressed, and good code transmission can be performed. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a main configuration of a recording apparatus to which the code transmission method of the present invention is applied, FIG. 2 is a diagram showing an example of a configuration of a parity calculation circuit shown in FIG. 1, FIG. FIG. 4 is a diagram showing a data format of a code sequence transmitted by the configuration of FIG. 1, and FIG. 4 is a schematic diagram showing a configuration example of a general data format of the code sequence. In the figure, 101 is a compression encoding circuit, 102 is a mapping encoding circuit, 103 and 104 are memories, 105, 106, 108, 112, 114, 122, 124, and 1
32,134 are latches, 107,113,123,133 are adders, 1 respectively
11, 121, and 131 are parity calculation circuits, 141 is a bit pattern detection circuit, 142 is a determination circuit, 143 is a counter, and 144 is a parity ROM.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ identification symbol FI H04L 25/49 H04L 25/49 A (58) Field surveyed (Int.Cl. ⁶ , DB name) G11B 20/14 G11B 20 / 18 H04L 1/00 H04L 25/49 H03M 13/00

Claims (2)

(57) [Claims] 1. A code transmission method in a case where a code group used for calculation at the time of generation of an error detection / correction check code includes a fractional bit corresponding to a fractional bit number of a main information code, wherein the calculated error detection code is used. A code transmission method comprising: detecting a bit pattern of a correction check code; and changing a value of the fractional bit according to a result of the detection. 2. The main information code includes a plurality of symbols each including a plurality of compression codes obtained by compressing sample values of an information signal, and the number of the compression codes in the last symbol of each code group is different from that of other symbols. The code transmission method according to claim 1, wherein the number of the compression codes is smaller than the number of the compression codes.