JP2799753B2 - Pulse width modulation controller - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse width modulation control device (hereinafter referred to as a PWM control device) in a power supply device such as a copying machine or a printer.

[Conventional technology]

2. Description of the Related Art Conventionally, power supply devices such as copiers and printers generally use an analog pulse width modulation circuit.

In recent years, with the development of semiconductor technology, microcomputers have become inexpensive, highly integrated, and sophisticated, and various control circuits have been incorporated into microcomputers that have been used for sequence control of equipment.
There has been an increasing trend in various fields to construct a highly reliable, high-performance, compact, and low-cost system by integrating the system into one chip.

Similarly, a digitally controlled power supply device that can be incorporated in a microcomputer and that can easily exchange data with the microcomputer has been proposed.

[Problems to be solved by the invention]

The following problems are conceivable in the digital control type power supply device.

As a digital control method, it is necessary to have a data holding means such as a register in order to enable data exchange with a microcomputer. As is known, the power supply device is a noise source such as radiation noise, and there is a possibility that the output of the data holding means such as a register changes and the output becomes abnormal.

In the case of the above state, not only the power supply device but also the system may be seriously damaged, thereby lowering the reliability of the system.

The present invention has been made to solve the above-described conventional problems, and has as its object to provide a PWM control device applicable to a system requiring high reliability.

[Means for solving the problem]

For this reason, in the present invention, an up / down counter for determining the increase / decrease of the period of the pulse width modulation output pulse, an up / down control circuit for controlling the count up and count down of the up / down counter, A down counter that counts down the count output value of the down counter as its maximum value, and a count value determination circuit that outputs a data set signal indicating the timing of starting the next pulse signal formation according to the count value of the down counter. A waveform shaping circuit for generating a pulse width modulation output pulse in accordance with the output of the up / down counter and the down counter and a signal of a data latch; and .Data transmitted to the down control circuit And the up / down control circuit is configured to increase or decrease the pulse width of the up / down counter when the pulse width and the pulse duty of the up / down counter become equal to or less than a predetermined first specified value. Stopping means for stopping the operation, and when the pulse width and the pulse duty become equal to or greater than a predetermined second specified value, a repetition limiting means for repeating the pulse width increasing / decreasing operation of the up / down counter at a predetermined cycle. And a pulse width modulation control device.

Another object of the present invention is to provide a pulse width modulation control device characterized in that the data latch is omitted.

[Action]

With the above configuration, the up / down counter value for determining the pulse width is compared with a prescribed value to limit the up / down counter pulse width increase / decrease operation repeatedly, or By stopping the increase / decrease operation, abnormal operation due to erroneous recognition of data due to noise around the power supply or external noise can be prevented, and a highly reliable system can be easily configured.

Further, the data latch can be omitted, and each prescribed value can be set as a fixed value in hardware in each block.

〔Example〕

(Embodiment 1) FIG. 1 is a block diagram of Embodiment 1 according to the present invention, and FIG. 2 is a block diagram showing only a basic configuration of a pulse width modulation control device according to the present invention. In the drawings, the same reference numerals indicate the same (corresponding) components.

Hereinafter, first, the basic configuration of the PWM control device according to the present invention will be described first with reference to FIG. 2, and then the details will be described.

That is, in FIG. 2, reference numeral 1 denotes an up / down control circuit, which is a circuit for controlling the count up and count down of an up / down counter 2 (hereinafter referred to as a U / D counter). / D counter 2 is connected to the clock input terminal,
The U / D control terminal is connected to the U / D counter 2
Connected to U / D control signal input terminal.

Further, a feedback signal terminal 8 for control by pulse width modulation (hereinafter referred to as PWM) is connected to a feedback signal input terminal of the up / down control circuit 1 through a signal line 9. The count value of U / D counter 2 is signal line 1.
1 is connected to the data input terminal of the down counter 3 and the U / D count data input terminal of the waveform shaping circuit 5. The count value data output terminal of the down counter 3 is connected via a signal line 12 to the data input terminal of the count value determination circuit 4a and the terminal of the waveform shaping circuit 5 to which the down counter data has been input. The count value determination circuit 4a
On the signal line 13 according to the count value of the down counter 3
This is a circuit having a function of terminating the pulse output of one cycle of the PWM signal and outputting a data set signal indicating the timing of starting the next pulse signal formation. Data set signal line
13 is connected to the control signal input terminal of the waveform shaping circuit 5. A part of the signal of the data latch 6 is further input to the waveform shaping circuit 5 through a signal line 14. Therefore, the waveform shaping circuit 5 generates a PWM output according to the signals on the signal lines 11, 12, 13, 14, and 15, and outputs a PWM signal to the PWM signal output terminal 17 through the signal line 16. The signal line 13 is connected to the down counter 3, the up / down control circuit 1, and the data set signal input terminal of the data latch 6. The data latch 6 receives control data of a central processing unit (hereinafter referred to as a CPU) 7 through a signal line 18 and transmits it to the waveform shaping circuit 5 and the up / down control circuit 1 through signal lines 14 and 19. 7-1 is a signal line for transmitting a write signal for writing information to the data latch 6 by the CPU 7.

A clock signal that provides a reference for the timing of the entire circuit is connected to a down counter 3, a count value determination circuit 4a, and a clock signal input terminal of the waveform shaping circuit 5 through a signal line 15.

 Next, the operation of FIG. 2 will be described.

The CPU 7 sends control data for controlling the PWM controller to a signal line 1.
8 and at the same time, a write signal is output to the signal line 7-1, and data for controlling the PWM control device is set on the data latch 6. However, the data is output on the signal lines 14 and 19 at the rising timing of the data set signal on the data set signal line 13. Here, the value of 1 on the signal line 13 is a data set signal. When 1 rises on the signal line 13, the waveform shaping circuit 5 is set, and operates so that 1 is output to the PWM signal output terminal 17 through the signal line 16. Also, U /
The output value of D counter 2 is set. The up-down control circuit 1 operates in synchronization with the rising and falling edges of the data set signal (load signal) on the signal line 13. That is, the up-down control circuit 1 is connected to the signal line 13
The feedback signal input terminal 8 and the data signal line 19 are synchronized with the rising timing of the upper data set signal.
The state of the upper signal (first control data) is determined, and the signal line 10
The data to be output above is determined, and a clock is output on the signal line 20 in synchronization with the falling timing of the load signal to increase or decrease the count output value of the U / D counter 2 by one. Or U / D of U / D counter 2
A clock for counting up or down is not output on the signal line 20 to stop the counting operation.

The down counter 3 sets the count output value of the U / D counter 2 as its maximum value and decreases the count value of the down counter 3 from that value each time the clock signal on the signal line 15 changes from 1 to 0. I do. Then, the waveform shaping circuit 5 takes in the count output value of the downcounter 3 through the signal line 12, and puts the control data (second control data) on the signal line 14 and the rising edge of the clock signal on the signal line 15. A comparison is made at the falling edge, and when the two values match, the data output to the PWM signal output terminal 17 through the signal line 16 is changed from 1 to 0 to control the duty of the signal output to the output terminal 17. I do. The waveform shaping circuit 5 also transmits data on the signal line 11 to the signal line 13.
It takes in at the falling edge of the above signal, compares the value with the output operation control data given on the signal line 14, and compares the data on the signal line 11 with the output operation control data given on the signal line 14. When small, PWM signal output pin 1
7 simply becomes 1, the output of the PWM signal is stopped, and the PWM signal is output only when the output is large. The down counter 3 operates in synchronism with the falling edge of the clock signal applied to the signal line 15 when all the flip-flops constituting the down counter 3 operate.
The operation of the down counter 3 stops, and the count output value of the signal line 12 is changed to data on the signal line 11 and is maintained as it is.

Now, consider an operation state in which the data on the signal line 11 is larger than the output operation control data given on the signal line 14.

The count value judging circuit 4a judges the count value of the down counter 3 at each falling edge of the clock signal on the signal line 15 through the signal line 12, and sets the data value on the signal line 13 at a predetermined value near the zero value. Outputs the signal and the signal line 13
The data set signal was output above (load state)
Is determined at each falling edge timing of the clock signal on the signal line 15, and if the data is detected, the data set signal on the signal line 13 is reset, and It works to be.

Since the present embodiment operates in synchronization with the data set signal in this manner, the frequency of the clock signal input on the signal line 15 is increased to 16 MHz to 30 MHz, for example, in order to increase the control accuracy of the external control circuit by the PWM output signal. Even if it is raised to the extent, by increasing the pulse width of the data set signal output on the signal line 13, malfunction can be prevented in the circuit, and the duty control of the PWM signal can be easily and accurately performed.

Next, a first embodiment according to the present invention will be described in detail. In addition,
FIG. 1 will be described with a particular emphasis on the up-down control circuit 1.

In the figure, a comparator 1-a for detecting a maximum value is provided inside an up-down control circuit 1, and data of a data latch 6 is inputted through a signal line 19. Also,
The count value of the U / D counter 2 is input through a signal line 11. The output of the comparator 1-a for maximum value detection is latched by the data holding means 1-d.

The count value of the U / D counter 2 is connected to a counter limiter 1-c through a signal line 11.
The output of the counter limiter 1-c is held by the data holding means 1-f. Reference numeral 1-g denotes an AND circuit to which a signal input from the field-back input terminal indicated by the input terminal 8 and a signal from the data holding means 1-d are input. And (AN
D) The output of the circuit 1-g is connected to the up / down control terminal of the U / D counter 2 via ten signal lines.

 Next, the operation of FIG. 1 will be described.

The CPU 7 has a control data signal line 18 for controlling the PWM controller.
It is assumed that a write signal is output to the signal line 7-1 at the same time, and data for controlling the PWM control device is set on the data latch circuit 6 to start the operation.

In a normal operation, when the control is performed at a predetermined value, the value input to the feedback signal 8 is a digital binary value here. doing. However, for some reason, the up / down counter value of the up / down counter 2 takes an abnormal value or the data latch 6
When any abnormal data is set in the system, such as when an abnormal value is set in the PWM control apparatus of the present embodiment, the following operation is performed by the means for repeatedly limiting the increase and decrease of the pulse width and the means for stopping the operation.

[1] When the output value of the up / down counter 2 becomes equal to or less than a predetermined first specified value.

[2] When the output value of the up / down counter 2 becomes larger than the second prescribed value of the maximum value set by the data latch 6.

Next, the operation of the above [1] and [2] will be described in detail.

In the case of [1], the counter limiter 1-c compares the preset fixed value with the output value of the up / down counter 2 input via the signal line 11.
In this case, the output of the counter limiter 1-c becomes 1 when the value becomes equal to or smaller than a preset fixed value.

This result is held in the data holding means 1-f, and based on this result, the RESET terminal of the frequency divider 1-k changes from 0 to 1 to bring it into the RESET state. Thus, the clock at the up / down clock terminal of the up / down counter 2 at the next stage is stopped, and the output value of the up / down counter 2 is fixed.

Therefore, the output pulse becomes a signal having a specified pulse width, and the output is fixed.

In the case of [2], the maximum value detection comparator 1-a compares the value set in the data latch 6 with the output value of the up / down counter 2 input via the signal line 11.

This result is held in the data holding means 1-d, and further input to the feedback signal 8 and the AND circuit 1-g. That is, here, the relationship between the output of the feedback signal terminal 8 and the output of the normal AND (AND) circuit 1-g is, as described above, that when the output is high, the feedback signal terminal 8 is 0 when the output is high. The output of -g becomes 1, whereby the up-down control terminal of the up-down counter 2 becomes 1, so that the pulse width increases. Conversely, when the output is low, the feedback signal terminal 8 is set to 1 and the AND circuit 1-
The output of g becomes 0, which causes the up-down control terminal of the up-down counter 2 to become 0, so that the pulse width is reduced.

When the output of the data holding means 1-d held as described above is input to the AND circuit 1-g, 0
From 1 to 1 when the output is high
D) The output of the circuit 1-g becomes 0, whereby the up-down control terminal of the up-down counter 2 becomes 0, so that the pulse width is reduced.

As a result of the above operation, the pulse width returns to the normal state from the state where the detection level was at the detection level by the maximum value detection comparator 1-a in order to decrease, and the output of the maximum value detection comparator 1-a and the data When the output of the holding means 1-d changes from 1 to 0, the AND circuit 1-g
Also returns to the original state.

By repeating the above operation, the output also repeats up and down with a predetermined width, and the pulse width becomes a vibration state where the pulse width also repeats up and down with a predetermined width.

Second Embodiment FIG. 3 is a block diagram of a second embodiment according to the present invention.
The same (corresponding) components as those in the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and redundant description will be omitted.

In the figure, a data buffer for the counter limiter 1-c is prepared without setting a predetermined fixed value in the counter limiter 1-c, and data can be set by the CPU through the signal line 21. This makes it possible to produce a more reliable system by setting the optimum limiter value each time according to the output setting state.

Third Embodiment FIG. 4 is a block diagram of a third embodiment according to the present invention.
Embodiment 1 and Embodiment 2 shown in FIGS. 1 to 3
The same (corresponding) components as those described above are denoted by the same reference numerals, and redundant description will be omitted.

In the figure, neither the counter limiter 1-c nor the maximum value detection comparator 1-a has a data buffer, and a predetermined fixed value is set for each, thereby simplifying the circuit and configuring a low-cost system.

〔The invention's effect〕

As described above, according to the value of the up / down counter for determining the pulse width, the means for repeatedly limiting the pulse width increase / decrease operation of the up / down counter and the pulse width increase / decrease of the up / down counter are provided. The provision of the means for stopping the operation has the following effects.

I. In digital control of power supply, it has become possible to easily configure a highly reliable system.

In particular, it becomes easy to prevent abnormal operation due to erroneous data recognition due to noise around the power supply or external noise.

B. If the data exceeds the second specified value and becomes abnormal due to extraneous noise, the above-mentioned up / down /
It is a configuration in which the pulse width increase / decrease operation of the counter is repeated at a predetermined cycle to repeatedly limit the increase / decrease operation, preventing power supply destruction beforehand, and further, when it becomes less than a predetermined first specified value,
By using the means for stopping the output of the up / down counter, it becomes possible to prevent the output from becoming abnormal even before the power supply is destroyed, thereby preventing the externally connected system from becoming abnormal.

C. If the data latch is omitted and each specified value is set as a fixed value in hardware in each block, the data set between CPUs becomes unnecessary, the circuit can be downsized, and it can be applied to a less expensive system. It is.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram showing only a basic configuration of a pulse width modulation control device of the present invention, and FIG. 3 is a block of a second embodiment of the present invention. FIG. 4 is a block diagram of the third embodiment. In the drawings, the same reference numerals indicate the same (corresponding) components. 1 is an up-down control circuit, 1-a is a maximum value detection comparator, 1-c is a counter limiter, 1-d and 1-f are data holding means, 1-g is an AND circuit, and 1-k is a frequency divider. Reference numeral 2 denotes an up / down counter, 6 denotes a data latch, and 7 denotes a CPU.

Claims (2)

(57) [Claims] 1. An up / down counter for determining an increase or a decrease in a period of a pulse width modulation output pulse, an up / down control circuit for controlling the count up and count down of the up / down counter, and the up / down counter. A down counter for counting down the count output value of the counter as its maximum value;
A count value judging circuit for outputting a data set signal indicating the timing of the start of the next pulse signal formation in accordance with the count value of the counter; A waveform shaping circuit for generating an output pulse; and a data latch for holding control data of a central control unit and transmitting the data to the waveform shaping circuit and the up / down control circuit, wherein the up / down control circuit includes the up / down control circuit. down·
When the pulse width and the pulse duty of the counter become equal to or less than a predetermined first specified value, the up / down /
Stopping means for stopping the pulse width increasing / decreasing operation of the counter, and when the pulse width and the pulse duty become equal to or more than a predetermined second specified value, the pulse width increasing / decreasing operation of the up / down counter is performed at a predetermined cycle. A pulse width modulation control device comprising: a repetition limiter. 2. The pulse width modulation control device according to claim 1, wherein said data latch is omitted.