JP2796763B2 - Print head control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention requires that the width of a pulse applied to a print head be made different depending on whether printing is a single shot, the beginning of continuous printing, the middle of continuous printing, or the end of continuous printing. Printer device having a piezoelectric head, for example.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a control block of the whole printer. In the figure, 1 is a processor, 2 is a program ROM, 3 is a work RAM, 3a is print data,
A line buffer, 4 an interface controller, 5 a mechanical status monitor, 6 a mechanical controller, 7 a printhead controller, 8 a mechanical driver, 9 a printhead driver,
10 is a paper feed motor, 11 is a carrier motor, 12
Denotes another motor, and 13 denotes a print head.

[0003] The processor 1 executes a program stored in a program ROM 2. Program ROM
Various programs exist in 2. Work RAM
3 stores temporary data. The print data line buffer 3a also exists in the work RAM 3. The interface control unit 4 is connected to a main unit (not shown) via an interface cable, and receives data from the main unit and transmits data to the main unit.

The mechanical state monitoring unit 5 monitors a signal from a paper sensor, a signal from a mechanical sensor, and a signal from an encoder, and notifies the processor 1 when the state of the signal changes. Further, the mechanical state monitoring unit 5 generates a print trigger CK (clock) based on the position information from the encoder. The print trigger CK activates the print head
Generated every time the carrier mounted moves a certain distance.
This print trigger CK is sent to the print head controller 7.
The mechanical control unit 6 outputs a drive signal for the paper feed motor 10, the carrier motor 11, the other motor 12, and the like based on a command from the processor 1. The drive signal output from the mechanical control unit 6 is sent to the paper feed motor 10, carrier motor 11, other motors 12 and the like via the mechanical driver 8.

The print head controller 7 generates an on-time signal I and an on-time signal II for driving the print head based on the received print data, and sends these signals to the print head driver 9. The print head driver 9 switches the output from a low level to a high level when receiving the on-time signal I, and switches the output from a high level to a low level when receiving the on-time signal II. The output of the print head driver 9 is
Sent to The print head 13 is, for example, a piezoelectric head having 24 pins arranged in a staggered manner in four rows.

The operation of the printer shown in FIG. 8 will be described. Upon receiving the print command from the interface, the processor 1 edits one line of print data in the print data line buffer 3a of the work RAM 3. Thereafter, the carrier motor 11 and the paper feed motor 10 are controlled, and when printing is possible, the print data is sequentially transferred from the print data line buffer 3a to the print head controller 7. A print trigger CK generated based on the position information from the encoder or a delayed print trigger CK is sent to the processor 1 as a print data request. When receiving the print data request, the processor 1 sends the next print data to the print head controller 7.

FIG. 9 is a diagram for explaining various signals in the piezoelectric printer. The print trigger clock is a basic timing signal for driving the print head, and has a certain periodicity suitable for the performance of the print head. As mentioned above,
The print trigger clock is generated based on position information from the encoder. The delay timer signal is a signal that is delayed by a predetermined time from the print trigger clock.

The on-time signal is a logical level signal (timing signal) for driving the print head, and gives a drive on / off timing to the print head driver. There are two types of on-time signals, an on-time signal I and an on-time signal II. The on-time signal I is generated based on a print trigger clock, and the on-time signal II is generated based on a delay timer signal. The time difference between the delay timer signal and the on-time signal II differs depending on whether it is a continuous first dot, a continuous halfway dot, a continuous last dot, or a single dot. Continuous means that the print pin is driven continuously for each print trigger clock, and single-shot means that the print pin is not driven in the preceding and subsequent print trigger clock cycles. As shown in the figure, in the case of continuous first, continuous middle, and continuous last, the interval between the delay timer signal and the on-time signal II is determined by the period t of the print trigger clock.
In the case of a single shot, the interval between the delay timer signal and the on-time signal II is larger than t and smaller than 2t.

FIG. 10 is a view for explaining a piezoelectric head.
The piezoelectric element converts electric vibration into mechanical vibration.
As shown in FIG. 3A, the mechanical vibration of the piezoelectric element is amplified by a vibration amplification mechanism, and the amplified mechanical vibration is transmitted to the print pin. FIG. 2B shows the output of the driver of the piezoelectric head, and shows the on-time signal I (charging pulse).
Is generated, the driver output rises and the on-
When the IM signal II (discharge pulse) is generated, the output of the driver falls.

FIG. 11 is a diagram showing an example of a conventional circuit configuration.
In the figure, 14 is a delay circuit, 15 to 18 are registers, 19 is a print data buffer, and 20 is a flip-flop.
Flop, 21 to 24 are gates, 26 to 29 are comparators, 31 to 34 are AND gates, 35 is OR gate, 36 is NAND gate, 37 is JK flip-flop, 38 is counter, 39 is printing per pin Each shows a pulse II generation circuit. It should be noted that, as shown in FIG. 11
The equipment present in the print head control unit 7 of FIG.

[0011] The delay circuit 14 is equivalent to the delay timer of Figure 9. The register 15 is set with the interval value between the delay timer signal and the on-time signal II in the case of a single shot, and the register 16 is stored in the register 16 with the delay timer signal and the on-time signal II in the first consecutive case.
The interval value between the delay timer signal and the on-time signal II in the case of continuous operation is set in the register 17, and the delay timer signal in the last case of the continuous operation is set in the register 18. The interval value of the on-time signal II is set.

The print data buffer 19 is a shift register. The print pulse II generation circuit 39 shown in FIG.
Assuming that the print data corresponds to the i-th print pin, print data for the i-th print pin is sequentially input to the print data buffer 19. Print data buffer 1
The output signal S1 from 9 indicates whether there is previous data,
The output signal S2 indicates whether there is current data, and the output signal S3 indicates whether there is next data. Signals S1, S2,
S3 is held in the flip-flop 20. NAND
Gate 36 outputs a pulse when a pulse is output from delay circuit 14 while output signal S2 is on.
When this pulse is output, the flip-flop 20
Captures the output signals S1, S2, S3.

The gate 21 outputs "1" when the condition 1 is satisfied, the gate 22 outputs "1" when the condition 2 is satisfied, and the gate 23 outputs "1" when the condition 3 is satisfied. The gate 24 outputs "1" when the condition 4 is satisfied. Condition 1 is that the current dot is a single dot, condition 2 is that the current dot is the first of the continuous dots, condition 3 is that the current dot is in the middle of the continuous dots, and condition 4 is that the current dot is in the middle of the continuous dots. That is, the dot is the last of the continuous dots.

When the NAND gate 36 outputs a pulse in the negative direction, the flip-flop 37 is set, and the counter 38 starts counting time. The comparator 26 compares the content of the register 15 with the count value of the counter 38, and outputs "1" when they match. Comparators 27, 28, 2
9 performs the same operation. When the comparator 26 outputs "1", the counter 38 returns to the initial value and enters the stopped state.

The AND gate 31 outputs "1" when both the comparator 26 and the gate 21 output "1". The AND gates 32, 33, and 34 perform the same operation. The output of the AND circuits 31 to 34 is the OR circuit 35
Is input to The output of the OR gate 35 is an on-time signal
II.

[0016]

As described above, the time difference between the delay timer signal and the on-time signal II differs depending on whether it is the beginning of continuous printing, the middle of continuous printing, the end of continuous printing, or single-shot printing. In some cases, the difference is longer than the printing cycle. In the conventional method, it is necessary to have a timer for counting the time difference as described above for each print pin, and thus the circuit scale is enormous. The present invention has been made in view of the above point, and has as its object to reduce the circuit scale of a circuit for generating an on-time signal II of a serial printer.

[0017]

FIGS. 1 and 2 are diagrams for explaining the principle of the present invention. A print head control method according to the present invention includes a print head having a plurality of print pins, a print head control unit that outputs an on-time signal I and an on-time signal II when driving the print pins, and an on-time signal I. Is output, the print pin drive signal rises, and when the on-time signal II is output, the print pin drive signal falls, the print head control method in a printer device having a print head driver, The print head control unit has a pulse generator and a print pulse output unit for each print pin .
Switch clock that is delayed by the specified time
Switching clock generating means, and the trailing edge coincides with the switching clock
First print to generate print pulse for on-time signal I
The pulse generation means and the time counter are opened when the start signal is received.
Was started, click when the time count was Tsu Na to a predetermined value
Receiving the start-up signal and the clocking mechanism on the A side that enters the rear state
And start time counting, and the time counting value reaches a predetermined value.
A timer mechanism B side becomes clear state when it is, switching
Each time a clock is generated, the logic of the timer select signal
A value is switched, and the A side is synchronized with the odd-numbered switching clock.
Generates a start signal for the timer of
In synchronization with the clock, the start signal for the clocking mechanism on the B side
A switching circuit for generating four output terminals on the A side and four B terminals
And an output terminal on the A side, and the value of the clocking mechanism on the A side is N _i (i
Is 1, ..., 4), the i-th output terminal on the A side
Output a print pulse for the on-time signal II to the
When the value of the clocking mechanism becomes N _i (i is 1, ..., 4)
Is connected to the i-th output terminal on the B side for the on-time signal II.
And a second print pulse generating means for outputting a printing pulse, the printing pulse output unit of each printing pin, comes sent by
1 bit in synchronization with the leading edge of the switching clock
Shift register type print data buffer
And the state of the print data buffer is predetermined
The condition that is, the first print pulse generating means
Therefore, the generated print pulse is used as the on-time signal I.
First print pulse output means for outputting, and a shift register
Output of the predetermined stage of the print data buffer
When a switching clock is generated under a value indicating condition
The state latch clock that generates the state latch clock
Clock generation means and when a status latch clock is generated
A select signal storage means for capturing a timer select signal in synchronization with the trailing edge of a state latch clock, status latch
State latch clock when the master clock is generated
Captures and stores print data buffer status at trailing edge
The print information storage means for performing the operation and the select signal output from the select signal storage means when the select signal has one logical value .
Output from the four output terminals on the A side of the print pulse generation means.
Select the printing pulse group that, when the select signal is in the other logic value B side of the second printing pulse production formation means
Group selecting means for selecting a print pulse group output from the four output terminals of the group, and print information from a print pulse group selected by the group select means.
1 based on the printing conditions determined by the state of the information storage means.
A second print pulse output means for selecting print pulses and outputting the selected print pulse as an on-time signal II.
And a step .

[0018]

The print trigger clock is turned off as shown in FIG .
It is input to the conversion clock generation means. Switching clock generator
The stage switches the clock after a predetermined time from the print trigger clock.
Generate a lock. The first printing pulse generating means has a trailing edge
Print pulse for on-time signal I that matches switching clock
Generate The switching circuit generates a switching clock
Switching the logical value of the timer select signal each time
And the clocking mechanism on the A side in synchronization with the odd-numbered switching clock
And generates an activation signal for
Synchronously, an activation signal for the clock mechanism on the B side is generated.

When the clocking mechanism on the A side receives the activation signal,
Time counting starts, and when the time counting value reaches a predetermined value,
State. The timing mechanism on side B is the same as the timing mechanism on side A.
Performs similar operations. A side clock mechanism and B side clock mechanism
Can be counted up to 2t. Where t
Is the cycle of the print trigger clock.

[0020] When the value of the A side of the counting mechanism is _{N 1,} the second
From the first output terminal on the A side of the print pulse generating means
Printing pulse is output, the value of the A-side of the timing mechanism it to N ₂
Then, a print pulse is output from the second output terminal on the A side.
Is the value of the A-side of the timing mechanism is N _3, the third A-side
The print pulse is output from the output terminal No.
When the value of the mechanism is N _4, or the fourth output terminal of the A-side
Output a print pulse. From the first output terminal
Printing pulse corresponds to the single printing, or the second output terminal
These print pulses correspond to the beginning of continuous printing, and the third
The print pulse from the output terminal corresponds to the middle of continuous printing,
The printing pulse from the fourth output terminal is in the middle of continuous printing
Corresponding to N ₁ is smaller than 2t at greater than t. B
A similar operation is performed on the side.

As shown in FIG . 2, a print data buffer
Is input with print data. Print data buffer
Is of the shift register type. Print data is bit
Print one bit at a time in synchronization with the switching clock
Input to the data buffer. First print pulse output
Means that the state of the print data buffer is in a predetermined state;
Print pulse for the on-time signal I
Is output as an on-time signal I. Black for status latch
Means for generating a print data buffer at a predetermined stage of the print data buffer.
Is generated under the condition of a predetermined logic value
And outputs a state latch clock. Status latch
When a lock is generated, the contents of the print data buffer are
In addition to being taken into the print information storage means,
The select signal is taken into the select signal storage means.

In the group selecting means, for example, the logical value of the select signal output from the select signal storing means is "1".
In the case of, the print pulse group on the A side is selected and output,
If the logical value of the select signal is "0", the print pulse group on the B side is selectively output. Second print pulse output
Means are selected from the selected print pulse group.
Based on the printing conditions determined by the state of the character information storage
Select the print pulse and turn on the selected print pulse
Output as time signal II.

[0023]

FIG . 3 is a block diagram showing a configuration example of a pulse generator according to the present invention. In the figure, 40 is a delay circuit, 4
1 is a counter, 42 to 44 are registers, 45 to 47 are comparators, 48 to 50 are JK flip-flops, 51 is a D flip-flop, 52 and 53 are gates, 54 is an AND gate, and 55 is a switching circuit. Is shown.

The circuit shown in FIG . 3 is a portion for generating a print pulse I. Printing trigger signal is input to the delay circuit 40, the slow
The output of the extension circuit 40 becomes a trigger for the print pulse I. Printing
The trigger for pulse I is JK flip-flop 48,4
It is input to 9,50 J input terminals. The normal output of the JK flip-flop 48 is input to the D flip-flop 51, and the output of the D flip-flop 51 is input to the upper input terminal of the AND gate 54. The normal output of the JK flip-flop 48 is input to the clear terminal of the counter 41. The inverted output of the JK flip-flop 48 is input to the lower input terminal of the AND gate 54.
The output of AND gate 54 is switching clock, and the Setsu換Ku
The lock is input to the switching circuit 55. The comparator 45 compares the value of the counter 41 with the value of the register 42, and applies “1” to the K input terminal of the JK flip-flop 48 when they match.

The non-inverted output of the JK flip-flop 49 is input to the lower input terminal of the gate 52. The normal output of the JK flip-flop 48 is input to the upper input terminal of the gate 52. The output of the gate 52 is the print pulse I
(Single shot). The comparator 46 compares the value of the counter 41 with the value of the register 43, and when both match, “1” is J.
Applied to the K input terminal of the K flip-flop 49.

The normal output of the JK flip-flop 50 is input to the lower input terminal of the gate 53. The non-inverting output of the JK flip-flop 48 is input to the upper input terminal of the gate 53. The output of the gate 53 is the print pulse I
(Continuous). The comparator 47 compares the value of the counter 41 with the value of the register 44, and when both match, "1" is J.
Applied to the K input terminal of the K flip-flop 50.

The switching clock is input to the switching circuit 55. The value of the timer select signal output from the switching circuit 55 is inverted each time the switching clock is input.
The counter A trigger signal is generated each time an odd-numbered switching clock is input, and the counter B trigger signal is generated each time an even-numbered switching clock is input.

FIG . 4 is a diagram showing a configuration example of the pulse generator (continued) of the present invention. In the figure, 61 to 64 are registers, 66A to 69A are comparators, 66B to 69B are comparators, 71 to 74 are registers, 76A to 79A are comparators, 76B to 79B are comparators, 8
1A to 84A are JK flip flops, 81B to 84B are also JK flip flops, 85A and 85B
Also, JK flip-flops and 86A and 86B indicate counters, respectively.

FIG . 4 shows a portion for generating the print pulse II. Registers 61 and 71 specify the rise time and fall time of the print pulse II in the case of one-shot printing, and the registers 62 and 72 define the rise time and fall time of the print pulse II in the first case of continuous printing. The register 63 and the register 73 define the rise time and the fall time of the print pulse II in the middle of the continuous printing, and the register 64 and the register 74 define the print pulse in the middle of the continuous print. II defines the rise time and fall time.

Since the configuration and operation of the A-side circuit portion and the B-side circuit portion in FIG . 4 are the same, only the A-side circuit portion will be described. When the counter A trigger signal is generated, the JK flip-flop 85A is set, and the counter 86A starts counting time . When the value of the counter 86A becomes equal to the value of the register 61, the comparator 66A outputs "1", the JK flip-flop 81A is set, and the pulse A for condition 1 rises. Counter 86
When the value of A becomes equal to the value of the register 71, the comparator 76
A outputs "1", the JK flip-flop 81A is reset, and the pulse A for condition 1 falls. When the comparator 76A outputs "1", the JK flip-flop 85A is reset and the counter 86A is cleared. The value of the register 71 is the largest among the registers 61 to 64 and 71 to 74.

When the count value of the counter 86A becomes equal to the value of the register 62, the comparator 67A outputs "1",
The K flip-flop 82A is set, and the pulse A for condition 2 rises. The value of the counter 86A and the register 7
When the values of 2 are equal, the comparator 77A outputs "1", the JK flip-flop 82A is reset, and the pulse A for condition 2 falls. The pulse A for condition 3 and the pulse A for condition 4 are generated in the same manner.

FIG. 5 is a diagram showing the signal timing of the pulse generator of the present invention. The switching clock is generated behind the print trigger pulse by an amount determined by the delay amount of the delay circuit 40 and the value of the register 42. The timer select signal rises in synchronization with the odd-numbered switching clock (the first being the first) and falls in synchronization with the even-numbered switching clock . Counter A trigger is odd-numbered off
The counter B trigger is generated in synchronization with the switching clock, and the counter B trigger is generated in synchronization with the even-numbered switching clock .

The pulse A for condition 1 rises after a time determined by the value of the register 61 after the counter A trigger is generated, and falls after a time determined by the value of the register 71.
The pulse A for condition 2 rises after a time determined by the value of the register 62 from the generation of the counter A trigger, and falls after a time determined by the value of the register 72. The pulse A for condition 3 is stored in the register 63 after the counter A trigger is generated.
Rises after the time determined by the value of the register 73, and falls after the time determined by the value of the register 73. The pulse A for condition 4 rises after a time determined by the value of the register 64 from the generation of the counter A trigger, and falls after a time determined by the value of the register 74.

The pulse B for condition 1 rises after a time determined by the value of the register 61 since the counter B trigger is generated, and falls after a time determined by the value of the register 71.
The pulse B for condition 2 rises after a time determined by the value of the register 62 since the counter B trigger is generated, and falls after a time determined by the value of the register 72. The pulse B for condition 3 is stored in the register 63 after the counter B trigger is generated.
Rises after the time determined by the value of the register 73, and falls after the time determined by the value of the register 73. The pulse B for condition 4 rises after a time determined by the value of the register 64 after the counter B trigger is generated, and falls after a time determined by the value of the register 74.

The print pulse I (single shot) rises after a time determined by the delay amount of the delay circuit 40 and the register 43 from the print trigger, and falls in synchronization with the switching clock . The print pulse I (continuous) rises after a time determined by the delay amount of the delay circuit 40 and the register 44 from the print trigger ,
It falls in synchronization with the switching clock .

FIG . 6 is a diagram showing a configuration example of a print pulse output unit for each pin according to the present invention. In the figure, 89 is a print data buffer, 90 is a flip-flop, 91 to 94 are gates, 96 to 99 are selectors, 101 to 104 are AND gates, 105 is an OR gate,
6 is a NAND gate, 107 is a JK flip-flop, 108 and 109 are gates, 110 is an OR gate, 1
Reference numeral 11 denotes a print pulse output unit per pin.

The print data buffer 89 is a shift register. Assuming that the illustrated print pulse output unit corresponds to the i-th print pin, print data for the i-th print pin is sequentially input to the print data buffer 89. The output signal S1 from the print data buffer 89 indicates whether or not there is previous data.
2 indicates whether there is current data, and the output signal S3 indicates whether there is next data. The signals S1, S2, S3 are held in the flip-flop 90. NAND gate 10
6 outputs a pulse when the switching clock is input while the output signal S2 is on. When this pulse is output, the flip-flop 90 outputs the output signals S1, S
2. Take in S3.

The gate 91 outputs "1" when the condition 1 is satisfied, the gate 92 outputs "1" when the condition 2 is satisfied, and the gate 93 outputs "1" when the condition 3 is satisfied. When the condition 4 is satisfied, the gate 94 outputs "1". Condition 1 is that the current dot is a single dot, condition 2 is that the current dot is the first of the continuous dots, condition 3 is that the current dot is in the middle of the continuous dots, and condition 4 is that the current dot is in the middle of the continuous dots. That is, the dot is the last of the continuous dots.

When the state latch CK is generated, the flip-flop 107 fetches a pulse select signal (synonymous with the timer select signal). The output of the flip-flop 107 becomes the select signal. Selector 96
Is the condition 1 pulse A when the select signal is "1".
Is selected, and if the select signal is "0", the pulse B for condition 1 is selected. Other selectors 97 to 98
Performs the same operation as the selector 96.

The AND gate 101 outputs "1" when both the selector 96 and the gate 91 output "1". AND gates 102, 103, and 104 perform the same operation. Outputs of the AND circuits 101 to 104 are input to the OR circuit 105. The output of the OR circuit 105
This becomes the on-time signal II .

The gate 108 outputs a print pulse I (single shot) on condition that there is no current data and there is next data. The gate 109 outputs the print pulse I (continuous) on condition that the current data is present and the next data is present . The outputs of the gates 108 and 109 are input to an OR gate 110,
The output of the OR gate 110 becomes the on-time signal I.

FIG . 7 is a diagram showing the signal timing of the print pulse output unit of the present invention. In the uppermost row in the figure, X indicates dot non-printing data, and O indicates dot printing data. The numbers above the circles indicate the serial numbers of the data with dot printing. The switching clock is delayed by a time determined by the delay circuit 40 and the register 42 from the print trigger.

Shift register type print data buffer
The flip-flop that constitutes (1 ) captures input data at the leading edge ( rising) of the switching clock . JK flip
-The flop 107 is connected to the trailing edge
At the rising edge, the timer select signal is captured. free
The top flop 90 is also the trailing edge of the status latch clock.
( Rising), the state of the print data buffer 89 is changed.
take in.

When a dot row as shown in the uppermost row is input to the print data buffer 89, the signals S1, S2, S3 output from the print data buffer 89 (previous data, current data, next data ) Change as shown. When the NAND of the signal S2 and the switching clock is taken, the result is the state latch CK. When the state latch CK is generated, the timer select signal is taken into the flip-flop 107. The output of the flip-flop 107 becomes the select signal. The condition 1 becomes H level (logic 1) on condition that there is no next data, there is current data, and there is no previous data. Condition 2 becomes H level on condition that there is next data, present data, and no previous data.
Condition 3 becomes H level on condition that there is next data, present data, and previous data. Condition 4 becomes H level on condition that there is no next data, there is current data, and there is previous data.

The firstOn-time signal I(With number 1
AddedOn-time signal I) Is the second print trigger
(The leftmost print trigger is the first)
You. The first on-time signal II isSwitching
clockIs equal to the value of register 61
Generated when The secondOn-time signal I
(The number 2 has been addedOn-time signalI) is the fourth
Generated based on a print trigger. The secondOn tie
SignalII is the fourthSwitching clockWhen relative to
It is generated when the interval becomes equal to the value of the register 62.

The thirdOn-time signal I(With the number 3
AddedOn-time signal I) Is the fifth print trigger
Generated based on The thirdOn-time signal II
Is the fifthSwitching clockRegis based on time
It is generated when it becomes equal to the value of the data 63. The fourth
On-time signal I(Number 4 addedOn-time signal
I) Is generated based on the sixth print trigger. No.
FourthOn-time signal IIIs the sixthSwitching clock
KHas become equal to the value of register 64
Sometimes generated.

FifthOn-time signal I(With the number 5
AddedOn-time signal I) Is the eighth print trigger
Generated based on FifthOn-time signal II
Is the eighthSwitching clockRegis based on time
It is generated when it becomes equal to the value of the data 61.

[0048]

As is apparent from the above description, according to the present invention, the two timing mechanisms can each count up to twice the printing cycle, so that the timings differ by more than the printing cycle due to differences in printing conditions. It is possible to respond. Therefore, for example, in the case of a 24-pin 4-row staggered head, 24
The number of timekeeping mechanisms can be reduced to four (2 × 2) and the circuit scale can be reduced, so that the cost can be reduced by reducing the size of the gate array by several ranks.

[Brief description of the drawings]

FIG. 1 is a diagram (part 1) illustrating the principle of the present invention.

FIG. 2 is a diagram (part 2) illustrating the principle of the present invention.

FIG. 3 is a diagram illustrating a configuration example of a pulse generator according to the present invention;
You.

FIG. 4 shows a configuration example (continued) of the pulse generator of the present invention .
FIG.

FIG. 5 shows the signal timing of the pulse generator of the present invention .
FIG.

FIG. 6 shows a configuration example of a print pulse output unit of each pin according to the present invention .
FIG.

FIG. 7 shows the signal timing of the print pulse output unit of the present invention .
FIG.

FIG. 8 is a diagram showing control blocks of the entire printer.

FIG. 9 is a diagram showing various signals in the piezoelectric printer.
You.

FIG. 10 is a diagram illustrating a piezoelectric head.

FIG. 11 FIG. 11 is a diagram illustrating a conventional circuit configuration example.

[Explanation of symbols]

61-64 registers 66A-69A comparators 66B-69B comparators 71-74 registers 76A-79A comparators 76B-79B comparators 81A-84A JK flip-flops 81B-84B JK flip-flops 85A and 85B JK flip-flops 86A And 86B counter 91 to 94 gate 96 to 99 selector 101 to 104 AND gate 106 gate 107 flip flop 108 to 110 gate 111 print pulse output unit per pin

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) B41J 2/51 B41J 2/30 G06F 3/12

Claims (1)

(57) [Claims] A print head having a plurality of print pins; a print head controller for outputting an on-time signal I and an on-time signal II when the print pins are driven; A print head control method in a printer device including a print head driver that raises a print pin drive signal and lowers the print pin drive signal when the on-time signal II is output. Has a pulse generation section and a print pulse output section for each print pin, and the pulse generation section has a pulse generator which is delayed by a predetermined time from the print trigger clock.
Switching clock generating means for generating a switching clock, and a mark for the on-time signal I whose trailing edge coincides with the switching clock.
A first print pulse generating means for generating a character pulse, and a time count is started upon receiving an activation signal, and the time count value is
A side that is cleared when it reaches a predetermined value
When the start signal is received, the time counting starts, and the time counting value is
B side that is cleared when it reaches a predetermined value
And a timer select signal each time the switching clock is generated.
Switching the logical value in synchronization with the number-th switching clock odd
Generates a start signal for the clocking mechanism on the A side,
Start signal to the clocking mechanism on B side in synchronization with the switching clock
Switch circuit for generating a signal, and four A-side output terminals and four B-side output terminals.
Then, the value of the timer on the A side becomes Ni (i is 1,..., 4).
The on-time signal to the i-th output terminal on the A side
The print pulse for II is output, and the value of the timer on the B side is N
i (i is 1,..., 4) when the i-th
Output print pulse for on-time signal II to output terminal
That the second; and a print pulse generating means, the printing pulse output unit of each printing pin, the bit string that has arrived in synchronization with the leading edge of the switching clock
Shift register type print data that captures one bit at a time
The buffer and the print data buffer are in a predetermined state.
Provided that the first print pulse generating means
Print pulse generated as on-time signal I
A first print pulse output means, and a shift register type print data buffer output from a predetermined stage.
Switching clock under conditions where the power is showing a predetermined logical value
To generate a status latch clock when
A state latch clock generating means, and a state latch clock when the state latch clock is generated.
Select signal storage means for taking in the timer select signal at the trailing edge of the lock; and a state latch clock when a state latch clock is generated.
Capture the status of the print data buffer at the trailing edge of the lock
A print information storage means for storing in, when the select signal output from the select signal storage means of one of the logical values A side of the second printing pulse generator
The print pulse group output from the four output terminals is selected. When the select signal has the other logical value, the second
Output from the four output terminals on the B side of the print pulse generator
Group selecting means for selecting a printing pulse group to be selected, and one printing based on printing conditions determined by the state of the printing information storage means from among the printing pulse groups selected by the group selecting means. Pulse, and outputs the selected print pulse as the on-time signal II .
2. A print head control system, comprising: