JP2791174B2 - Electronic component solder connection life evaluation method - Google Patents
Electronic component solder connection life evaluation methodInfo
- Publication number
- JP2791174B2 JP2791174B2 JP2093153A JP9315390A JP2791174B2 JP 2791174 B2 JP2791174 B2 JP 2791174B2 JP 2093153 A JP2093153 A JP 2093153A JP 9315390 A JP9315390 A JP 9315390A JP 2791174 B2 JP2791174 B2 JP 2791174B2
- Authority
- JP
- Japan
- Prior art keywords
- life
- strain
- crack
- evaluation
- crack growth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Investigating Or Analyzing Materials Using Thermal Means (AREA)
- Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子回路機器のはんだ接続部の熱疲労寿命評
価方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for evaluating the thermal fatigue life of a solder joint of an electronic circuit device.
従来、電子回路部品のはんだ接続寿命評価方法につい
てはソリッドステイツテクノロジー、７月号（1970年）
第48頁から第54頁（Solid State Techinology July（19
70）PP48−54）において論じられている。Conventionally, regarding the method of evaluating the solder connection life of electronic circuit components, Solid States Technology, July issue (1970)
Pages 48 to 54 (Solid State Technology July (19
70) discussed in PP48-54).
また、金属系材料の疲労寿命は多くの研究と疲労破壊
事故の経験とに基づいて、様々な評価法，寿命式が第１
表に示すごとく提案され、一部は実際に用いられてい
る。In addition, the fatigue life of metallic materials is based on a number of studies and experiences of fatigue failure accidents, and various evaluation methods and life formulas are the first.
It is proposed as shown in the table, and some are actually used.
特に、No1のManson−Coffin則は多くの金属の低サイ
クル疲労寿命評価に用いる事が可能であることが知られ
ている。そこで、さらにこの式を疲労の繰返し周波数ｆ
とき裂の長さａに対して修正したNo.9の繰返し修正速度
式が実際の寿命を評価できると言われている。In particular, it is known that the Manson-Coffin rule of No. 1 can be used for low cycle fatigue life evaluation of many metals. Therefore, this equation is further converted to the fatigue repetition frequency f
It is said that the No. 9 repetition correction speed equation corrected for the crack length a can sometimes evaluate the actual life.
上記従来技術は以下の点について配慮されておらず、
正確にして簡単な寿命評価ができないという問題があっ
た。The above prior art does not consider the following points,
There was a problem that accurate and simple life evaluation could not be performed.
（１）電子回路の接合部ははんだの融点（Pb−Sn系で18
3−320℃）に比べ、部品の発熱や使用環境温度変化によ
って融点直下まで温度上昇するという厳しい温度環境に
ある。この温度変化を伴う電子回路の接合部の熱疲労寿
命評価ができていない。(1) The junction of the electronic circuit has a melting point of solder (Pb-Sn based 18
(3-320 ° C), the temperature rises to just below the melting point due to the heat generated by the components and changes in the operating environment temperature. The thermal fatigue life evaluation of the junction of the electronic circuit accompanying the temperature change has not been performed.
（２）接続形状によってき裂の進展速度が変化するが、
これを配慮した寿命評価がなされておらず残り断面積が
把握できないため、耐重量や電流容量について設計がで
きない。(2) The crack growth rate changes depending on the connection shape.
Since the life evaluation taking this into consideration is not performed and the remaining cross-sectional area cannot be grasped, it is not possible to design the withstand weight and the current capacity.
このように、接続部の寿命評価が正確にできないた
め、多くの製品不良が発生する可能性がある。As described above, since the life evaluation of the connection portion cannot be accurately performed, many product defects may occur.
本発明の目的は上記の問題点を解決し、短時間で寿命
評価を行うことにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to evaluate the life in a short time.
本発明の他の目的は、き裂進展経過を含めた寿命を評
価することにある。Another object of the present invention is to evaluate the life including the progress of crack growth.
本発明の他の目的は、簡便な作業工程で精度良く寿命
を評価することにある。Another object of the present invention is to evaluate the life accurately with a simple operation process.
上記目的を達成するために、本発明は、以下の特徴を
有する。In order to achieve the above object, the present invention has the following features.
通常疲労寿命と支配するひずみ振幅は第１表のNo1,No
9の寿命式における塑性ひずみ振幅Δεｐが採用されて
いる。Δεｐは第１図に示すごとく、材料に機械的な繰
返し応力−ひずみを加えた際の履歴曲線におけるひずみ
範囲が用いられている。しかし、電子回路のはんだ接続
部のごとく、はんだ材の融点に近い温度変化が起こる
と、部品と基板の熱膨張差によってはんだに生じる熱応
力−ひずみが、はんだ自身の強度の温度依存性によって
さらに変化する。そのため、第１図に示す従来の実験方
法ではこのΔεｐを求めることが非常に難しい。Normally, the fatigue life and the dominant strain amplitude are No. 1 and No.
The plastic strain amplitude Δεp in the life equation of 9 is adopted. As shown in FIG. 1, Δεp uses a strain range in a hysteresis curve when mechanically repeated stress-strain is applied to a material. However, when a temperature change close to the melting point of the solder material occurs, as in the case of the solder connection part of an electronic circuit, the thermal stress-strain generated in the solder due to the difference in thermal expansion between the component and the board is further increased by the temperature dependence of the strength of the solder itself. Change. Therefore, it is very difficult to obtain Δεp in the conventional experimental method shown in FIG.
そこで、上記の問題的を解決して目的を達成するため
に、第２図に示すはんだ材料の強度の温度依存性を考慮
して、第３図に示すような温度サイクルで時々刻々変化
するはんだの熱応力−ひずみを有限要素法３次元熱弾塑
性解析により求め、その相当応力−ひずみ履歴曲線（第
２図）からその最大の相当びすみ範囲Δεeqmaxを熱疲
労における第１図の塑性ひずみ範囲Δεｐとし、このΔ
εeqmaxとき裂進展速度式とから寿命評価基準式および
き裂進展評価基準式を求めたものである。このき裂進展
速度式は、き裂が進展したはんだ破断面を電子顕微鏡で
観察し、き裂進展量を測定し、求めたものである。ここ
で相当応力−ひずみはミーゼスの基準に従ったが、物理
的意味としてはひずみエネルギー量に関係していること
が知られており、相当ひずみ範囲は温度サイクル中には
んだ接合部に加えられたエネルギー範囲と考えることが
できる。Therefore, in order to solve the above-mentioned problems and achieve the object, in consideration of the temperature dependence of the strength of the solder material shown in FIG. 2, the solder that changes every moment in a temperature cycle as shown in FIG. Is obtained by the finite element method three-dimensional thermo-elasto-plastic analysis, and the maximum equivalent strain range Δεeqmax is obtained from the corresponding stress-strain history curve (FIG. 2). Δεp and this Δ
The criterion equation for life evaluation and the criterion equation for crack growth evaluation were obtained from εeqmax and the crack growth rate equation. This crack growth rate equation is obtained by observing the cracked solder fracture surface with an electron microscope and measuring the amount of crack growth. Here, the equivalent stress-strain was in accordance with Mises criteria, but it is known that the physical meaning is related to the amount of strain energy, and the equivalent strain range was applied to the solder joint during the temperature cycle. It can be considered as an energy range.
上記の他の目的を達成するために、電子回路部品の寸
法，はんだ材料特性，温度サイクル条件とから簡便に最
大の相当ひずみ振幅Δεeqmaxを求める近似式を求め、
これを電子計算機用にプログラム化したものである。In order to achieve the other objects, an approximate expression for easily obtaining the maximum equivalent strain amplitude Δεeqmax from the dimensions of electronic circuit components, solder material characteristics, and temperature cycle conditions is obtained,
This is programmed for a computer.
き裂進展速度式を求めることにより、最終破断に到る
以前に最終破断寿命を予測することができる。By determining the crack growth rate equation, the final fracture life can be predicted before the final fracture.
寿命評価基準式およびき裂進展評価式を求めることに
より、残り断面積を確保するために許容されるき裂進展
量に対するサイクル数がわかるため耐用年数を明らかに
でき、逆に、必要なサイクル数に対してもき裂進展量が
わかるため残り断面積を明らかにでき製品としての寿命
期間内で不良を起こすことがないように予め設計でき
る。By calculating the life evaluation standard formula and the crack growth evaluation formula, the number of cycles for the amount of crack growth allowed to secure the remaining cross-sectional area can be determined, and the useful life can be clarified. In addition, since the amount of crack propagation is known, the remaining cross-sectional area can be clarified, and the design can be made in advance so as not to cause a defect within the life of the product.
相当ひずみ振幅を求める近似式を用いることにより、
簡便な操作と短い時間で相当ひずみ振幅を求めることが
でき、この値を用いて予め求めておいた寿命評価基準式
およびき裂進展量評価基準式から寿命およびき裂進展量
を計算できるため、高精度な設計が簡単にできる。By using the approximate expression to find the equivalent strain amplitude,
Since the equivalent strain amplitude can be obtained in a simple operation and in a short time, the life and the crack growth amount can be calculated from the life evaluation standard expression and the crack growth amount evaluation standard expression obtained in advance using this value. High-precision design can be easily performed.
以下、本発明の一実施例を図を用いて説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
第５図は半導体集積回路１を回路基板２にはんだ３を
用いて接続したものである。半導体集計回路１と回路基
板２とでは熱膨張率が異なるため、温度変化や回路のパ
ワーオン・オフが繰返えされると接続部はんだ３にひず
みが繰返し発生し第４図（ａ）の拡大図に示したように
き裂４が発生する。このき裂４は１回のサイクル毎に間
隔da/dNずつ伸びていき、その都度き裂を発生した破断
面にはギザギザの模様が残る。この間隔da/dNをき裂進
展速度という。第６図は、温度サイクル試験に1000サイ
クルかけた第５図に示す電子回路品の半導体集積回路１
を機械的に取外し、き裂４の破断面を走査電子顕微鏡に
より観察した結果である。き裂長さa1，a2におけるSEM
観察像（ｂ），（ｃ）からそれぞれのき裂進展速度da/d
Nを求めるとそれぞれ1，2となった。これらの点の
他にもいくつか測定した結果をまとめると第６図（ａ）
に示すようにき裂進展速度da/dNはき裂長さａに対して
直線関係 da/dN＝Aa＋Ｂ で近似できることがわかった。上式を積分することによ
り第４図（ｂ）に示すように、寿命評価式 と寿命評価線図を得る。これより、寿命基準となるき裂
長さafから寿命としてのサイクル数Nfが求まる。試験サ
イクル数1000において求めた完全断線に対する予測寿命
は3000サイクルであり、同一条件で試験を継続し電気的
に断線を確認したところ3300サイクルであり、良く一致
した。第７図に示すのは、第５図に示したはんだ接続構
造を有限要素法三次元熱弾塑性解析により、第３図に示
す室温〜＋150℃〜−50℃〜室温という温度サイクル試
験に相当する温度変化を与えたときのはんだ接続部の第
４図（ａ）に示したき裂部４に発生する相当応力−相当
歪の履歴曲線である。これからひずみ振幅は履歴中の最
大の歪振幅Δεeqmaxとした。この相当歪み振幅と予め
破壊試験から求めたき裂進展速度da/dNとき裂長さａと
の関係を整理すると、 da/dN＝Ｃ（Aa＋Ｂ）・（Δεeqmax）n と表わされる。これを積分することにより、寿命Nfは次
式に示す寿命評価基準式から求められる。FIG. 5 shows a semiconductor integrated circuit 1 connected to a circuit board 2 using solder 3. Since the coefficient of thermal expansion is different between the semiconductor integrated circuit 1 and the circuit board 2, if the temperature changes or the power on / off of the circuit is repeated, the solder 3 at the connecting portion is repeatedly distorted, and FIG. 4 (a) is enlarged. Cracks 4 occur as shown in the figure. The crack 4 grows at intervals of da / dN in each cycle, and each time a crack occurs, a jagged pattern remains on the fractured surface. This interval da / dN is called the crack growth rate. FIG. 6 shows a semiconductor integrated circuit 1 of the electronic circuit product shown in FIG.
Is a result of observing the fracture surface of the crack 4 with a scanning electron microscope. SEM at crack lengths a 1 and a 2
From the observed images (b) and (c), the respective crack growth rates da / d
When N was calculated, they were 1 and 2 , respectively. Fig. 6 (a) summarizes some measured results in addition to these points.
As shown in the figure, it was found that the crack growth rate da / dN can be approximated to the crack length a by a linear relationship da / dN = Aa + B. By integrating the above equation, as shown in FIG. And a life evaluation diagram. From this, the cycle number Nf as the life is obtained from the crack length af which is the life standard. The expected life for a complete disconnection obtained at a test cycle number of 1000 was 3000 cycles, and when the test was continued under the same conditions and the disconnection was confirmed electrically, it was 3300 cycles, which was a good match. FIG. 7 shows a temperature cycle test from room temperature to + 150 ° C. to -50 ° C. to room temperature shown in FIG. 3 by the finite element method three-dimensional thermo-elasto-plastic analysis of the solder connection structure shown in FIG. 4A is a hysteresis curve of equivalent stress-equivalent strain generated in the crack portion 4 shown in FIG. 4A of the solder connection portion when a temperature change is given. From this, the strain amplitude was set to the maximum strain amplitude Δεeqmax in the history. When the relationship between the equivalent strain amplitude, the crack growth rate da / dN, and the crack length a previously obtained from the fracture test is arranged, da / dN = C (Aa + B) · (Δεeqmax) n is obtained. By integrating this, the life Nf is obtained from the life evaluation criterion equation shown below.
また、上式から逆算することによりＮサイクル後のき裂
長さａは第８図に示す関係から次式に示すき裂進展評価
式から求められる。 Further, the crack length a after N cycles can be obtained from the relationship shown in FIG.
これらの式から、過去に製品不良を起こしたものにつ
いて計算したところ、実際の寿命3500サイクルに対して
計算による寿命は3200サイクルである、非常に良い一致
を見た。 From these formulas, calculations were performed for products that had product failures in the past. As a result, a very good agreement was found that the calculated life was 3200 cycles compared to the actual life of 3500 cycles.
第10図に示すのは、第７図に示した相当歪振幅Δεeq
maxを第９図に示した半導体集積回路１の寸法ｄと接続
高さhjと半導体集積回路１の熱膨張係数と回路基板２の
熱膨張係数の差Δαと温度サイクルにおける温度差ΔＴ
から次式により計算されるせん断ひずみγ、 との関係を求めたものである。ここでＥは形状に依存す
る補正パラメータである。ここに示すように、相当歪振
幅Δεeqmaxは、せん断ひずみγを用いて次式で表わさ
れる。FIG. 10 shows the equivalent strain amplitude Δεeq shown in FIG.
9 is the dimension d of the semiconductor integrated circuit 1, the connection height hj, the difference between the thermal expansion coefficient of the semiconductor integrated circuit 1 and the thermal expansion coefficient of the circuit board 2, and the temperature difference ΔT in the temperature cycle.
Shear strain γ calculated from And the relationship between them. Here, E is a correction parameter depending on the shape. As shown here, the equivalent strain amplitude Δεeqmax is expressed by the following equation using the shear strain γ.
Δεeqmax＝Ａ′γ2＋Ｂ′γ 上式を用いることにより、簡単な計算から相当歪振幅
Δεeqmaxを求めることができ、さらには寿命Nfおよび
き裂進展量ａをそれぞれ前述した寿命評価基準式および
き裂進展評価式から算出できる。さらに、部品と基板に
温度差がある場合、せん断ひずみγはより一般的に次式
で表わされることは言うまでもない。Δεeqmax = A′γ 2 + B′γ By using the above equation, the equivalent strain amplitude Δεeqmax can be obtained from a simple calculation, and further, the life Nf and the crack propagation amount a can be obtained by the above-mentioned life evaluation criteria and It can be calculated from the crack growth evaluation formula. Further, when there is a temperature difference between the component and the substrate, it goes without saying that the shear strain γ is more generally expressed by the following equation.
ここで、α1，T1は部品すなわち半導体集積回路の熱
膨張係数と温度、α2，T2は基板の熱膨張係数と温度で
ある。以上、電子回路のはんだ接続部に関して、簡単に
して正確求める実施例について説明した。 Here, α 1 and T 1 are the coefficients of thermal expansion and temperature of the components, ie, the semiconductor integrated circuit, and α 2 and T 2 are the coefficients of thermal expansion and temperature of the substrate. In the above, the embodiment which simply and accurately obtains the solder connection portion of the electronic circuit has been described.
次に、この寿命評価法を入出力を含むプログラムと
し、より簡単に評価する実施例について説明する。Next, a description will be given of an embodiment in which the life evaluation method is a program including input and output, and the evaluation is made easier.
このプログラムの全体構成を示すフローチャートを第
11図に示す。また、このフローチャートにおける電子部
品（ここではフリップチップあるいはCCBチップ）のは
んだ接続形状を入力する画面，寿命評価結果とき裂進展
状況を出力する画面、を第12図（ａ），（ｂ）に示す。A flow chart showing the overall configuration of this program is shown in FIG.
Figure 11 shows. FIGS. 12 (a) and 12 (b) show a screen for inputting a solder connection shape of an electronic component (in this case, a flip chip or a CCB chip) and a screen for outputting a life evaluation result and a crack propagation state in this flowchart. .
このプログラムによる評価は以下の手順に従って行
う。Evaluation by this program is performed according to the following procedure.
まず（１）対象とする電子部品の選択を行う。次に
（２）第12図（ａ）に示すように対象とする電子部品お
よびその接続形状の寸法を、予め構成した形状画面に入
力する。形状は３角法で表示しているので、見やすく寸
法入力の間違いが少ない。（３）使用する各種材料定数
を入力する。（４）前記の実施例で示した各評価式（寿
命式やき裂進展式等）を登録し、指数，定数を入力す
る。（５）使用条件を考慮して、温度，繰返し周波数，
温度差等の解析条件を入力する。（６）寿命計算を実施
し、結果を表示する。（７）最後に、第12図（ｂ）に示
すように、き裂進展状況を表示し、寿命を推定する。こ
こでは、接続部のどこまでき裂が進み、残りの寿命がい
くらあるかも容易に推定できる，等の特徴を持ってい
る。これらの各工程は、どこからでも、繰返すことがで
きる。対象とする電子部品はフリップチップ以外フラッ
トパッケージICやチップ部品等も対象としていることは
言うまでもない。First, (1) a target electronic component is selected. Next, as shown in FIG. 12 (a), the dimensions of the target electronic components and their connection shapes are input to a previously configured shape screen. Since the shape is displayed by the triangular method, it is easy to see and there are few errors in dimension input. (3) Input various material constants to be used. (4) Each evaluation formula (life formula, crack propagation formula, etc.) shown in the above embodiment is registered, and an index and a constant are input. (5) Considering operating conditions, temperature, repetition frequency,
Input analysis conditions such as temperature difference. (6) Perform the life calculation and display the result. (7) Finally, as shown in FIG. 12 (b), the crack growth state is displayed and the life is estimated. Here, the connection portion has a feature that the crack progresses and the remaining life can be easily estimated. Each of these steps can be repeated from anywhere. It goes without saying that the target electronic components include flat package ICs and chip components in addition to flip chips.
これらのプログラム計算をパーソナルコンピュータ，
大形コンピュータ等で簡単に行うことができ、寿命の設
計が可能である。具体的に、寿命試験サンプルに適用し
た所、寿命の温度サイクル数，き裂進展量がともに±10
％の誤差範囲で一致し、かつ計算および寿命評価の実行
時間をわずか５〜10分で行うことができた。これは前記
実施例におけるような最大相当ひずみ振幅を有限要素法
で求める計算時間が、スーパーコンピュータS810でもCP
U時間で２〜５時間必要であり、これに比べて大幅な時
間短縮とコスト低減を達成できた。A personal computer,
It can be easily performed by a large-sized computer or the like, and the life can be designed. Specifically, when applied to a life test sample, the number of life cycle temperature cycles and the amount of crack growth were both ± 10
% And the execution time of the calculation and the life evaluation could be performed in only 5 to 10 minutes. This is because the calculation time for obtaining the maximum equivalent strain amplitude by the finite element method as in the above embodiment is also
It takes 2 to 5 hours in U time, and a considerable time reduction and cost reduction can be achieved.
（Δεp;塑性ひずみ振幅），（C,n,m,定数）， （Npp;pp波形寿命），（Ncc;cc波形寿命）， （Ncp;cp波形寿命），（Npc;pc波形寿命）， （Dp;短時間高温引っ張り破断延性）， （Dc;クリープ破断延性），（Δσ；応力範囲）， （ΔK;応力拡大係数範囲），（a;き裂長さ）， （ΔεTR；全ひずみ範囲），（Δεp,Δεe;塑性および
弾性ひずみ範囲），（f;繰り返し周波数）， （Q;活性化エネルギー），（k;ボルツマン定数）， （T;温度），（ΔKeff;有効応力拡大係数範囲）， （Kop;き裂開口時のＫ），（ΔJ;J積分範囲）， （ΔΦ；き裂開口変位範囲） 〔発明の効果〕 本発明によれば、従来難しかった電子部品のはんだ接
続寿命評価を、パソーナルコンピュータや大形コンピュ
ータで短時間で実行できるようになった点は大きな進歩
である。 (Δεp; plastic strain amplitude), (C, n, m, constant), (N pp ; pp waveform life), (N cc ; cc waveform life), (N cp ; cp waveform life), (N pc ; pc (Waveform life), (Dp; short-time high-temperature tensile rupture ductility), (Dc; creep rupture ductility), (Δσ; stress range), (ΔK; stress intensity factor range), (a; crack length), (Δε TR ; Total strain range), (Δεp, Δεe; plastic and elastic strain range), (f; repetition frequency), (Q; activation energy), (k; Boltzmann constant), (T; temperature), (ΔKeff; effective (Stress intensity factor range), (Kop; K at crack opening), (ΔJ; J integration range), (ΔΦ; crack opening displacement range) [Effects of the Invention] According to the present invention, electronic components conventionally difficult This is a major advance in that the evaluation of solder connection life can be performed in a short time on a personal computer or a large computer.
また、温度分布やあらゆる環境条件に対しても有限要
素法三次元熱塑性解析によって解析できるので、従来で
きなかった寿命の評価や高精度化を行うことができ、今
後増々厳しくなる電子回路の高信頼化に大きく寄与でき
る効果を有する。In addition, since the temperature distribution and all environmental conditions can be analyzed by the finite element method three-dimensional thermoplastic analysis, it is possible to evaluate the life and improve the accuracy, which could not be done conventionally, and to improve the reliability of electronic circuits, which will become increasingly severe in the future. This has the effect of greatly contributing to the development of
第１図は従来の疲労における応力−ひずみ履歴曲線図、
第２図は本発明における熱疲労の相当応力−相当ひずみ
線図、第３図は温度サイクルのプロファイルの１例を示
した図、第４図は、本発明の一実施例の寿命評価基準線
図を説明する図、第５図ははんだ接続した電子回路部品
の側面図、第６図はき裂進展速度式を表わす線図、第７
図は、有限要素法三次元熱弾塑性解析によるはんだ接続
部内の点における相当応力と相当ひずみの履歴曲線、第
８図は相当ひずみを考慮した寿命評価基準線図、第９図
ははんだ接続した電子回路部品の主要寸法を示す側面
図、第10図は相当ひずみを求めるためのひずみ評価基準
線図、第11図は、本発明に係る評価方法のプログラムに
おけるフローチャート、第12図は、本発明に係る評価方
法を実施するときの入・出力画面を示す図である。 １…半導体集積回路、２…回路基板、３…はんだ、ａ…
き裂長さ、Ｎ…温度サイクル数、da/dN…き裂進展速
度、Δεeqmax…最大相当ひずみ振幅。FIG. 1 is a stress-strain history curve diagram in conventional fatigue,
FIG. 2 is a diagram showing an equivalent stress-equivalent strain diagram of thermal fatigue in the present invention, FIG. 3 is a diagram showing an example of a temperature cycle profile, and FIG. 4 is a life evaluation reference line of one embodiment of the present invention. FIG. 5 is a side view of an electronic circuit component connected by soldering, FIG. 6 is a diagram showing a crack growth rate equation, FIG.
The figure is a history curve of equivalent stress and equivalent strain at a point in the solder joint by the finite element method three-dimensional thermo-elasto-plastic analysis, FIG. 8 is a life evaluation reference diagram considering equivalent strain, and FIG. FIG. 10 is a side view showing main dimensions of electronic circuit components, FIG. 10 is a strain evaluation reference diagram for obtaining equivalent strain, FIG. 11 is a flowchart of a program of an evaluation method according to the present invention, and FIG. FIG. 7 is a view showing an input / output screen when the evaluation method according to the embodiment is performed. DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 2 ... Circuit board, 3 ... Solder, a ...
Crack length, N: number of temperature cycles, da / dN: crack growth rate, Δεeqmax: maximum equivalent strain amplitude.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 金井 紀洋士 茨城県勝田市大字高場2520番地 株式会 社日立製作所佐和工場内 (72)発明者 高橋 勉 千葉県習志野市東習志野７丁目１番１号 株式会社日立製作所習志野工場内 (72)発明者 竹中 隆次 神奈川県秦野市堀山下１番地 株式会社 日立製作所神奈川工場内 (72)発明者 今田 晴彦 東京都小平市上水本町５丁目22番１号 日立マイクロコンピュータエンジニアリ ング株式会社内 (58)調査した分野(Int.Cl.6，ＤＢ名) H05K 3/34──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Norihiro Kanai 2520 Takada, Katsuta-shi, Ibaraki Inside Sawa Plant, Hitachi, Ltd. (72) Inventor Tsutomu Takahashi 7-1-1 Higashi Narashino, Narashino-shi, Chiba Hitachi, Ltd. Narashino Plant (72) Inventor Ryuji Takenaka 1, Horiyamashita, Hadano-shi, Kanagawa Prefecture Hitachi, Ltd. Kanagawa Plant, (72) Inventor Haruhiko Imada 5-2-12-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Microcomputer Engineering Co., Ltd. (58) Field surveyed (Int. Cl. 6 , DB name) H05K 3/34
Claims (3)
ん断ひずみを求める第１工程と、予め有限要素法三次元
熱弾塑性解析から求めた相当ひずみ振幅と上記せん断ひ
ずみとの関係から相当ひずみ振幅を求める第２工程と、
予め温度サイクル試験後の破面解析によって求めたき裂
進展速度と上記相当ひずみ振幅との関係を示すき裂進展
速度式を求める第３工程と、上記相当ひずみ振幅とき裂
の長さと寿命サイクル数との関係を示す寿命評価基準式
より寿命を求める第４工程とからなることを特徴とする
電子部品はんだ接続寿命評価法。1. A first step for determining a shear strain generated in a solder connection portion of an electric circuit device, and a corresponding strain based on a relationship between an equivalent strain amplitude previously determined from a finite element method three-dimensional thermo-elasto-plastic analysis and the above-mentioned shear strain. A second step of determining the amplitude;
A third step of obtaining a crack growth rate equation indicating the relationship between the crack growth rate previously determined by fracture surface analysis after the temperature cycle test and the equivalent strain amplitude, and the equivalent strain amplitude and crack length and life cycle number; And a fourth step of obtaining a life from a life evaluation criterion formula indicating the relationship of the above.
義からなる事を特徴とする電子部品はんだ接続寿命評価
法。 2. A method for evaluating the solder connection life of an electronic component, wherein the shear strain according to claim 1 has the following definition.
て、部品と基板の熱膨張差と温度差と部品の寸法と接続
高さとを入力する第１工程と、第２項記載のせん断ひず
み式から求めるせん断ひずみ計算とひずみ評価線図から
求める相当ひずみ計算と寿命評価基準式から求める寿命
計算とき裂進展速度式から求めるき裂長さの結果、を順
次実行する第２工程と、各計算結果を表示出力する第３
工程とからなることを特徴とする電子部品はんだ接続寿
命評価法。3. The method according to claim 1, wherein a first step of inputting a difference between a thermal expansion of the component and the substrate, a temperature difference, a dimension of the component, and a connection height is provided. The second step of sequentially executing the shear strain calculation obtained from the equation, the equivalent strain calculation obtained from the strain evaluation diagram, the life calculation obtained from the life evaluation reference formula, and the result of the crack length obtained from the crack growth rate equation, and each calculation result Display output 3
A method for evaluating the solder life of soldering electronic components, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2093153A JP2791174B2 (en) | 1989-04-10 | 1990-04-10 | Electronic component solder connection life evaluation method |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-87927 | 1989-04-10 | ||
| JP8792789 | 1989-04-10 | ||
| JP2093153A JP2791174B2 (en) | 1989-04-10 | 1990-04-10 | Electronic component solder connection life evaluation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03128431A JPH03128431A (en) | 1991-05-31 |
| JP2791174B2 true JP2791174B2 (en) | 1998-08-27 |
Family
ID=26429156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2093153A Expired - Fee Related JP2791174B2 (en) | 1989-04-10 | 1990-04-10 | Electronic component solder connection life evaluation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2791174B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7725866B2 (en) | 2005-03-18 | 2010-05-25 | Fujitsu Limited | Electronic package evaluation apparatus, electronic package optimizing apparatus, and computer-readable recording medium in which electronic package evaluation program is recorded |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7722246B1 (en) * | 2005-04-20 | 2010-05-25 | Carty William M | Method for determining the thermal expansion coefficient of ceramic bodies and glazes |
| JP2009216386A (en) * | 2006-06-29 | 2009-09-24 | Mitsubishi Electric Corp | Test specification design method for random vibration test |
| JP4855947B2 (en) * | 2007-01-11 | 2012-01-18 | 富士通株式会社 | Crack growth evaluation device, crack growth evaluation method, and crack growth evaluation program |
| JP4686522B2 (en) * | 2007-09-28 | 2011-05-25 | 株式会社日立製作所 | Fracture surface analysis method and apparatus |
| JP4938695B2 (en) * | 2008-01-23 | 2012-05-23 | 富士通株式会社 | Crack growth evaluation apparatus and crack growth evaluation method |
| JP5187243B2 (en) * | 2009-03-13 | 2013-04-24 | 株式会社Ｉｈｉ | Method for deriving and evaluating nonlinear fracture mechanics parameters |
| JP5025676B2 (en) * | 2009-03-25 | 2012-09-12 | 株式会社東芝 | Monitoring device and monitoring method |
| JP5175911B2 (en) | 2010-09-16 | 2013-04-03 | 株式会社東芝 | Solder joint life prediction method, solder joint life prediction device |
| JP6247903B2 (en) * | 2013-11-07 | 2017-12-13 | 株式会社日立製作所 | Life prediction structure |
| JP6854480B2 (en) * | 2017-03-31 | 2021-04-07 | 国立大学法人大阪大学 | Test methods, test samples, test systems, evaluation methods, evaluation systems, and evaluation programs |
| CN112730211B (en) * | 2020-12-24 | 2022-08-02 | 浙江华电器材检测研究所有限公司 | Method and device for estimating fatigue life of industrial pure aluminum wire |
| CN116859206B (en) * | 2023-09-04 | 2024-01-30 | 湖南大学 | Method for predicting minimum residual length of bonding interface in power module |
-
1990
- 1990-04-10 JP JP2093153A patent/JP2791174B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7725866B2 (en) | 2005-03-18 | 2010-05-25 | Fujitsu Limited | Electronic package evaluation apparatus, electronic package optimizing apparatus, and computer-readable recording medium in which electronic package evaluation program is recorded |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03128431A (en) | 1991-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2791174B2 (en) | Electronic component solder connection life evaluation method | |
| Durand et al. | Solder fatigue failures in a new designed power module under power cycling | |
| US5291419A (en) | Method for diagnosing the life of a solder connection | |
| Basaran et al. | Measuring intrinsic elastic modulus of Pb/Sn solder alloys | |
| Kovacevic-Badstuebner et al. | Modelling for the lifetime prediction of power semiconductor modules | |
| Yongle et al. | Physics of failure of die-attach joints in IGBTs under accelerated aging: Evolution of micro-defects in lead-free solder alloys | |
| JP2013058657A (en) | Electronic device life estimation method and electronic device design method using the same | |
| US4947341A (en) | Method of predicting fatigue lifetimes of metallic structures | |
| Pecht et al. | In-situ measurements of surface mount IC package deformations during reflow soldering | |
| EP0392471B1 (en) | Method for evaluating life of connection | |
| Stolkarts et al. | Constitutive and damage model for solders | |
| Dornic et al. | Analysis of the degradation mechanisms occurring in the topside interconnections of IGBT power devices during power cycling | |
| JP2005148016A (en) | Method and device for diagnosing thermal fatigue life of solder weld part | |
| JP2004237304A (en) | Method for estimating life time of solder joining | |
| Deplanque et al. | Lifetime prediction of SnPb and SnAgCu solder joints of chips on copper substrate based on crack propagation FE-analysis | |
| Sommer et al. | Solder fatigue at high-power IGBT modules | |
| JP2004045343A (en) | Life diagnostic method and device of solder joint part | |
| Durand et al. | Study of fatigue failure in Al-chip-metallization during power cycling | |
| Hanss et al. | Failure identification in LED packages by transient thermal analysis and calibrated FE models | |
| JP2004085397A (en) | Life estimation method for solder junction part | |
| JP2002076071A (en) | Reliability evaluation method and reliability evaluation equipment of component mounting part | |
| Shi et al. | Determination of fracture toughness of underfill/chip interface with digital image speckle correlation technique | |
| JP2003083871A (en) | Reliability testing method of joint part of electronic part | |
| JP4168090B2 (en) | Fatigue evaluation method for solder joints | |
| Jacques et al. | Experimental characterization of thermo-mechanical properties of lead-based solders for power electronics packaging reliability applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080612 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080612 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090612 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |