JP2790157B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of forming a self-aligned refractory metal silicide.

[0002]

2. Description of the Related Art Titanium silicide is taken as an example of a self-aligned refractory metal silicide which has been conventionally used, and its manufacturing method will be described below. As shown in FIG. 3, an element isolation region 201, a gate oxide film 301, a gate electrode 4 made of polysilicon or the like are formed on one main surface of a semiconductor substrate 101.
01, a sidewall 501 is formed. Further, as shown in FIG. 4, an impurity element is introduced by an ion implantation method or the like to form a diffusion layer 601. After forming the diffusion layer 601, titanium 701 is deposited by a sputtering method or the like as shown in FIG. As the thickness of titanium, about 300 to 1000 Å is used. Next, titanium 701 is reacted with silicon by performing a first heat treatment in a nitrogen or ammonia atmosphere to form titanium silicide. The condition of the first heat treatment is a temperature of 60
The temperature is 0 to 700 ° C. and the time is about 30 to 60 seconds, but the optimum value varies depending on the conditions such as the deposited film thickness of titanium and the temperature.

[0003] The difference between the reaction between titanium and silicon and the reaction between titanium and silicon oxide will be described below, and how titanium silicide can be formed on the diffusion layer 601 and the gate electrode 401 will be described in detail. FIG. 6 shows a state of a reaction on silicon during the first heat treatment, that is, a reaction on the diffusion layer 601 or the gate electrode 401. By the first heat treatment in a nitrogen or ammonia atmosphere, the reaction between the titanium and silicon proceeds at the interface between titanium and silicon, and titanium silicide 702 is formed. On the other hand, on the surface of titanium, the reaction with nitrogen or ammonia proceeds, and titanium nitride 703 is formed. The thickness of the unreacted titanium 701 becomes thinner with the elapse of the first heat treatment time, and eventually the titanium silicide 702 and the titanium nitride 703 come into contact with each other, and the unreacted titanium 701 disappears and the reaction does not proceed any more.

FIG. 7 shows the state of the reaction on silicon oxide during the heat treatment, that is, the element isolation region 201 and the sidewall 501.
This shows the above reaction. Similarly to the reaction on silicon, titanium nitride 703 is formed from the titanium surface.
However, at the interface between silicon oxide and titanium, the reaction hardly proceeds, and oxygen and titanium in the silicon oxide slightly react to form an extremely thin titanium oxide 704. Therefore, after heat treatment is performed until the unreacted titanium 701 disappears, the thin titanium oxide 70 serving as an insulator is formed on the silicon oxide.
4 and titanium nitride 703 are formed.

[0005] Since the titanium nitride 703 as a conductor is formed on silicon and silicon oxide only by performing the above heat treatment, insulation between the gate electrode 401 and the diffusion layer 601 in FIG. 5 is not obtained.

However, it is possible to remove only the titanium nitride 703 by exposing it to a mixed solution of hydrogen peroxide, ammonia and water, so that the gate electrode 401 and the diffusion layer 601 are insulated. At this point, the resistivity of the titanium silicide is about 110 μΩcm.

After removing titanium nitride 703, 8
A second heat treatment at about 00 ° C. is applied for about 30 seconds. This is performed to lower the resistance of titanium silicide. By the second heat treatment, the resistivity of titanium silicide becomes about 15 μΩcm. In the first heat treatment described above, the temperature was from 600 to 700 ° C.
If the first heat treatment is performed at a temperature higher than that temperature, for example, at 800 ° C., titanium silicide having a resistivity of about 15 μΩcm can be obtained. However, as shown in FIG. And reacts with titanium on silicon oxide. As a result, since titanium silicide is formed on silicon oxide, there is a danger that the diffusion layers to be separated or the diffusion layer and a gate electrode or the like may be electrically connected to each other by titanium silicide. Therefore, the first heat treatment temperature cannot be increased.

Using the above method, titanium silicide 702 is formed on gate electrode 401 and diffusion layer 601 in a self-aligned manner as shown in FIG.

[0009]

When the refractory metal silicide is formed in a self-aligned manner by the above method, the following drawbacks occur. According to the prior art, impurities are introduced on the diffusion layer and the gate electrode before the deposition of titanium. For example, when titanium is deposited on silicon containing arsenic and subjected to the first heat treatment, silicide is not formed if arsenic having a concentration of 2 × 10 20 / cm 3 or more is contained in silicon. Even when the concentration is lower than that, the formation speed of silicide is slower than the case where arsenic is not included or the case where boron is used instead of arsenic. The effect is more remarkable as the line width is smaller. Titanium silicide can be formed by raising the first heat treatment temperature. However, since silicon diffuses in titanium and titanium silicide is formed also in the element isolation region as described in the section of the related art, the first heat treatment is performed. Raising the temperature is not possible from the standpoint of forming an integrated circuit.

Further, the above-mentioned effect becomes more remarkable as the wiring line width becomes narrower. If titanium silicide is formed without introducing impurities into the diffusion layer region and then the diffusion layer is formed by introducing impurities by ion implantation, the impurity concentration in silicon when forming titanium silicide can be reduced to a low value. The above problem cannot occur because it can be suppressed. However, since titanium is knocked on during ion implantation, the concentration of titanium in the diffusion layer increases, and the leakage current increases, so that the diffusion layer cannot be formed after the formation of titanium silicide.

As described above, the first problem is that titanium silicide is not formed or hardly formed on silicon having a high impurity concentration, and the effect becomes more remarkable as the line width becomes smaller.

FIG. 9 shows a cross-sectional shape of titanium silicide when titanium nitride is removed after the first heat treatment. The titanium silicide 702 has surface irregularities of about several hundred angstroms, and the film thickness is not uniform and varies.
In the second heat treatment or the heat treatment in the subsequent integrated circuit manufacturing process, unevenness and unevenness of the film thickness are emphasized, and titanium silicide is partially cut off. In particular, when the line width is narrow, the wiring formed of titanium silicide is disconnected, and the wiring having low resistance may have high resistance.

As described above, the second problem is that the unevenness of the titanium silicide and the non-uniformity of the film thickness are emphasized by the heat treatment, and the resistance of the wiring or the like to be formed of titanium silicide having a low resistance is increased.

When a circuit such as a CMOS is formed on a silicon substrate, the diffusion layer is formed by selectively introducing an impurity element into both the N-type and the P-type using a mask such as a photoresist. After that, titanium is deposited and subjected to a first heat treatment. However, the formation speed of titanium silicide is generally lower on silicon containing N-type impurities than on those containing P-type impurities.
The thickness of the titanium silicide on the p-type diffusion layer and the p-type diffusion layer is smaller in the former than in the latter. For this reason, when titanium silicide having a layer resistance required for the design of an integrated circuit is formed in the N-type diffusion layer, the thickness of the titanium silicide on the P-type diffusion layer increases.

Taking into account that the resistance of the titanium silicide layer after the second heat treatment is determined by the thickness of titanium silicide since the resistivity is substantially the same, the layer of titanium silicide on the P-type diffusion layer is considered. Since the resistance is smaller than that on the N-type diffusion layer, the design criteria are satisfied.

However, it is not preferable from the viewpoint of securing transistor performance. The reason is described below. As shown in FIG. 1, when titanium silicide is formed on the diffusion layer, the interface between titanium silicide 702 and diffusion layer 601 is located below gate insulating film 501. Since titanium silicide thicker than the N-type diffusion layer is formed on the P-type diffusion layer, the P-type diffusion layer has to be deeper than the N-type diffusion layer. Then, the deep channel has a remarkable short-channel effect at the same channel length as compared with the shallow diffusion layer, so that it becomes more difficult to design the P-channel transistor as the channel becomes shorter.

As described above, the P-type diffusion layer is forced to be deeper than the N-type diffusion layer due to the difference in the titanium silicide film thickness on the N-type diffusion layer and the P-type diffusion layer. The third problem is that the short-channel effect of the transistor is more remarkable than that of the N-channel transistor, and the design of the P-channel transistor becomes difficult.

[0018]

According to the present invention, after forming a diffusion layer region and a gate electrode, the substrate surface is made amorphous by ion implantation, and a heat treatment step is performed after a high melting point metal is deposited on the entire surface of the substrate. Is separated into two stages, the first heat treatment condition is set to 600 to 700 ° C. in a nitriding atmosphere, the second heat treatment temperature is set to 700 to 900 ° C., and after the two heat treatment steps, the unreacted high A method for manufacturing a semiconductor integrated circuit device is provided, which includes a step of removing a nitride of a high melting point metal or a high melting point metal.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment will be described. A method for amorphization by ion implantation using the structure shown in FIG. 4 will be described. Element isolation region 2 on one main surface of semiconductor substrate
01, a gate oxide film 301, a gate electrode 401, a sidewall 501, and a diffusion layer 601 are formed. After that, the surfaces of the gate electrode 401 and the diffusion layer 601 are made amorphous by an ion implantation method. Next, titanium is deposited by a sputtering method or the like, and a first heat treatment including two steps is performed. In the first stage of the two stages, the temperature is 650 ° C. and the time is 30 seconds, and the second stage is 800 ° C. and 30 seconds. Next, the titanium nitride is removed and a second heat treatment is performed at 850 ° C. for 10 seconds to form titanium silicide on the diffusion layer 601 and the gate electrode 401 in a self-aligned manner as shown in FIG. FIG. 11 shows the relationship between the line width and the layer resistance of titanium silicide on the diffusion layer obtained by performing the two-step heat treatment after performing the amorphization according to the present invention. The case where the second step was not performed and the case where neither the amorphousization nor the second stage heat treatment was performed are shown.

All three samples were prepared under the same conditions except for the amorphization step. As is clear from FIG. 11, the two samples subjected to amorphization have a lower layer resistance at all line widths than those not subjected to amorphization. Also, it can be seen that the line width dependence of the layer resistance is smaller in the former case. In the latter, when the line width becomes about 0.5 μm, the layer resistance becomes about 50 Ω / □, and titanium silicide is not formed, or titanium silicide is formed in some parts, and titanium silicide is not formed in some parts. It is the layer resistance of itself. In the case of line widths of 1 μm or less, those without the second stage heat treatment showed a slight increase in the layer resistance, and the degree of the increase increased as the line width became narrower. Does not show this sign, and it can be seen that titanium silicide formed by combining the two steps of amorphization and two-step heat treatment is extremely good in terms of device fabrication.

Further, when self-aligned silicide is formed on the complementary MIS integrated circuit device, the diffusion of silicon into Ti during the silicide reaction in the p + region is larger than that in the n + region. This causes a problem that silicide on the p @ + region is formed even on silicon oxide as shown in FIG. According to the experiments by the present inventors, when arsenic or phosphorus is used for amorphization, a large difference in the ease of diffusion of silicon between the p + region and the n + region is not recognized, and p It was confirmed that the protrusion of silicide on the + region can be prevented without reducing the layer resistance of the silicide on the n + region. By limiting the type of implanted ions to arsenic or phosphorus at the time of amorphization, it is possible to apply the invention to a complementary MIS integrated circuit.

Next, a second embodiment will be described. FIG.
As shown by 0, the present invention is applicable even when the gate electrode has a two-layer structure composed of polycrystalline silicon 401 and tungsten silicide 402. That is, similarly to the first embodiment, the diffusion layer is made amorphous by an ion implantation method, and then titanium is deposited and subjected to a first heat treatment consisting of two steps to remove titanium nitride and to carry out a second heat treatment. Apply. Then, titanium silicide is formed on the diffusion layer as shown in FIG. Since titanium silicide 402 is present on the gate electrode, titanium silicide is not formed, but the present invention is also effective when titanium silicide is formed only on the diffusion layer.

[0023]

According to the present invention, the irregularities of the refractory metal silicide formed by applying the present invention are reduced, and the variation in the film thickness is also reduced. Further, even when silicon contains a high concentration of N-type impurities, refractory metal silicide can be formed. In addition, even in the case where the line width is small, the resistivity is almost the same as that in the case where the line width is large, and the increase in the resistivity unlike the case where the line is not amorphous is not observed.

Further, whether the impurity contained in the diffusion layer is P-type or N-type, there is no difference in film thickness between the two, which is preferable in terms of CMOS circuit design.

[Brief description of the drawings]

FIG. 1 shows that titanium silicide is formed on a diffusion layer and a gate electrode in a self-aligned manner.

FIG. 2 illustrates a method of applying the present invention when a gate electrode has a two-layer structure of tungsten silicide and polycrystalline silicon.

FIG. 3 shows a state before a diffusion layer is formed.

FIG. 4 shows the situation before titanium deposition.

FIG. 5 shows the deposition of titanium.

FIG. 6 shows how titanium on silicon reacts by heat treatment.

FIG. 7 shows how titanium on silicon oxide reacts by heat treatment.

FIG. 8 shows a situation where titanium silicide has also grown on silicon oxide.

FIG. 9 shows unevenness and unevenness of film thickness of titanium silicide.

FIG. 10 illustrates a method of applying the present invention when a gate electrode has a two-layer structure of tungsten silicide and polycrystalline silicon.

FIG. 11 shows the relationship between the line width and the layer resistance of titanium silicide on a diffusion layer for a sample subjected to amorphization according to the present invention and for a sample not subjected to amorphization.

[Explanation of symbols]

 Reference Signs List 101 semiconductor substrate 201 element isolation region 301 gate insulating film 401 gate electrode 402 polycrystalline silicon 403 tungsten silicide 501 sidewall 601 diffusion layer 701 titanium 702 titanium silicide 703 titanium nitride 704 titanium oxide

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21/44-21/445 H01L 29/40-29/45 H01L 29 / 78 H01L 21/336

Claims (4)

(57) [Claims] After forming a diffusion layer region and a gate electrode, the substrate surface is made amorphous by ion implantation, and a heat treatment step after depositing a high melting point metal over the entire surface of the substrate is divided into two steps. In the nitriding atmosphere, the heat treatment conditions are set at 600 to 700 ° C., the second heat treatment temperature is set at 700 to 900 ° C., and after the two heat treatment steps, unreacted high melting point metal or nitride of high melting point metal is removed. A method for manufacturing a semiconductor integrated circuit device, comprising a step of removing. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein titanium is used as the refractory metal. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the ion species used for ion implantation at the time of amorphization is arsenic. 4. A method for manufacturing a semiconductor integrated circuit device, wherein an ion species used for ion implantation for amorphization is phosphorus.