JP2788885B2 - Lead frame for semiconductor device and semiconductor device - Google Patents
Lead frame for semiconductor device and semiconductor deviceInfo
- Publication number
- JP2788885B2 JP2788885B2 JP7333064A JP33306495A JP2788885B2 JP 2788885 B2 JP2788885 B2 JP 2788885B2 JP 7333064 A JP7333064 A JP 7333064A JP 33306495 A JP33306495 A JP 33306495A JP 2788885 B2 JP2788885 B2 JP 2788885B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- double
- convex portion
- adhesive layer
- height
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置用リード
フレーム（以下単に、リードフレーム、と称す）および
半導体装置に係わり、特にＬｅａｄ Ｏｎ Ｃｈｉｐ
（ＬＯＣ）型の半導体装置用リードフレームのインナー
リード構造およびＬＯＣ型の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device (hereinafter, simply referred to as a lead frame) and a semiconductor device, and more particularly to a Lead On Chip.
The present invention relates to an inner lead structure of a (LOC) type semiconductor device lead frame and a LOC type semiconductor device.
【０００２】[0002]
【従来の技術】図５はＬＯＣ型半導体装置を示す平面図
である。ＩＣチップ（半導体チップ）１１の主面上にリ
ードフレームの多数のインナーリード１が延在して両面
接着テープ４によりＩＣチップ１１の主面に固着され、
すなわちダイボンディングされ、その後、インナーリー
ド１の先端部分とＩＣチップ１１の電極パッド部１３と
が金属ワイヤー１２でワイヤーボンディングされる。2. Description of the Related Art FIG. 5 is a plan view showing a LOC type semiconductor device. A large number of inner leads 1 of the lead frame extend on the main surface of the IC chip (semiconductor chip) 11 and are fixed to the main surface of the IC chip 11 by the double-sided adhesive tape 4.
That is, die bonding is performed, and thereafter, the tip portion of the inner lead 1 and the electrode pad portion 13 of the IC chip 11 are wire-bonded with the metal wire 12.
【０００３】図６（Ａ）は、導体パターンであるインナ
ーリード１と両面が接着層であるポリイミド等の両面接
着テープ４の一方の接着層とを接着してある状態を拡大
して示した断面図である。FIG. 6A is an enlarged cross-sectional view showing a state in which an inner lead 1 as a conductor pattern is bonded to one adhesive layer of a double-sided adhesive tape 4 made of polyimide or the like on both surfaces thereof. FIG.
【０００４】図６（Ｂ）は、図６（Ａ）の状態のインナ
ーリード１とＩＣチップ１１とを位置あわせし、ヒータ
ーツールによりＩＣチップ１１を両面接着テープ４の他
方の接着層に加熱接着することによりインナーリードと
ＩＣチップとを固着接続（ダイボンディング）し、イン
ナーリード１を押えた状態でＩＣチップ１１の電極パッ
ド部１３とインナーリード１をＡｕ等のボンディングワ
イヤー１２で配線接続（ワイヤーボンディング）した状
態を示す断面図である。FIG. 6B shows a state in which the inner lead 1 and the IC chip 11 in the state shown in FIG. 6A are aligned, and the IC chip 11 is heated and bonded to the other adhesive layer of the double-sided adhesive tape 4 by a heater tool. Then, the inner lead and the IC chip are fixedly connected to each other (die bonding), and the electrode pad 13 of the IC chip 11 and the inner lead 1 are connected by a bonding wire 12 such as Au while the inner lead 1 is held down (wire bonding). It is sectional drawing which shows the state which carried out (bonding).
【０００５】[0005]
【発明が解決しようとする課題】しかしながら上記従来
技術では、ワイヤーボンディング前のインナーリード成
形時あるいは上記ダイボンディングのテーピング時にね
じれ浮き等が発生したまま固定されるため、図６のＡ−
Ａ部の断面図の図７に示すように、長方断面形状のイン
ナーリード１の上面がランダムに傾斜し、水平かつ安定
したワイヤーボンディング面が確保できない。However, in the above-mentioned prior art, the inner leads are fixed with the occurrence of twisting and floating during the inner lead forming before wire bonding or the taping of the die bonding.
As shown in the cross-sectional view of part A in FIG. 7, the upper surface of the inner lead 1 having a rectangular cross-sectional shape is randomly inclined, and a horizontal and stable wire bonding surface cannot be secured.
【０００６】したがってワイヤーボンディング時にボン
ディング強度の低下が発生するという問題を有する。Therefore, there is a problem that the bonding strength is reduced during wire bonding.
【０００７】したがって本発明は、ＬＯＣ構造パッケー
ジ用リードフレームのインナーリードと両面接着テープ
との接着性および安定性を向上させることにより、ボン
ディングワイヤーとリードフレームとの接着強度を向上
させたリードフレームおよび半導体装置を提供するもの
である。Accordingly, the present invention provides a lead frame having an improved bonding strength between a bonding wire and a lead frame by improving the adhesion and stability between an inner lead of a lead frame for a LOC structure package and a double-sided adhesive tape. A semiconductor device is provided.
【０００８】[0008]
【課題を解決するための手段】本発明の特徴は、ベース
フィルムの両面に接着層を設けた両面接着テープにより
ＩＣチップと接着するインナーリードを具備する半導体
装置用リードフレームにおいて、前記インナーリードの
前記両面接着テープとの接触面には幅方向の中央を凹部
とし両側端にそれぞれ鋭角先端を有する凸部を備え、前
記凸部はたがいに平行に長手方向を延在し、前記凹部の
底と前記凸部の先端間の寸法である前記凸部の高さはた
がいに等しく、かつそれぞれの前記凸部の高さは前記接
触面が接着する前記接着層の厚さと均等であるリードフ
レームにある。この均等の高さは、前記接着層の厚さを
Ｔμｍとし、前記凸部の高さをＨμｍとした場合、Ｈは
（Ｔ＋４）μｍ以下で（Ｔ−４）μｍ以上であることが
好ましい。また、前記両面接着テープはポリイミドから
なるベースフィルムの両面にフェーノル系樹脂からなる
接着層を塗布形成して構成されていることができる。SUMMARY OF THE INVENTION A feature of the present invention is a semiconductor device lead frame having an inner lead bonded to an IC chip by a double-sided adhesive tape having an adhesive layer provided on both sides of a base film. The contact surface with the double-sided adhesive tape is provided with a convex portion having a central portion in the width direction as a concave portion and an acute-angled tip on each side edge, and the convex portions extend in a longitudinal direction in parallel with each other, and a bottom of the concave portion. The height of the protrusions, which is the dimension between the tips of the protrusions, is equal to each other, and the height of each of the protrusions is equal to the thickness of the adhesive layer to which the contact surface is bonded. . As for this uniform height, when the thickness of the adhesive layer is T μm and the height of the projection is H μm, it is preferable that H is not more than (T + 4) μm and not less than (T-4) μm. Further, the double-sided adhesive tape can be formed by applying and forming an adhesive layer made of a phenolic resin on both sides of a base film made of polyimide.
【０００９】本発明の他の特徴は、ＩＣチップ上を延在
するインナーリードにベースフィルムの両面に接着層を
設けた両面接着テープにより該ＩＣチップが固着された
ＬＯＣ型の半導体装置において、前記インナーリードの
前記両面接着テープとの接触面には幅方向の中央を凹部
とし両側端にそれぞれ鋭角先端を有する凸部を備え、前
記凸部はたがいに平行に長手方向を延在し、前記凹部の
底と前記凸部の先端間の寸法である前記凸部の高さはた
がいに等しく、かつそれぞれの前記凸部の高さは前記接
触面が接着する前記接着層の厚さと均等であり、それぞ
れの前記凸部の鋭角先端が前記接着層を通して前記ベー
スフィルムにに食い込んで達している半導体装置にあ
る。ここで、前記両面接着テープはポリイミドからなる
ベースフィルムの両面にフェーノル系樹脂からなる接着
層を塗布形成して構成されていることができる。Another feature of the present invention is a LOC type semiconductor device in which the IC chip is fixed by a double-sided adhesive tape in which adhesive layers are provided on both sides of a base film on inner leads extending on the IC chip. The contact surface of the inner lead with the double-sided adhesive tape is provided with a convex portion having a central portion in the width direction as a concave portion and an acute-angled tip on each side end, and the convex portions extend in a longitudinal direction parallel to each other, The height of the convex portion, which is the dimension between the bottom of the convex portion and the tip of the convex portion, is equal to each other, and the height of each of the convex portions is equal to the thickness of the adhesive layer to which the contact surface adheres, In the semiconductor device, the acute-angled tip of each of the protrusions penetrates into the base film through the adhesive layer. Here, the double-sided adhesive tape can be formed by applying and forming an adhesive layer made of a phenolic resin on both sides of a base film made of polyimide.
【００１０】このような本発明によれば、インナーリー
ド裏面に互いに平行また高さの等しい鋭角先端を有する
凸部をそれぞれの両側端に設けることにより、ワイヤー
ボンディング時に、インナーリードが受ける力を面から
点あるいは線で受けることで、インナーリード裏面への
抵抗が減少し、インナーリード裏面の凸部がベースフィ
ルムに食い込む。これにより、ワイヤーボンディング時
に、インナーリードの横すべりや上下へのバラツキを減
少し、インナーリードと両面接着テープとお接着強度が
高くなり、インナーリードのワイヤーボンディング上面
が水平になり、これらによりインナーリードへのワイヤ
ーボンディング性が向上する。[0010] According to the present invention, by providing on both sides of the inner lead back surface a convex portion having an acute-angled tip which is parallel to each other and has the same height, the force received by the inner lead during wire bonding is provided. , The resistance to the back surface of the inner lead is reduced, and the protrusion on the back surface of the inner lead bites into the base film. As a result, during wire bonding, side slip and variations in the vertical direction of the inner lead are reduced, the bonding strength between the inner lead and the double-sided adhesive tape is increased, and the upper surface of the inner lead wire bonding is horizontal, which allows the inner lead to adhere to the inner lead. The wire bonding property is improved.
【００１１】[0011]
【発明の実施の形態】以下図面を用いて本発明を説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.
【００１２】図５に示すようなＬＯＣ型の半導体装置を
製造する本発明の実施の形態において、まず図１の断面
図に示すような両面接着テープ４を用いる。In the embodiment of the present invention for manufacturing a LOC type semiconductor device as shown in FIG. 5, first, a double-sided adhesive tape 4 as shown in a sectional view of FIG. 1 is used.
【００１３】この両面接着テーフ４は、ポリイミドから
なるベースフィルム３の両面にフェノール系樹脂からな
る接着層２を塗布形成して構成されている。また接着層
２の膜厚Ｔは２０μｍになるように設計されている。The double-sided adhesive tape 4 is formed by applying an adhesive layer 2 made of a phenolic resin on both sides of a base film 3 made of polyimide. The thickness T of the adhesive layer 2 is designed to be 20 μm.
【００１４】Ｃｕ合金もしくは４２合金からなるこの実
施の形態におけるリードフレームのインナーリードの図
６のＡ−Ａ部に相当する箇所の断面は、図２や図３に示
すように、インナーリード１の裏面すなわち両面接着テ
ープとの接着面は、２箇所（両側端に沿ってたがいに平
行にそれぞれ１箇所）のたがいに高さが等しい鋭角先端
を有する凸部１Ａが設けられている。この凸部１Ａの高
さＨは中心を２０μｍとし２４μｍ以下で１６μｍ以上
の寸法範囲になるように、すなわち接着層２の膜厚Ｔの
±４μｍになるように加工されている。このような寸法
範囲は接着層の各部分における膜厚のバラツキを考慮
し、本発明の効果に実質的に影響を及ぼさない範囲を検
討してから定めたものである。As shown in FIGS. 2 and 3, the cross section of the inner lead of the lead frame according to the present embodiment, which is made of a Cu alloy or a 42 alloy, corresponds to the section AA of FIG. The back surface, that is, the adhesive surface with the double-sided adhesive tape, is provided with a convex portion 1A having an acute-angled tip having the same height at two places (one place parallel to each other along both side edges). . The height H of the convex portion 1A is processed so that the center is 20 μm and the dimension ranges from 24 μm or less to 16 μm or more, that is, ± 4 μm of the thickness T of the adhesive layer 2. Such a dimensional range is determined after considering a range that does not substantially affect the effects of the present invention in consideration of variations in the film thickness in each part of the adhesive layer.
【００１５】次に本発明の実施の形態の図２において、
前記のように構成されたＬＯＣ構造パッケージ用リード
フレームは、従来技術と同様にダイボンディング及びワ
イヤーボンディングされるが、ワイヤーボンディング前
には図２（Ａ）に示すようにランダムに傾いていたイン
ナーリード１が、ワイヤーボンディングする時にボンデ
ィング位置周辺を押さえつけること、また、ワイヤーを
接着するツールによりインナーリードが加圧されること
により、インナーリード裏面のそれぞれの凸部１Ａが両
面接着テープの接着層２を通してベースフィルム３に到
達しそこに食い込むようにすることにより、図２（Ｂ）
に示すように、インナーリード１のワイヤーボンディン
グ上面が水平となりインナーリードが安定し、信頼性が
高いワイヤーボンディングが可能となる。Next, in FIG. 2 of the embodiment of the present invention,
The lead frame for a LOC structure package configured as described above is die-bonded and wire-bonded in the same manner as in the related art, but before the wire bonding, the inner leads are randomly inclined as shown in FIG. 1 presses the periphery of the bonding position during wire bonding, and the inner lead is pressed by a tool for bonding the wire, so that each convex portion 1A on the back surface of the inner lead passes through the adhesive layer 2 of the double-sided adhesive tape. By reaching the base film 3 and digging into it, FIG.
As shown in (1), the upper surface of the wire bonding of the inner lead 1 becomes horizontal, the inner lead is stabilized, and highly reliable wire bonding becomes possible.
【００１６】図４は本発明に関係のある技術におけるイ
ンナーリードを示す斜視図である。先に説明した実施の
形態におけるインナーリード裏面の凸部１Ａは両面接着
テープのベースフィルムに線接触するもであったが、図
４のインナーリードは点で接触する様な形状となってい
るから、その加工は多少複雑となるが、ベースフィルム
への食い込みがより容易になり、インナーリードをより
安定させることができる。FIG. 4 is a perspective view showing an inner lead in a technique related to the present invention . Although the convex portion 1A on the back surface of the inner lead in the embodiment described above was in line contact with the base film of the double-sided adhesive tape, the inner lead in FIG. Although the processing is somewhat complicated, the bite into the base film becomes easier and the inner leads can be more stabilized.
【００１７】[0017]
【発明の効果】以上説明したように本発明によれば、イ
ンナーリード裏面に凸部１Ａを設けることでワイヤーボ
ンディング時にインナーリードが両面接着テープに固定
されるから、ワイヤーボンディング時にインナーリード
が安定する。これによりワイヤー接着強度の低下や剥れ
等の不具合を低減することができる。As described above, according to the present invention, since the inner lead is fixed to the double-sided adhesive tape at the time of wire bonding by providing the convex portion 1A on the back surface of the inner lead, the inner lead is stabilized at the time of wire bonding. . As a result, problems such as a decrease in wire bonding strength and peeling can be reduced.
【図１】本発明の実施の形態に用いる両面接着テープを
示す断面図である。FIG. 1 is a sectional view showing a double-sided adhesive tape used in an embodiment of the present invention.
【図２】本発明の実施の形態を示す図であり、（Ａ）は
ワイヤーボンディング工程前の断面図、（Ｂ）はワイヤ
ーボンディング工程中及びそれ以降の断面図である。2A and 2B are diagrams showing an embodiment of the present invention, wherein FIG. 2A is a cross-sectional view before a wire bonding step, and FIG. 2B is a cross-sectional view during and after the wire bonding step.
【図３】本発明の実施の形態のインナーリードを示す斜
視図である。FIG. 3 is a perspective view showing an inner lead according to the embodiment of the present invention.
【図４】本発明に関係のある技術のインナーリードを示
す斜視図である。FIG. 4 is a perspective view showing an inner lead of a technique related to the present invention.
【図５】ＬＯＣ型の半導体装置を示す平面図である。FIG. 5 is a plan view showing a LOC type semiconductor device.
【図６】図５の一部を拡大して示した図であり、（Ａ）
はインナーリードに両面接着テープを接着した状態の断
面図、（Ｂ）は（Ａ）の状態のインナーリードと半導体
チップとを接着し、ワイヤーボンディングを行った状態
の断面図である。6 is an enlarged view of a part of FIG. 5, and FIG.
3A is a cross-sectional view of a state in which a double-sided adhesive tape is bonded to an inner lead, and FIG. 4B is a cross-sectional view of a state in which the inner lead and the semiconductor chip in the state of FIG.
【図７】従来技術を示す断面図である。FIG. 7 is a sectional view showing a conventional technique.
１ インナーリード １Ａ 凸部 ２ 接着層 ３ ベースフィルム ４ 両面接着テープ １１ ＩＣチップ １２ ボンディングワイヤー １３ 電極パッド部 DESCRIPTION OF SYMBOLS 1 Inner lead 1A Convex part 2 Adhesive layer 3 Base film 4 Double-sided adhesive tape 11 IC chip 12 Bonding wire 13 Electrode pad part
Claims (4)
両面接着テープによりＩＣチップと接着するインナーリ
ードを具備する半導体装置用リードフレームにおいて、
前記インナーリードの前記両面接着テープとの接触面に
は幅方向の中央を凹部とし両側端にそれぞれ鋭角先端を
有する凸部を備え、前記凸部はたがいに平行に長手方向
を延在し、前記凹部の底と前記凸部の先端間の寸法であ
る前記凸部の高さはたがいに等しく、かつそれぞれの前
記凸部の高さは前記接触面が接着する前記接着層の厚さ
と均等であることを特徴とする半導体装置用リードフレ
ーム。1. A lead frame for a semiconductor device comprising an inner lead bonded to an IC chip by a double-sided adhesive tape provided with an adhesive layer on both sides of a base film,
On the contact surface of the inner lead with the double-sided adhesive tape, the center in the width direction is a concave portion, and the sharp ends are respectively formed on both side edges.
Comprising a convex portion , the convex portion extends in the longitudinal direction parallel to each other, the height of the convex portion, which is a dimension between the bottom of the concave portion and the tip of the convex portion, is equal to each other, and each A lead frame for a semiconductor device, wherein a height of the projection is equal to a thickness of the adhesive layer to which the contact surface adheres.
部の高さをＨμｍとした場合、Ｈは（Ｔ＋４）μｍ以下
で（Ｔ−４）μｍ以上であることを特徴とする請求項１
記載の半導体装置用リードフレーム。 Wherein the thickness of the adhesive layer and Timyuemu, if the height of the convex portion was Hμm, H is characterized by at (T + 4) μm or less (T-4) μm or more claims Item 1
13. The lead frame for a semiconductor device according to claim 1.
にベースフィルムの両面に接着層を設けた両面接着テー
プにより該ＩＣチップが固着されたＬＯＣ型の半導体装
置において、前記インナーリードの前記両面接着テープ
との接触面には幅方向の中央を凹部とし両側端にそれぞ
れ鋭角先端を有する凸部を備え、前記凸部はたがいに平
行に長手方向を延在し、前記凹部の底と前記凸部の先端
間の寸法である前記凸部の高さはたがいに等しく、かつ
それぞれの前記凸部の高さは前記接触面が接着する前記
接着層の厚さと均等であり、それぞれの前記凸部の鋭角
先端が前記接着層を通して前記ベースフィルムにに食い
込んで達していることを特徴とする半導体装置。3. A LOC-type semiconductor device in which an IC chip is fixed by a double-sided adhesive tape in which an adhesive layer is provided on both sides of a base film on inner leads extending on the IC chip, wherein the double-sided bonding of the inner leads is performed. The contact surface with the tape is provided with a convex portion having a central portion in the width direction as a concave portion and an acute-angled tip at each end on both sides, the convex portions extending in the longitudinal direction parallel to each other, and the bottom of the concave portion and the convex portion. The height of the projections, which is the dimension between the tips of the projections, is equal to each other, and the height of each projection is equal to the thickness of the adhesive layer to which the contact surface adheres, and the height of each projection is A semiconductor device, wherein an acute-angled tip penetrates into the base film through the adhesive layer.
るベースフィルムの両面にフェーノル系樹脂からなる接
着層を塗布形成して構成されていることを特徴とする請
求項１記載の半導体装置用リードフレームまたは請求項
３記載の半導体装置。 4. The double-sided adhesive tape is made of polyimide.
Phenolic resin on both sides of the base film
Characterized in that it is formed by coating and forming an adhesion layer.
A lead frame for a semiconductor device according to claim 1 or claim.
4. The semiconductor device according to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7333064A JP2788885B2 (en) | 1995-12-21 | 1995-12-21 | Lead frame for semiconductor device and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7333064A JP2788885B2 (en) | 1995-12-21 | 1995-12-21 | Lead frame for semiconductor device and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09172132A JPH09172132A (en) | 1997-06-30 |
| JP2788885B2 true JP2788885B2 (en) | 1998-08-20 |
Family
ID=18261869
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7333064A Expired - Fee Related JP2788885B2 (en) | 1995-12-21 | 1995-12-21 | Lead frame for semiconductor device and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2788885B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5088638B2 (en) * | 2009-12-03 | 2012-12-05 | Ｔｄｋ株式会社 | Coil component, transformer, and method of manufacturing coil component |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1238119A (en) * | 1985-04-18 | 1988-06-14 | Douglas W. Phelps, Jr. | Packaged semiconductor chip |
| JP2587533B2 (en) * | 1990-11-02 | 1997-03-05 | 九州日本電気株式会社 | Lead frame |
-
1995
- 1995-12-21 JP JP7333064A patent/JP2788885B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09172132A (en) | 1997-06-30 |
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