JP2778520B2 - Multicast method and switching switch - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch for performing packet exchange such as a communication network and a computer connection network.

[0002]

2. Description of the Related Art Conventionally, as a multicast system for transmitting a packet to a plurality of destinations in a multistage network as shown in FIG.
There is a method of writing a multicast destination in a specific field of a packet.

In general, as shown in FIG. 2, a packet 14 is composed of a header 15 at the head and actual data (body 16) following the header. The header 14 includes elements necessary for passing through the exchange switch, such as the destination and whether or not the packet is a multicast packet.

[0004] Therefore, in the case of a packet to be multicast, a flag indicating that the packet is multicast is set in a specific field of the header portion, and a destination to be multicast is written.

Thus, when a packet arrives at the switch, this field is read, and if a multicast flag is set, a port to be output is determined.
It transmits to the port at the same time.

As such a system, there is a "network control system" (Japanese Patent Application No. 2-238779). The “network control method” enables multicasting of a packet to a destination having a plurality of consecutive addresses.

Here, the conventional system will be described in detail with reference to embodiments.

FIG. 3 shows a conventional exchange switch (SU:
FIG. 3 is a block diagram of a switching unit.
It comprises 21 buffers, 22 crossbar switches, and 23 controllers.

The buffer 21 stores the packet input to the SU, and writes the stored packet to the next SU or PE through the crossbar switch 22 according to the instruction of the controller 23. If the packet data stored in the buffer 21 exceeds a certain amount with respect to the capacity, the information (fullf
lag) is transmitted to the preceding SU or PE connected by the 21 buffer.

The 22 crossbar switch is an N × M crossbar switch composed of N input lines and M output lines.
Switch connections on each grid point. Normally, one input line is connected to one output line, but one input line can be connected to a plurality of output lines, which is multicast. Conversely, a plurality of input lines are not connected to one output line. That is, if an output line is already connected to an input line, the other input lines cannot be connected to the output line. By performing such exclusive control, parallel operation of a plurality of ports becomes possible.

The operation of the 23 controller will be described with reference to a control transition diagram. However, although all ports actually operate in parallel, the description is complicated, so the description will be made focusing on one port.

FIG. 8 shows a control transition of the conventional exchange switch. The respective states are as follows.

(State 0) Idle state. Wait for the packet to arrive. When the packet arrives, go to state 1.

(State 1) Checking of packet header. Check the header of the arriving packet, and go to state 2 in case of multicast. In other cases, state transition is performed by normal wormhole routing.

(State 2) The crossbar switch is connected. Connect the input lines to all output lines to be connected. If any of the output lines to be connected is already connected to an external input line and cannot be connected to this input line, wait until the output line can be connected. If everything is connected, go to state 3.

(State 3) Operation state of multicast. 1
When packets cannot be output to one or more ports, go to state 4. When all multicast packets have been transmitted, go to state 0. Also, when output to a port is not possible, the SU or PE connected to that port
It is when the l flag is transmitted.

(State 4) Standby state. When output to all ports is possible, go to state 2.

This conventional example is summarized as follows.

When the packet arrives at the switch and is stored in the buffer 21, the controller 23 reads the header of the packet from the buffer 21 and checks whether or not the packet is a multicast packet and the destination (state 1). In the case of multicast, if all output lines to be connected can be connected, the state goes to state 3; if not, the state waits until connection can be made (state 2). If output is possible to all ports, multicast is performed (state 3). If packets cannot be output to one or more ports, go to state 4,
Wait for output to all ports.

[0020]

The conventional "network control system"
However, when the Wormhole routing is used as the flow control, there is a disadvantage that a deadlock may occur.

Wormhole routing is a flow control in which a field indicating the destination of a packet is read even when the entire packet does not arrive at a switch, and the packet is transmitted when an output port is determined. This is effective in reducing delay time. Is raised.

However, it has been confirmed that the use of this flow control causes a deadlock as shown in FIG. This is from PE0 and PE10 (PE: Proc
Essor Element), which attempts to perform multicast to all PEs at the same time. in this case,
The packet from PE0 can be transmitted to SU4 and SU5 (SU: Switching Unit), while SU6,
Since transmission to SU7 is not possible, transmission from SU0 stops, and SU0 is waiting for transmission to SU6 and SU7. Conversely, the packet from the PE 10 can be transmitted to the SUs 6 and 7 but cannot be transmitted to the SUs 4 and 5, so that the transmission from the SU 2 stops, and
U2 is waiting for transmission to SU4,5. Therefore, both will cause a deadlock.

[0023] This is because, when the Wormhole routing is used, if at least one port in the switch cannot be output at the time of multicasting, even if there is a port that can be output, output cannot be performed to all ports. Underlying is underlying. When this phenomenon occurs in a plurality of switches, a deadlock occurs.

It is an object of the present invention to provide a multicast implementation that avoids deadlock even when using Wormhole routing.

[0025]

SUMMARY OF THE INVENTION A multicast system and an exchange switch according to the present invention, when performing multicast in a communication network using Wormhole routing or a multistage network of computers, send packets to one or more ports in a certain switch. When it becomes impossible to output the packet, the packet is transmitted to the port that can output the packet, and the packet data is simultaneously stored in the multicast buffer.
When a port that could not be output becomes available for output, multicast is realized by extracting data from the multicast buffer and transmitting it.

[0026]

According to the present invention, when multicast is performed in a multistage network using Wormhole routing, if a packet cannot be output to one or more ports in a switch, the packet is transmitted to a port that can output the packet. At the same time, packet data is stored in the multicast buffer. After that, the port that could not output,
When the output becomes possible, data is extracted from the multicast buffer and transmitted. With the above control, if there is even one port that cannot be output,
Even if there is a port that can be output, it is possible to eliminate the cause of a deadlock that prevents output to all ports.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The multicast method and exchange switch of the present invention will be described in detail with reference to embodiments.

FIGS. 4 and 5 are block diagrams showing the present invention.

FIG. 4 shows an N-input M-output exchange switch (S) using a memory as a multicast buffer.
U). The 34-multicast memory is connected to the buffer, and data is written directly from the 31-buffer to the 34-multicast memory without passing through the 32 crossbar switch. Therefore, the data on the 34 multicast memory is output from the exchange switch through the 32 crossbar switch. In this case, what is required besides the hardware of the conventional method is one multicast memory corresponding to the maximum packet length for each exchange switch. This method has the advantage that the amount of additional hardware is small.

FIG. 5 shows an exchange switch using a FIFO as a multicast buffer. 44 Multicast FIFO is connected to the crossbar switch,
The data in the 41 buffer is written to the 44 FIFO FIFO through the 42 crossbar switch. Therefore, the data on the 44 multicast FIFO is 4
It is output directly from the switch unit without passing through the two crossbar switches. In this case, what is required other than the hardware of the conventional method is a multicast FIFO for the maximum length of the packet for each output port for each exchange switch. This method has an advantage that buffer control is easy because of FIFO.

Next, the operation of each element (buffer, crossbar switch, controller, multicast buffer) will be described.

The operation of the buffer and the crossbar switch is the same as that of the above-mentioned conventional type for both the memory type and the FIFO type. For the operation of the controller and the buffer for multicast,
This will be described with reference to a control transition diagram.

FIGS. 9 and 10 show the transition of the controller control of the switch in each type.

FIG. 9 shows a transition of control of a switch using a memory as a multicast buffer. The respective states are as follows. However, although all ports actually operate in parallel, the explanation becomes complicated,
Here, the description will focus on one port.

(State 0) Idle state. Wait for the packet to arrive. When the packet arrives, go to state 1.

(State 1) Checking of packet header. Check the header of the arriving packet, and go to state 2 in case of multicast. Otherwise, state transition is performed by normal Wormhole routing.

(State 2) It is checked whether multicast is being performed. The controller keeps track of the current multicast operation status for each port. In other words, a multicast register is prepared in the controller as to whether or not multicast is being performed to each port, and when multicasting, which data in the multicast memory is being transmitted to each port. And hold information on it. During transmission, the value of the multicast register is
Indicates the data position (pointer) to be transmitted on the multicast memory, and indicates null when transmission is completed. That is, when all the multicast registers indicate null, it means that the multicast is not being performed. If multicasting is being performed, the process waits until output to all ports is completed.

(State 3) The crossbar switch is connected. Connect the input lines to all output lines to be connected. If any of the output lines to be connected is already connected to an external input line and cannot be connected to this input line, go to state 5;
What.

(State 4) Multicast operation state. 1
When packets cannot be output to one or more ports, go to state 5. In addition, when output to a port is not possible, the SU or PE connected to the port is full.
This is when the flag is transmitted.

(State 5) Data is stored in the multicast memory. At the same time as transmitting a packet to an output-capable port, packet data is stored in this multicast memory. For an unconnectable output line or a port that cannot be output, the data to be transmitted on the multicast memory is stored. The pointer is held in the multicast register. After reading all the multicast packets to be sent from the buffer, if a line that could not be connected or a port that could not be output becomes connectable or outputable, the information held in the multicast register Allows you to send data,
Set the value of the multicast register sequentially. If all values of the multicast register indicate null,
Go to state 0.

The following is a summary of this embodiment.

When a packet arrives at the switch, first,
It is checked whether the packet is a multicast packet (state 1). In the case of multicast, the value of the multicast register is checked, and if at least one is not null, the process waits until all of them are null (state 2).
When all the multicast register values become null, the crossbar switch is connected (state 3), and then transmission of packet data is started (state 4). In this state, if there is an output line that cannot be connected, or if there is a port that cannot be output, the packet data is stored in the multicast memory while transmitting the packet data to the output-capable port, Set the memory pointer in the multicast register. if,
When the port that cannot be connected or output becomes connectable or outputable, the value of the multicast register of the port is sequentially set while transmitting the data indicated by the pointer from the multicast memory. When all the values of the multicast register indicate null, a packet reception waiting state (state 0) is set.

FIG. 10 shows the transition of control of a switch using a FIFO as a multicast buffer.
The respective states are as follows. However, although all ports actually operate in parallel, the description is complicated, so the description will be made focusing on one port.

(State 0) Idle state. Wait for the packet to arrive. When the packet arrives, go to state 1.

(State 1) Checking of packet header. Check the header of the arriving packet, and go to state 2 in case of multicast. Otherwise, state transition is performed by normal Wormhole routing.

(State 2) It is checked whether or not the multicast is being performed. If there is no data in the multicast FIFO of the port to be output, go to state 3.
At other times, it waits until the above state is reached.

(State 3) The crossbar switch is connected. Connect the input lines to all output lines to be connected. If any of the output lines to be connected is already connected to an external input line and cannot be connected to this input line, wait until the output line becomes connectable. If everything is connected, go to state 4.

(State 4) Multicast operation state. 1
When packets cannot be output to one or more ports, go to state 5. In addition, when output to a port is not possible, the SU or PE connected to that port
It is when the flag is transmitted.

(State 5) Data is stored in the multicast FIFO. Multicast F for ports that cannot transmit simultaneously while transmitting packets to ports that can output
The packet data is stored in the IFO. If the output-disabled port becomes available for output, data is transmitted from the multicast FIFO. When all multicast packets have been transmitted, go to state 0.

The following is a summary of this embodiment.

When a packet arrives at the switch, first,
It is checked whether the packet is a multicast packet (state 1). In the case of multicast, it is confirmed whether or not there is data in the multicast FIFO of the port to be output, and if there is data, it waits until there is no more data (state 2). When there is no more data in the multicast FIFO, a crossbar switch is connected. If all output lines to be connected can be connected, the state goes to state 4; if not, the state waits until connection can be made (state 3). If output is possible to all ports, transmission of packet data is started (state 4). If there is a port that cannot be output in this state, the packet data is stored in the multicast FIFO while transmitting the packet data to the port that can output. If the output-disabled port becomes available for output, data is transmitted from the multicast FIFO. When all the multicast packets have been transmitted, the state becomes a packet reception waiting state (state 0).

FIG. 7 shows an example in which the deadlock shown in FIG. 6 is avoided in the memory type exchange switch of the present invention.

This is an attempt to simultaneously perform multicast from PE0 and PE10 to all PEs (Processor Elements). When the present invention is used, the packet from PE0 can be transmitted to SU4 and SU5, but cannot be transmitted to SU6 and SU7.
Saves the data of the multicast packet without delay to the multicast memory. On the other hand, the packet from the PE 10 can be transmitted to the SUs 6 and 7 on the contrary.
Since the data cannot be transmitted to U4 and U5, the data of the multicast packet without delay is saved in the multicast memory. Thereafter, since transmission from SU0 to SU6 and SU7 is enabled, data is transmitted from the multicast memory. Similarly, since transmission from SU2 to SU4 and SU5 is enabled, data is transmitted from the multicast memory.

With such hardware and a control method, deadlock can be avoided at the time of multicasting even in a multi-stage network using warmhole routing as flow control.

Further, the present invention has an advantage that packets other than the multicast can be processed by the same control method as the conventional one.

[0056]

As described above, according to the present invention, W
When performing multicast in a multistage interconnected network using ormhole routing, deadlock can be avoided and multicast can be realized by a multicast buffer and a special control method. Since this multicast can be performed by one transfer, higher-speed multicast is possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a multistage connection network in the case of 64 PE.

FIG. 2 is a diagram showing a packet.

FIG. 3 is a block diagram of a conventional exchange switch.

FIG. 4 is a block diagram of a memory type exchange switch according to the present invention.

FIG. 5 is a block diagram of a FIFO type exchange switch of the present invention.

FIG. 6 is a diagram showing an example of deadlock occurring in the case of a conventional exchange switch.

FIG. 7 is a diagram showing an example in which the deadlock of FIG. 6 is avoided by the exchange switch of the present invention.

FIG. 8 is a specific state transition diagram of a conventional control method.

FIG. 9 is a specific state transition diagram of the control method of the memory type exchange switch of the present system.

FIG. 10 is a specific state transition diagram of the control method of the FIFO type exchange switch of the present system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Exchange switch 12 Input port 13 Output port 14 Packet 15 Header 16 Body 21 Buffer 22 Crossbar switch 23 Controller 31 Buffer 32 Crossbar switch 33 Controller 34 Multicast memory 41 Buffer 42 Crossbar switch 43 Controller 44 Multicast FIFO

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/56 H04L 12/18 H04L 12/28 JICST file (JOIS)

Claims (3)

(57) [Claims] In a multicast method in a communication network or a multi-stage computer network using wormhole routing, a plurality of switching switches having a plurality of input / output ports are connected. When it is impossible to output the multicast packet to the output port, the multicast packet is transmitted to the output port that can output, and at the same time, the packet data is stored in the multicast buffer provided separately from the input buffer, and the output that cannot be output is output. A multicast method, comprising: transmitting a packet from the multicast buffer when a port becomes available for output. 2. An N buffer for storing packet data, a controller for analyzing a header of the packet data and determining an output port for outputting the packet data, and M packets for storing the packet data stored in the buffer. An N-input / M-output crossbar switch for outputting to an output port designated by the controller among the output ports, and a switching switch in a communication network or multi-stage computer network using wormhole routing, wherein the N A multicast memory connected between a buffer and the crossbar switch for storing the packet data, wherein the controller can output a packet when it is unable to output a packet to one or more output ports during multicasting Sends the packet data to the output port and at the same time The packet data is stored in a buffer for multicasting, and when the output port that could not be output becomes available for output, control is performed so that packet data is transmitted from the multicast memory to the output port. switch. 3. A buffer for storing packet data, a controller for analyzing a header of the packet data and determining an output port for outputting the packet data, and M packets for storing the packet data stored in the buffer. An N-input M-output crossbar switch for outputting to an output port designated by the controller among the output ports, and a switching switch in a communication network using wormhole routing or a multi-stage computer network; M multicast FIFOs are connected between the output ports and the crossbar switch for each of the output ports and store the packet data, and the controller transmits packets to one or more output ports at the time of multicast. When output is no longer possible, a packet is Data is transmitted, and at the output port that cannot be output at the same time, packet data is stored in the corresponding FIFO for multicast, and when the output port that cannot be output becomes available for output, the output port receives the packet from the FIFO for multicast. An exchange switch for controlling transmission of packet data.