JP2776313B2 - Liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a drive system of an active matrix type liquid crystal display device used for a display, a projector, a television, and the like.

[0002]

2. Description of the Related Art Toward the multimedia age, a liquid crystal display compatible with various personal computers (hereinafter, PCs), workstations (hereinafter, WS), televisions, etc., having different video frequencies, pixel counts, and scanning methods. Equipment is being required.

In order to correspond to PC, WS, etc., it is necessary to perform a sequential scanning method in which scanning is performed in order regardless of odd-numbered lines and even-numbered lines. On the other hand, current television,
In order to support HDTV, it is necessary to perform so-called interlaced driving, in which pixels in odd lines are sequentially scanned in odd fields and pixels in even lines are sequentially scanned in even fields in accordance with a transmitted signal. There is a demand for a liquid crystal display device that can cope with this.

There is also a demand for a liquid crystal display device capable of enlarging and displaying an image having a smaller number of pixels than the liquid crystal display device has by an arbitrary multiple in both the vertical and horizontal directions. At that time, when displaying an image having a smaller number of pixels than the number of pixels of the liquid crystal display device, during the blanking period, the remaining upper and lower or left and right pixels outside the image display area are displayed in black. It is necessary to perform black display writing for the pixel.

In recent years, in liquid crystal projectors, which have become widespread as large-screen displays and presentation displays, three liquid crystals corresponding to red, green, and blue are used due to the difference in the number of times light reflected and bent through the liquid crystal display device. For one panel of the display device, the image needs to be mirror-inverted. Further, there is a need for a flexible liquid crystal display device that can handle front projection, rear projection, floor placement, and ceiling suspension with one liquid crystal projector device. For this reason, the scanning circuits constituting the vertical drive circuit and the horizontal drive circuit are both required to be capable of bidirectional scanning.

As described above, a liquid crystal display device which can cover all of the scanning method, enlarged display, movement, black display writing, and bidirectional scanning is strongly desired as a liquid crystal display device in the coming multimedia age. Hereinafter, such a liquid crystal display device is referred to as a multi-sync liquid crystal display.

On the other hand, with the aim of reducing the size and cost of the liquid crystal display device, a technology for integrating peripheral driving circuits on the same substrate as the liquid crystal display substrate has been developed. The peripheral drive circuit is
The vertical drive circuit scans the gates of the thin film transistors forming the active matrix array, and the horizontal drive circuit supplies image signals to pixels.

When a specific number of pixels are displayed by a specific scanning method, a shift register circuit is used as a scanning circuit used in a vertical driving circuit. However, when a shift register circuit is used, the circuit speed is limited,
Due to the limit of the data writing frequency, the above black display writing cannot be performed during the limited blanking period,
It is difficult to realize the multi-sync liquid crystal display device described above.

At present, an address decoder is used in a vertical drive circuit of a multi-sync liquid crystal display device. FIG.
FIG. 1 is a diagram showing a configuration of a conventional liquid crystal display device using an address decoder. As shown in the figure, the liquid crystal display device includes an active matrix array 401 for displaying an image, a vertical drive circuit 402, and a horizontal drive circuit 403. A plurality of control signals 404 for selecting a scanning line are input to the vertical drive circuit 402.

FIG. 6 is a diagram showing an example of a conventional driving method of a liquid crystal display device using an address decoder as the vertical driving circuit 402. Here, an example of sequential scanning is shown. The horizontal drive circuit 403 is a circuit corresponding to a multi-sync liquid crystal display device. Further, the number of scanning lines is 1024, and in that case, the control signal 40
The number 4 is A0, A0, A1, A1,.
9, the number of inverted A9 is 20.

In the video writing period (scanning period), a clock signal having a phase relationship as shown in the figure is input as the control signal 404, and Ai + 1 (i is from 0 to 9).
Clock period is 2 of the clock period of Ai.
Doubled. By inputting such a control signal 404, the scanning lines GP1, GP2,.
4 can be obtained.

If an address decoder is used, the control signal 4
Depending on the combination of the logic levels of 04, one or a plurality of arbitrary scanning lines can be simultaneously selected.
Therefore, in addition to the sequential scanning shown in FIG. 6, interlaced scanning and simultaneous driving of two lines can be easily performed. In addition, it can support enlarged display, movement of a display area, and bidirectional scanning.

Further, during the vertical blanking period,
Since the scanning lines of the pixels for which black display writing is desired can be selected at the same time, the time for upper and lower black display writing can be sufficiently long. For these reasons, an address decoder is used in a vertical drive circuit of a multi-sync liquid crystal display device.

The time required for writing to one display pixel of a liquid crystal display device is generally longer than the time required for output from a PC or the like. Therefore, usually PC
The video signal is sent to the liquid crystal display section by the signal processing section where the signal is branched into X lines (X is a positive integer) suitable for input to the liquid crystal display section.

[0015]

As described above, in a liquid crystal display device of the type in which a video signal is branched into a plurality of (X) video signals by a signal processing unit and transmitted to a liquid crystal display unit, the video signal after each branch is output. If there is an amplitude deviation between the signals, the quality of the displayed image deteriorates, which is problematic. Therefore, during the vertical blanking period, AG
C (automatic gain adjustment) processing is performed so that the output amplitudes of all X lines become a specified value.

Since much time is spent in the vertical blanking period in the AGC processing of the output amplitude, it is difficult to set the above-described black display writing processing time in this vertical blanking period. I have.

Further, this AGC processing is performed for the maximum of the video signal.
It is necessary to do for two amplitudes , the amplitude and the minimum amplitude, and therefore two AGCs in the vertical blanking period.
Due to the processing performed, it is more difficult to take the time for the black display writing process, and not only when a shift register is used for the vertical drive circuit, but also when an address decoder is used as shown in FIG. The same goes for

Further, in the case of the address decoder, as the number of scanning lines increases, the number of control lines also increases, which causes problems such as an increase in the size of the liquid crystal display module and an increase in cost. For example, if the number of scanning lines is 10
In the case of 24, 20 control terminals are required. Further, when the number of scanning lines exceeds 1024, 22 or more control terminals are required.

On the other hand, when a shift register is used for the vertical drive circuit, the number of clock signal terminals and input signal terminals required to drive the shift register is about three in total, regardless of the number of scanning lines. However, as described above, the shift register cannot cope with the multi-sync liquid crystal display device due to the limitation of the circuit speed.

An object of the present invention is to adapt to a multi-sync liquid crystal display so that a process for writing a black signal to a non-display portion of a liquid crystal display portion can be performed at high speed in a vertical blanking period. It is to provide a liquid crystal display device.

Another object of the present invention is to provide a small-sized and low-cost liquid crystal display device in which the number of drive control signals for a vertical drive circuit is greatly reduced as compared with an address decoder.

[0022]

According to the present invention, there is provided a liquid crystal display device having an active matrix array structure in which switching elements are respectively arranged at intersections of a plurality of scanning lines and a plurality of signal lines, and the scanning lines. Vertical driving means for driving the signal line, a horizontal driving means for driving the signal line, and an amplitude adjusting process of a signal corresponding to a black display signal of each branch signal by dividing the input video signal into a plurality of signals within a vertical blanking period. A vertical drive means for sequentially shifting a drive signal of the scanning line according to a shift clock; and a multiplying means for multiplying a frequency of a scanning clock as the shift clock. Shift control means for controlling start / stop of the shift operation of the shift means using a clock, and each shift after the shift operation of the shift means is stopped And a selection gate means for selecting in accordance with a selection control signal a force to the scan lines corresponding vertical Blanc
Within the king period, the shift control means
The shift operation is performed for a predetermined period after the shift means starts shifting.
Operation is stopped and the shift is performed by the selection gate means.
While supplying the selection shift output after the operation is stopped to the scanning line,
A liquid crystal display device characterized in that the horizontal drive means supplies a signal corresponding to the black display signal after the amplitude adjustment processing to the signal line.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.
That is, the drive data for driving the scanning line is shifted and transferred at a high speed by the shift register during the vertical blanking period, and the shift data is held and held for a certain period. An amplitude signal (both maximum and minimum amplitudes are signals corresponding to black display) is written according to the hold data.

The shift transfer of the driving data of the scanning line is performed by a high-speed clock during an AGC processing period immediately after the start of the vertical blanking period, and the shift register is held immediately after the AGC processing. By writing the processed black display equivalent signal in accordance with the hold data, high-speed black signal writing can be performed during the vertical blanking period, and the number of control signals can be reduced by using a shift register configuration. And

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a view showing one embodiment of the liquid crystal display device of the present invention. The liquid crystal display device includes the liquid crystal display unit shown in FIG. 1 and the signal processing unit shown in FIG.

The liquid crystal display section includes an active matrix array 101 in which thin film transistors are respectively arranged at intersections of a plurality of scanning lines and a plurality of signal lines, a vertical driving circuit 102 for driving each scanning line, and each signal. And a horizontal drive circuit 103 for driving the lines. In this embodiment, the number of scanning lines is 1024.

The vertical drive circuit 1 of the liquid crystal display device of this embodiment
02 is a half-bit 256-stage scanning circuit 104-1 that sequentially shifts the scanning line driving pulse signal VSTa input from the shift input terminal 107 in synchronization with a clock signal (not shown), as shown in FIG. 104-257,
The half bit configuration scanning circuits 104-1 to 104-2
, P256 and the gate control signals G1, G2,..., G8 as input signals.
And an output buffer circuit 106 that uses each output signal of the NAND gate circuit as an input signal. Outputs GP1 to GP1024 of each output buffer circuit are drive signals for each scanning line.

Half-bit scanning circuit 104-1 to 104-1
Four NAND gate circuits are connected to the respective outputs 04-257, and the control signals of eight adjacent NAND gate circuits are all different.

The scanning circuit 104 having a half bit configuration is used.
-1 to 104-257 are configured to be capable of bidirectional scanning (shifting), and when scanning in the reverse direction, the scanning line driving pulse signal VSTb is input from the other input terminal 108. The half-bit configuration scanning circuit 104-1
The circuits 104 to 257 use circuits driven by two-phase clock signals having a complementary phase relationship with each other.

Therefore, the half-bit configuration scanning circuit 104
The number of drive signals required to drive -1 to 104-257 is determined by two 2-phase clock signals including the scan line drive pulse signals VSTa and VSTb input when scanning in the forward and reverse directions. The total of four line drive pulse input signals is four. Further, NAND gate circuits 105-1 to 105-
In addition to the 1024 control signals G1 to G8, the total number of drive signals input to the vertical drive circuit 102 is twelve. The number of drive signals does not change even when the number of scanning lines exceeds 1024.

On the other hand, when the conventionally used address decoder is applied to a vertical drive circuit, the number of control signals is 20, as described above. That is, in the liquid crystal display device of the present embodiment, the number of drive signal terminals of the vertical drive circuit is 3/5 of the conventional one. Also, if the number of scanning lines is one,
When the number of control signals exceeds 024, the number of control signals of the address decoder is 22, and the number of drive signal terminals of the vertical drive circuit of this embodiment is about half of the conventional one.

As shown in FIG. 2, the signal processing unit develops a video signal input from the video signal input 111 into a number X suitable for the number of video input terminals of the liquid crystal display unit and branches. As a method of expansion performed here, a digital method of converting digital data using analog-digital conversion, performing layer expansion using a shift register or the like, and then returning to analog using digital-analog conversion, Alternatively, an analog method of performing layer development using a sample-and-hold or the like in an analog state is used.

Each output after layer development is performed by the AGC circuit 1
10-1 to 110-X, and the amplitude is adjusted to match the video input voltage range of the liquid crystal display unit.
Since this adjustment is performed using a blanking period so as not to affect the displayed image, the signal BLA112 indicating the blanking period and the maximum amplitude of the amplitude adjustment are output to the layer development unit. A signal H / L 113 for instructing whether to output the minimum amplitude or a signal AGC 114 for instructing execution of the AGC process.

FIG. 3 is a diagram showing an example of a driving method of the liquid crystal display device of the present invention. In this example, when displaying an image having a smaller number of pixels than the liquid crystal display device has by using the liquid crystal display device shown in FIG. 1, during the blanking period, the remaining upper and lower pixel regions are blackened. 1 shows an example of a driving method for writing. Hereinafter, a driving method in the case where pixels for 16 lines in each of the upper and lower lines are written in black display will be described with reference to FIG.

First, during the blanking period, the half-bit scanning circuits 104-1 to 104-257
A shift clock signal CLK having a clock cycle of TH and two scanning line drive pulse signals A and B having a pulse width of (2.times.TH) are input at the timing shown in FIG.

At this time, the time from the rise of the pulse signal A to the rise of the pulse signal B is (124 × TH) as shown in the figure. Thus, the shift clock signal CLK and the scanning line drive pulse signal VST
a, the half-bit scanning circuit 104
As the output signals P1 to P256 of −1 to 104-257, signals in which the two pulse signals A and B are sequentially shifted by (TH / 2) are output at the timing shown in FIG.

On the other hand, during this period, low-level signals are all input as the gate control signals G1 to G8 of the NAND gate circuit. As a result, regardless of the logic levels of the output signals P1 to P256 of the half bit configuration scanning circuit, the output signals GP1 to GP102 of the vertical drive circuit 102
4 is in a low level state. Note that the clock frequency (1 / TH) in this period is higher by about three digits than the clock frequency in the video signal writing period to perform the high-speed shift. The above operation of causing the liquid crystal display unit to read the selection signal of the scanning line of the liquid crystal display unit is performed during the first first AGC operation in the blanking period.

Following this period in which the two pulse signals A and B are shifted at a high speed about three orders of magnitude higher than the video writing period, after the pulse signal A is input, (12
After 8 × TH), the level of the clock signal is held low as shown in the figure. Thereby, the output signals P1 to P4 and P2 of the half bit configuration scanning circuit
53 to P256 are held at a high level as shown in the figure.

On the other hand, during this period, high-level signals are input as gate control signals G1 to G8 input to the NAND gate circuit, as shown in FIG. As a result, only when the control signals G1 to G8 of the NAND gate circuit are at the high level, the output signal G
P1～GP 16 and GP1009~GP1024 goes high.

In this period, an output for performing the AGC operation on the maximum amplitude side is performed from the signal processing unit, and the liquid crystal display unit uses the output as it is as a black signal for writing.
Incidentally, the liquid crystal display unit is a system called normally white, which is transparent when no video signal is written, and deserves to be shielded from the signal processing unit during the AGC period.
Since the video signal on the maximum amplitude side (or the minimum amplitude side) is output, black display can be realized by writing this.

During this period, a black display signal is written into the pixels of the upper and lower 16 lines. Normally, the writing period is set to be long enough for the black display signal to be sufficiently written in the selected pixel. Further, by adjusting the pulse widths of the pulse signals A and B, it is possible to adjust the line for writing black display.

Subsequent to the upper and lower black writing period, a clock signal having a clock cycle of TH is input again to the half-bit scanning circuits 104-1 to 104-257.
Thereby, the scanning circuit 104-1 having the half bit configuration is provided.
The data held at 104 to 257 is swept out at high speed.

On the other hand, during this period, all low-level signals are input as control signals G1 to G8 of the NAND gate circuit. As a result, regardless of the logic levels of the output signals P1 to P256 of the half-bit configuration scanning circuit,
The output signal of the vertical drive circuit is at a low level.

Also, during this period, in order to generate a scanning pulse signal in the video writing period, the pulse width TH
Is input at the timing shown in the figure, and the pulse signal C is transferred to the fourth stage. As a result, in the video writing period, the transfer starts from the fifth stage, and as the output of the vertical drive circuit, the scanning starts from the 17th scanning line which is the video display area.

FIG. 4 is a diagram showing another embodiment of the driving method of the liquid crystal display device of the present invention. In the present example, similarly to the example of FIG. 3, when displaying an image having a smaller number of pixels than the number of pixels of the liquid crystal display unit using the liquid crystal display device illustrated in FIG. This shows an example of a driving method of writing the remaining upper and lower pixel areas in black, but differs from the previous example in that pixels for the upper 15 lines and the lower 17 lines are written in black.

That is, the present embodiment shows a driving method when the video display device is moved by one line from the state of the previous example. This driving method is used when it is desired to freely move the image display area. Hereinafter, the driving method will be described.

First, during the blanking period, the half-bit configuration scanning circuits 104-1 to 104-257 supply
A shift clock signal CLK having a clock cycle of TH and scanning line drive pulse signals A and B are input at the timing shown in the figure.

At this time, the time from the fall of the pulse signal A to the rise of the pulse signal B is (124 × TH) as shown in the figure. As described above, by inputting the shift clock signal CLK and the scanning line driving signal VSTa, the half bit scanning circuits 104-1 to 104-1 are input.
As output signals P1 to P256 of 104-257, signals obtained by sequentially shifting the two scanning line driving pulse signals A and B by (TH / 2) are output at the timing shown in the figure.

On the other hand, during this period, all low level signals are input as control signals G1 to G8 of the NAND gate circuit. As a result, regardless of the logic levels of the output signals P1 to P256 of the half-bit configuration scanning circuit,
The output signal of the vertical drive circuit is at a low level.
Note that the clock frequency (1 / T) in this period is set to be about three digits higher than the clock frequency in the video writing period.

Following this period in which the two pulse signals A and B are shifted at a higher frequency by about three orders of magnitude than the video writing period, following the input of the pulse signal A, (1
After 27 × TH), the level of the clock signal is held high as shown in the figure. This allows
Output signals P1 to P4 and P of the half bit configuration scanning circuit
253 to P256 are held at a high level as shown in the figure. This period is defined as a first black writing period.

On the other hand, during this period, the gate control signals G1 to G4 and G8 input to the NAND gate circuit are set to high level, and G5 to G7 are set to low level. As a result, the output signals GP1 to GP4, GP8,
GP9-GP12, GP1008, GP1009-GP
1012, GP1016, GP1017 to GP102
0, GP1024 is at a high level. During this period, black display writing is performed for a part of the portion to be displayed black.

Following the first black writing period, the level of the clock signal is switched from a high level to a low level as shown in the figure. In this period, all the low-level signals are input as the control signals G1 to G8 of the NAND gate circuit, and the output signal P1 of the half-bit configuration scanning circuit is input.
The output signal of the vertical drive circuit is kept at a low level regardless of the logic levels of P256.

Following this period, the control signals G1 to G7 input to the NAND gate circuit are set to the high level and G8 is set to the low level while the logic level of the clock signal is held at the low level. As a result, the output signal GP of the vertical drive circuit
1 to GP7, GP9 to GP15, GP1009 to GP1
015, GP1017 to GP1023 are at a high level. During this period, black display writing is performed for a part of the portion to be displayed black. This period is the second
Black writing period.

Subsequent to the first and second black and white writing periods, a shift clock signal having a clock cycle of TH is supplied again to the half-bit scanning circuits 104-1 to 104-2.
Input to 57. As a result, the data held in the half-bit scanning circuits 104-1 to 104-257 is swept out at high speed.

On the other hand, during this period, all low level signals are input as the control signals G1 to G8 of the NAND gate circuit. As a result, the output signal of the vertical drive circuit is at a low level regardless of the logic levels of the output signals P1 to P256 of the half-bit scanning circuit.

During this period, the pulse width TH is used to generate a scanning pulse signal in the video writing period.
Is input at the timing shown in the figure, and the pulse signal C is transferred to the fourth stage. After that, the clock frequency is modulated, and a pulse signal whose phase is sequentially shifted in the order of G8, G1, G2,..., G7 is input as a control signal to be input to the logic gate circuit. As the output of the vertical drive circuit, scanning starts from the 16th scanning line which is a video display area.

By the driving method described above, the video display position can be moved in units of one line, and the black signal can be written in the non-display area above and below it.

The liquid crystal display portion of the liquid crystal display device of this embodiment is formed by integrating polycrystalline silicon thin film transistors on a glass substrate. The vertical drive circuit and the horizontal drive circuit are configured by CMOS static circuits.
Of course, it is also possible to configure a MOS dynamic circuit.

Although a polycrystalline silicon thin film transistor is used in this embodiment, the thin film transistor may be formed of another thin film transistor using amorphous silicon, cadmium selenium, or the like for the semiconductor layer. In addition, it is of course possible to configure a single-crystal silicon MOS transistor.

[0061]

As described above, according to the present invention, in a system for shifting and transferring scanning line drive data by a shift register, this shift operation is processed at a higher speed by using a clock higher than a scanning clock, and a video image is displayed. Since the writing is performed using the black display equivalent signal after the AGC processing of the signal as it is, there is an effect that the scanning line driving data transfer processing and the black signal writing processing can be performed within the vertical blanking period.

Further, by using the shift register system for the vertical drive circuit, the number of control signals to be input becomes extremely small, and the size and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a liquid crystal display unit of a liquid crystal display device of the present invention.

FIG. 2 is a diagram showing an embodiment of a signal processing unit of the liquid crystal display device of the present invention.

FIG. 3 is a diagram illustrating an example of a driving method of the liquid crystal display device of the present invention.

FIG. 4 is a diagram showing another example of the driving method of the liquid crystal display device of the present invention.

FIG. 5 is a diagram showing a conventional liquid crystal display device.

FIG. 6 is a diagram illustrating an example of a conventional driving method of a liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 101 active matrix array 102 vertical drive circuit 103 horizontal drive circuit 104-1 to 104-257 half-bit scan circuit 105-1 to 105-1024 NAND gate circuit 106 buffer circuit 107, 108 scan line drive signal input terminal 109 X layer developing section 110-1 to 110-X AGC circuit 111 Video signal input 112 BLA input 113 H / L input 114 AGC input

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-95071 (JP, A) JP-A-4-165329 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/133 G09G 3/36

Claims (4)

(57) [Claims] 1. An active matrix array-structured liquid crystal display device in which switching elements are respectively arranged at intersections of a plurality of scanning lines and a plurality of signal lines; vertical driving means for driving the scanning lines; A liquid crystal display device comprising: horizontal driving means for driving lines; and signal processing means for branching an input video signal into a plurality of parts and performing amplitude adjustment processing of a signal corresponding to a black display signal of each branch signal within a vertical blanking period Wherein the vertical driving means shifts the drive signal of the scanning line sequentially according to a shift clock, and the shift operation of the shift means uses a multiplied clock obtained by multiplying a frequency of a scanning clock as the shift clock. Control means for performing start / stop control of the shift operation, and selecting and controlling each shift output after the shift operation of the shift means is stopped corresponding to the scanning line. Select gate means for selecting according to a signal , wherein the shift control means is provided within a vertical blanking period.
A predetermined period after starting the shift by the shift means.
Stop the shift operation during the
The selected shift output after the shift operation is stopped is applied to the scanning line.
While supplying, the horizontal drive means corresponds to the black display signal
A liquid crystal display device, wherein the signal after the amplitude adjustment processing of the signal to be supplied is supplied to the signal line. 2. The signal processing means is configured to perform the amplitude adjustment processing immediately after the start of a vertical blanking period, and the shift control means performs the shift operation during the amplitude adjustment processing of the signal processing means. 2. The liquid crystal display device according to claim 1, wherein the control is performed in such a way as to be performed in the following manner. 3. A signal corresponding to the black display signal is a maximum / minimum amplitude of the input video signal, and the signal processing means performs one of the maximum / minimum amplitude in a first period immediately after the start of a vertical blanking period. , And the other of the maximum / minimum amplitude is adjusted in a second period immediately before the end of the vertical blanking period, and the shift control unit controls the shift unit in the second period. 3. The liquid crystal display device according to claim 2, wherein the control is performed such that the contents are discharged. 4. During the first and second periods,
4. The liquid crystal display device according to claim 3, wherein the selection control signal is set and controlled differently in the first half and the second half, and the output of the selection gate means is controlled according to each selection control signal.