JP2770743B2 - Weight control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a weight control system such as a microprocessor and a microcontroller, and more particularly to a microprocessor and a microcontroller having an internal weight control circuit.

[0002]

2. Description of the Related Art In a system using a microprocessor, a microcontroller, or the like, a central processing unit (hereinafter referred to as a "CPU") accesses a device such as a memory or an I / O device having a low operating speed by a bus cycle. A technique for extending a bus cycle by generating a wait (WAIT) according to the operation speed when performing the operation is widely known.

As this type of weight control circuit, for example, Japanese Patent Application Laid-Open No. 63-66659 discloses a program in which wait timings according to the characteristics of each I / O device are set in advance,
The register where the wait timing is set from each I / O
A weight control circuit of a microcomputer provided in the apparatus (referred to as “conventional example 1”) has been proposed. That is, in the publication, each I / O device is provided with a register,
When accessing multiple I / O devices, by setting different weight data depending on the characteristics of each I / O device,
A method for performing programmable weight control is disclosed.

In Japanese Patent Application Laid-Open No. 3-135649, a general memory means having an address input is used to store different weight values for a plurality of access targets such as an I / O device in the memory means. When accessing the memory means in parallel with a part of the address value of the bus cycle when the CPU accesses various memories and I / O devices, use the wait value stored in the memory means. Weight control circuit that performs weight control by means of a conventional method (referred to as "conventional example 2")
Has been proposed.

[0005]

Problems to be solved when the above-mentioned conventional weight control circuit is used will be described below.

In the first prior art, since registers provided for each I / O device for setting wait timing data are initialized at the time of reset, all I / O devices are reset until the CPU resets them by a program. The weight value of the / O device is fixed to either the maximum or the minimum.

When the weight value is fixed to the maximum, the access speed becomes extremely slow until the program sets an initial value in the register of each I / O device.

For this reason, when the wait control method of the prior art 1 is used for a memory for storing programs and data, there is a problem in that the execution speed and performance of the microcomputer are deteriorated until the wait value is reset. Become.

Particularly, in the case of a test using an LSI tester at the time of manufacturing an LSI or the like, since the test time is directly related to the manufacturing cost, the decrease in the execution speed immediately after the reset of the microcomputer which is a non-test device is large. It becomes a problem.

On the other hand, when the weight value is fixed to the minimum, access to the I / O device and the like cannot be performed until the weight value is reset.

Generally, a memory such as a ROM (Read Only Memory) or a RAM (Random Access Memory) in which programs and data are stored has a lower operation speed than a CPU.

At the time of starting the CPU, in order to prevent the ROM and the data RAM storing the necessary programs from being set to the minimum wait, these ROMs and RAMs must be removed from the wait control target according to the conventional example 1. It is necessary to exclude and separately generate a weight in an external circuit.

The objects that can be initialized to the minimum weight value are limited to only those not directly related to system startup, such as some I / O devices.

Further, in the wait control circuit of the conventional example 2, since a general memory means having an address input is used for setting the wait value, the value at the time of resetting is undefined.

Therefore, the memory or the I / O device to be wait controlled cannot be accessed until the initial value is set by the program after the reset.

Since the ROM for storing the initial value setting program for defining the operation of the CPU after resetting must be excluded from the wait control, a ROM corresponding to the operating speed of the CPU may be used. Wait control for this ROM is required and must be provided separately.

Recently, the operating frequency of a processor has been increased, and the speed difference between the processor and a memory has been increasing.

Therefore, the number of waits (that is, the number of CPU clocks) that can be specified by the built-in wait control also increases.

Setting the weight control to the maximum weight at the time of resetting for the convenience of the user causes a large number of clocks to be lost in a simulation at the time of LSI development or a test by an LSI tester at the time of LSI manufacture or the like. .

Accordingly, it is an object of the present invention to provide a weight control circuit and a weight control method which solve the above problems and speed up the transition of weight control. It is another object of the present invention to provide a weight control circuit and a weight control method that enable high-speed and efficient evaluation in a simulation, a tester, or the like.

[0021]

In order to achieve the above object, the present invention provides a central processing unit, which is inserted into a bus cycle.
A register in which a wait value is set, a counter, and counter control means for controlling the loading and counting of the count value into the counter, wherein the counter counts the count value loaded from the register in a bus cycle. period counting, the is configured to request the weight to the central processing unit, at the time of reset, the register
The star is initialized to the maximum weight value and the maximum number of ways
Is inserted in the bus cycle, and after reset,
The desired value is stored in the register by executing the instruction of the central processing unit.
By setting, the optimum wait value is
And a weight control circuit for the microprocessor.

In the present invention, the central processing unit has a c.
Has an external terminal for externally specifying
A wait release signal input from the external terminal;
Of the signal output by the counter at the end of counting the count value.
When any of them are active,
It is characterized in that the site request is canceled .

Also, in the present invention, the central processing unit
Value can be set by executing instructions of the central processing unit
Registers, counters, and the loading of values to the counters
Counter control means for controlling the execution of
Request a wait for the central processing unit bus cycle.
Weight request means, and the weight of the central processing unit.
An external terminal for externally specifying release
A microprocessor, wherein the counter control means
The signal output from the central processing unit at the start of a cycle
Count value from the register to the counter based on
Is controlled to be loaded, and the weight requesting means is controlled.
Is input from an external terminal in a bus cycle.
The signal to specify the release of the wait and the number of waits
A signal indicating the state of the counter,
Control the weight for the device and input from the external terminal
The wait release signal and the counter
When one of the signals output at the end of counting is active
The wait request to the central processing unit is released,
It is characterized by having been constituted as follows.

Further, in the present invention, at the time of reset,
The register is initialized to the maximum weight value and the external
Wait release state of wait release signal input from pin
Depending on the value indicating the state, the wait bus
Non-insertion into cycle / bus cycle with maximum number of waits
Insertion into the file is selectively controlled .

According to a second aspect of the present invention, a central processing unit, a counter whose count value can be set variably, a plurality of registers whose values are set by executing instructions of the central processing unit, and a plurality of registers are provided. Address range detecting means for detecting a range of the selected address space, wherein the address range detecting means inputs an address signal, selects one of the address ranges, and corresponds to the selected address range for each bus cycle. The wait value to be loaded is selectively loaded into the counter from any one of the plurality of registers, and the bus requests a wait to the central processing unit for a period during which the counter counts the loaded count value in a bus cycle. And a weight control circuit for a microprocessor configured as described above.

According to the present invention, in the second aspect, the external terminal for externally designating cancellation of the wait of the central processing unit is provided, and the external terminal is provided for each of a plurality of divided address spaces. A wait request signal is supplied to the central processing unit based on a wait release designation signal input from the outside and / or a signal indicating a count state of the counter. The wait release designation signal (= ready signal) externally input to the external terminal is an inverted value of the wait. As a signal indicating the count state of the counter, preferably, a zero detection output that becomes "1" when the counter value of the down counter is in a zero value state is used as a wait release designation signal, and the zero detection output becomes "0". At the time, a wait request is specified.

Further, according to a third aspect of the present invention, there is provided a counter having a variably settable count value, and a wait request to the central processing unit during a period determined by the count value of the counter in a bus cycle. A method of controlling the wait of a microprocessor, wherein when the microprocessor is reset, a maximum count value is set in the counter and the maximum number of waits are inserted into a bus cycle. Is variably set, and a microprocessor weight control method is provided.

The present invention further provides a counter whose count value can be set variably, an address range detecting means for detecting a range of a plurality of divided address spaces, and a plurality of registers for setting the number of waits in the counter. The address range detecting means inputs an address signal and selects one of the address ranges for each bus cycle, and a weight value corresponding to the selected address range is selected from one of the plurality of registers. A weight control method for a microprocessor, wherein the weight control is variably performed according to a division of an address space to be selectively loaded into the counter and accessed.

[0029]

According to the present invention, since the register for setting the wait value to the down counter is set to the maximum number of waits at the time of reset under the above configuration, the interface with a low-speed memory or I / O at the time of starting the CPU is provided. In addition to securing the optimal wait value by executing the program after resetting, the external wait control circuit can be simplified and the connection between the microprocessor, the memory and the I / O device can be established. It's easier.

Further, according to the present invention, in a simulation at the time of LSI development or a test at the time of LSI manufacture, if the external wait input terminal is always fixed to “0”, the CPU does not depend on the state of the down counter, and Is always ready (=
(Wait release status) is supplied, so immediately after reset, regardless of the internal wait value register, the CPU
Can be operated without weight. In addition, since a program for resetting the value of the weight value register to zero can be omitted, simulation or LSI
Test program size and execution time can be reduced.

Further, according to the second aspect of the present invention, the connection is made by changing the weight value register used according to the address range, or by selectively using the external wait terminal and the internal wait control. It is possible to perform appropriate weight control for a memory or an I / O device. Further, since a wait control register may be provided only in a space requiring internal weight control, the amount of hardware used can be reduced.

According to the wait control method of the present invention, the maximum wait value is inserted into the bus cycle at the time of reset to secure an interface with a low-speed memory or I / O at the time of starting the CPU, and to execute the program after reset. By resetting the weight value to the optimum value, the external weight control circuit is simplified and the connection between the microprocessor, the memory and the I / O device is facilitated.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

[0034]

FIG. 1 is a block diagram of a microprocessor according to a first embodiment of the present invention.

Each component will be described with reference to FIG.
In FIG. 1, 101 is a microprocessor, 102 is a CPU.
(Central processing unit), 103 is a down counter, 104 is a register for setting a weight value (also referred to as a “weight value register”), 105 and 106 are OR gates, and 107 is a NOT gate (inverter).

Reference numeral 108 denotes a clock input terminal (CLKIN) to the microprocessor 101, and reference numeral 109 denotes a microprocessor 10
A reset input terminal (RSTIN) to 1 and 110 is a wait input terminal (READYZ) to the microprocessor 101.

Reference numeral 111 denotes a clock input of the CPU 102 (CPUCL
K), 112 is reset input (CPURESET) of CPU102, 113 is C
A ready input (CPU READY) 114 of the PU 102 is a bus cycle start signal (BCYST) output from the CPU 102.

Reference numeral 115 denotes a clock input (CCLK) of the down counter 103, 116 denotes a reset input (CRESET) of the down counter 103, and 117 denotes a zero detection output (CZERO) output when the counter value of the down counter 103 is zero. Reference numeral 118 denotes a load signal input (CLOAD) for controlling the loading of the counter value of the down counter 103, and 119 denotes a data input (CDATA) of the down counter 103. Reference numeral 120 denotes a bus control signal group including addresses, data, and the like for the CPU 102 to access an external memory and I / O.

In FIG. 1, a reset input terminal (RSTI
The reset signal input from N) 109 is supplied to the reset input (CPURESET) 112 of the CPU 102 and the register 104, and is also supplied to the reset input (CRESET) 116 of the down counter 103 via the OR gate 106.

The signal input to the wait input terminal (READYZ) 110 passes through a NOT gate 107 and an OR gate 105, and becomes a ready signal (READY) of the CPU 102 as a ready signal (READY).
PUREADY) 113.

More specifically, when a weight of the CPU 102, which will be described later, is sampled, a weight input terminal (READYZ) 110
Is "1" (that is, the ready signal (READY) is "0"), a wait is designated to the CPU 102, and if the wait input terminal (READYZ) 110 is "0" at the time of sampling (that is, the ready signal (READY)). READY) is “1”), and instructs the CPU 102 to release the wait.

As described above, the wait input terminal (READYZ)
When "0" is input to 110, the ready signal (READY) is activated, and in this embodiment, the ready signal (READY) is an inverted value of the wait signal. Therefore, the name of the wait input terminal 110 is “READYZ”, which indicates that it is a ready signal of negative logic.

The zero detection output (CZERO) 117 of the down counter 103 is input to the ready input (CPU READY) 113 of the CPU 102 via the OR gate 105.

Next, the bus cycle of the CPU 102 will be described with reference to the timing charts of FIGS.

FIG. 2 shows a bus cycle of the CPU 102 when no wait is input, and FIG. 3 shows a bus cycle of the CPU 102 when one wait is input.

As shown in FIG. 2, the bus cycle of the CPU 102 is synchronized with the rising edge of the clock input (CPUCLK) 111.
It consists of two types of states, "T1" and "T2".

The T1 state is a state at the start of a bus cycle. When a bus control signal such as an address is started to be output, the bus cycle start signal (BCYST) 114 is set to the T1 state.
It becomes "1" during the state.

At the next clock after the T1 state, the state always transitions to the T2 state.

In the T2 state, the CPU 102 sets the ready input (CPUREADY) 113 at the fall of the clock input (CPUCLK) 111.
Is sampled (see the timing shown by the arrow in the figure), and if the ready input (CPU READY) 113 is "1", the bus cycle ends.

Sampled ready input (CPU READY)
If “113” is “0”, as shown in FIG. 3, the T2 state continues in the next clock period, and a wait is inserted in the bus cycle.

Next, the operation of the down counter 103 will be described with reference to the timing charts of FIGS. FIG. 4 shows a reset operation of the down counter 103,
FIG. 5 shows the operation of the down counter 103 when loading and when counting down.

As shown in FIG. 4, when the reset input (CRESET) 116 of the down counter 103 is input, the down counter 103 is reset to zero in synchronization with the rising of the next clock input (CCLK) 115, and at the same time, Zero detection output (CZE
RO) 117 becomes “1”.

When the load signal input (CLOAD) 118 of the down counter 103 is activated as shown in FIG. 5, data is input to the down counter 103 in synchronization with the next rising edge of the clock input (CCLK) 115. The value input to (CDATA) 119 is loaded. The down counter 103 sequentially counts down from the loaded counter value in synchronization with the rising edge of the clock input (CCLK) 115. FIG.
As shown in (1), the down counter 103 stops counting when the count value becomes zero.

Next, the CP described with reference to FIGS.
Based on the bus cycle of U102 and the operation of the down counter 103 described with reference to FIGS. 3 and 4, the operation of the wait control method of the present embodiment will be described with reference to FIGS.

Normally, an external wait request to the CPU 102 is input from a wait input terminal (READYZ) 110, inverted by a NOT gate 107, and then input to a ready input (CPUREADY) 113 of the CPU 102 via an OR gate 105. Is done.

First, when a reset signal externally input to the reset input terminal (RSTIN) 109 is activated, a reset signal (READY) input to a reset input (CPURESET) 112 of the CPU 102 is activated, and the CPU 102
Is reset, and the down counter 103 is reset by a reset input (CRESET) 116 via the OR gate 106.

The same reset signal causes the weight value register 104 to be initialized not to zero but to its maximum value. The weight value register 104 is automatically set to the maximum value at the time of reset.
A desired value is set via the bus control signal group 120 by a predetermined instruction executed in U102.

After the reset, when the CPU 102 starts a bus cycle, a bus cycle start signal (BCYST) 114 is output in synchronization with the state "T1".

The bus cycle start signal (BCYST) 114 is input to the load signal input (CLOAD) 118 of the down counter 103, and as described with reference to FIG. CDATA) 119 is loaded into the counter value.

In the state "T2", since the loaded count value is non-zero, the zero detection output (CZERO) 117 is "0", and as long as the external wait input terminal (READYZ) 110 is "1", The output of the OR gate 105 becomes "0". That is, the ready input (CPU READY) 113 of the CPU 102 becomes “0”, and a wait is entered in the bus cycle.

The down counter 103 receives a clock input (CCL
K) Since the count advances in synchronization with the rise of 115, the count is stopped when the count value becomes zero. In synchronization with the count value becoming zero, zero detection output (CZER
O) Since 117 becomes "1", the ready signal (READY) becomes "1" (active) via the OR gate 105, and the CPU 10
The wait is released by being input to the second ready input (CPU READY) 113.

The timing chart of FIG. 6 shows the signal waveforms of FIG. 1 when the value of the weight value register 104 is "3" in the above operation.

As shown in FIG. 6, in the T1 state, the bus cycle start signal (BCYST) 114 becomes "1" and the register 10
The value 3 of 4 is loaded as the counter value of the down counter 103. At the time of sampling in the T2 state, the count value is "3", so the zero detection output (CZERO) 117 is "0", and the ready signal (READY) is Is set to “0” and T
Wait is inserted after 2 states, and down counter 1
Until the count value of 03 becomes “0”, waits for a total of three clocks are inserted.

FIG. 7 is a timing chart when a wait release signal is input to the wait input terminal (READYZ) 110 while the count value of the down counter 103 is non-zero. That is, FIG. 7 is a timing chart when the wait input terminal (READYZ) 110 becomes “0” in the second state “T2” (that is, the counter value is “2”) in FIG.

As shown in FIG. 7, the signal (= "0") externally input to the wait input terminal (READYZ) 110 is N
The output is inverted by the OT gate 107 (EREADY = “1”), the output of the OR gate 105 (READY = “1”) is input to the ready input (CPUREADY) 113 of the CPU 102, and the wait of the CPU 102 is released. It is input to the reset input (CRESET) 116 of the down counter 103 via 116 to reset the counter value of the down counter 103 to zero.

In FIGS. 6 and 7, this embodiment has been described for the case where the value of the register 104 is "3". However, in practice, the operating frequency of the high-speed microprocessor and the low-speed memory and In order to interface with the / O access time, the initial value at the time of resetting the register 104 takes a large value, for example, from “15” to “31”.

As described above, according to this embodiment,
By setting the register 104 to the maximum number of waits at the time of reset, an interface with a low-speed memory or I / O is secured, and the optimum wait value is reset by executing the program after the reset. This enables the external weight control circuit to have a simple configuration and facilitates the connection between the microprocessor, the memory, and the I / O device.

Also, according to the present embodiment, in the simulation at the time of LSI development and the test at the time of LSI manufacture, the external wait input terminal (READYZ) 110 is always fixed to “0” so that the ready input (CPU) CPUREADY) 113 is always activated to set the wait release state, and even at the time of reset, CPU 102 can be operated without wait regardless of internal wait value setting register 104.

According to the present embodiment, by always fixing the external wait input terminal (READYZ) 110 to “0”, the value of the weight value setting register 104 is
Because the program for resetting to zero by executing the PU102 instruction can be omitted, simulation and LSI
Test program size and execution time can be reduced.

Also, according to the present embodiment, the CPU 102 can be set to zero wait by setting the external wait input terminal (READYZ) 110 to "0" and always in the wait release state immediately after the reset of the microprocessor 101. Even in a system in which access of peripheral devices having dynamically changing wait times and access of peripheral devices having fixed wait times coexist, it is possible to easily shift to the zero wait state as compared with the related art.

According to the present embodiment, as shown in FIG. 1, a signal from the wait input terminal (READYZ) 110 is changed to a ready input (CPUREADY) which is a wait release signal to the CPU 102.
And a reset input to the down counter 103 (CRESE
Since T) 116 is used in common, a dedicated external terminal or the like for resetting down counter 103 is not required.

[0072]

Embodiment 2 FIG. 8 is a block diagram of a microprocessor according to a second embodiment of the present invention.

In FIG. 8, the elements having the same functions as those in FIG. 1 are denoted by the same reference numerals. Hereinafter, only differences from the first embodiment will be described.

In FIG. 8, in addition to the first embodiment shown in FIG. 1, a decoder 501 for decoding upper two bits of an address, a second register 502 for setting a weight value, A value selector 503, AND gates 504 to 509, and OR gates 510 and 511 are provided.

A second register for setting a weight value
502 is initialized to the maximum wait value at the time of reset similarly to the register 104, and after reset, a desired value is set via the bus control signal group 120 by a predetermined instruction executed in the CPU 102.

In the present embodiment, the upper two bits of the address signal from the CPU 102 are decoded by the decoder 501 to divide the address space into four.

FIG. 9 shows an example of a method of selecting external weight control by weight input terminal (READYZ) 110 and internal weight control by weight value setting registers 104 and 502 for each of four address spaces. Have been.

The operation of the second embodiment of the present invention will be described below with reference to FIGS.

First, an address space in which the upper two bits of the address are "00" (referred to as an address space "00") will be described.

As shown in FIG. 9, for the address space "00", both the external weight control and the internal weight control are enabled, and the external weight control by the weight input terminal (READYZ) 110 and the weight value setting Internal wait control by the registers 104 and 502 is used.

In the bus cycle for the address space “00”, the “00” output of the decoder 501 becomes “1”,
The AND gate 504 having the "00" output as one input outputs the bus cycle start signal (BCYST) 114 output from the CPU 102, which is the other input, at the start of the bus cycle as it is, and the bus cycle start signal (BCYST) 114 Is a load signal input (CLOAD) 119 of the down counter 103 via the OR gate 511.
Is input to Selector is selected by the output of AND gate 504
Reference numeral 503 selects the output of the register 104, and the value of the register 104 is loaded as a counter value from the data input (CDATA) 119 of the down counter 103.

Similarly, the “501” output of the decoder 501
Since one of the inputs of the ND gates 508 and 509 is "1",
D gates 508 and 509 output the other input as it is.

For address space "00", decoder 501
Since the outputs of “01” and “10” are “0”, the outputs of the AND gates 506 and 507 are always “0”.

As described above, when the states of the AND gates 506, 507, 508, and 509 are integrated, the output value of the OR gate 105 is directly input to the ready input (CPU READY) 113 of the CPU 102 in the bus cycle for the address space "00". The output (EREADY) of the NOT gate 107 is directly input to the OR gate 106.

This state is the same as that of the first embodiment shown in FIG.

Therefore, in the bus cycle for the address space "00", as in the first embodiment, the internal wait control based on the count control of the down counter 103 and the input to the external wait input terminal (READYZ) 110 are performed. Both the external weight control based on the signal to be performed effectively functions.

Next, the upper two bits of the address signal are set to "0".
The address space "01" which is 1 "will be described. FIG.
As shown in the figure, the address space "01" uses only the external wait.

In the bus cycle for the address space "01", the "01" output of the decoder 501 becomes "1".

Therefore, the four AND gates 506, 507, 508,
Of the 509, only the AND gate 507 passes the other input signal. Since the outputs of the AND gates 508 and 506 can take only “0”, the zero detection output (CZERO) 11 of the down counter 103
7 is not transmitted to the ready input (CPU READY) 113 of the CPU 102, and the operation of the down counter 103 is not transmitted to the ready input (CPU READY).
Y) Does not affect 113.

External wait input terminal (READYZ) 11
Signal (EREADY) input to 0 and inverted by NOT gate 107
Is input to a ready input (CPU READY) 113 through an AND gate 507 and an OR gate 510.

In this state, only the external wait control works effectively.

Next, the upper two bits of the address signal are set to "1".
The address space “10” that is “0” will be described. FIG.
As shown in the figure, the address space "10" uses only internal weights.

In the bus cycle for the address space "10", the "10" output of the decoder 501 becomes "1".
The selector 503 selects the value of the second register 502 as the value to be loaded into the down counter 103 by the bus cycle start signal (BCYST) 114. When the bus cycle is actually started, the bus cycle start signal (BCYST) 114 is ANDed
Down counter 103 through gate 505 and OR gate 511
Is input to the load signal input (CLOAD) 118 of the
The selector 503 selects the register 502 via 05.

The four AND gates 506, 507, 508, 50
Of the 9, only the AND gate 506 passes the other signal.

Since the output of the AND gate 509 can only take "0", it is input to the wait input terminal (READYZ) 110 and
The signal (EREADY) inverted by the gate 107 is output to the OR gate 106
Reset input (CRESET) of down counter 103 via 1
16 is never transmitted.

A weight input terminal (READYZ) 110
Is passed through the AND gates 507 and 508 to the ready input (C
PUREADY) 113 is not affected.

The zero detection output of the down counter 103 (CZER
O) 117 is transmitted to the ready input (CPU READY) 113 through the AND gate 506 and the OR gate 510.

This state is a state where only the internal wait control works effectively.

Next, the upper two bits of the address signal are set to "1".
The address space “11” that is “1” will be described. FIG.
As shown in the figure, in the address space "11", both the external and internal waits are invalidated.

In the bus cycle for the address space "11", the "11" output of the decoder 501 is "1" and the other outputs are "0", so that the four AND gates 506, 507, 5
The outputs of 08 and 509 are always "0".

Further, since the "11" output of the decoder 501 is input to the ready input (CPU READY) 113 of the CPU 102 via the OR gate 510, the CPU 102 enters the wait release state.

In this state, neither the external weight control nor the internal weight control works.

As described above, in this embodiment, as shown in FIG. 9, when the upper two bits of the address are "00", the register 104 for setting the wait value is used, and both the internal wait control and the external wait terminal are valid. When "01", only the external wait terminal is enabled, when "10", the second register 502 for setting the weight value is used and only the internal wait control is enabled, and when "11", the internal wait control is enabled. And the external wait terminal are invalidated.

As a result, the address space "00" is
02 is a program area where program execution starts after reset, address space "01" is an area of an I / O device in which the number of waits dynamically changes, and address space "10" is an area using a fixed number of waits. / O device area, address space "1
In the case of "1", the weight control can be selectively used for each address space, such as an area of an I / O device built in the microprocessor which can be accessed without waiting.

As described above, in this embodiment, by changing the value of the weight value register used in accordance with the address range, or by selectively using the external wait terminal and the internal wait control, the memory to be connected can be changed. Appropriate weight control can be performed on the I / O device.

Further, since a wait control register may be provided only in a space requiring internal wait control, the amount of hardware used can be reduced.

[0107]

The weight control circuit according to the present invention has the following effects.

According to the present invention, at the time of reset, the register for setting the wait value to the counter is set to the maximum number of waits. Therefore, at the time of starting the CPU, an interface with a low-speed memory or an I / O device is secured, After that,
By executing the program on the CPU, it is possible to reset the optimal weight value to the register, which speeds up the weight control and simplifies the circuit configuration of the external weight control circuit. The connection between the microprocessor, the memory and the I / O device is facilitated.

Further, according to the present invention, the external wait signal is always kept in the wait release state immediately after the reset of the microprocessor, so that zero wait can be achieved. Even in a system in which accesses from peripheral devices having a fixed wait time coexist, the state can be easily shifted to the zero wait state as compared with the related art.

According to the present invention, in a simulation at the time of LSI development or a test at the time of LSI manufacture, the external wait input terminal is always set to “0” to set the central processing unit to the wait release state. However, immediately after reset, the central processing unit can be operated without wait regardless of the internal wait value register.
Loss of a large number of clocks can be avoided, and simulation or test time can be reduced in evaluation by simulation or test to achieve faster and more efficient evaluation.

Further, according to the present invention, since the program for resetting the value of the weight value register to zero can be skipped, the program size and execution time of the simulation and the LSI test can be reduced.

That is, even when the weight value register is set to the maximum weight at the time of reset during simulation during LSI development or use of the LSI tester during manufacture, it is not necessary to execute an extra instruction sequence for canceling it. Therefore, efficiency can be improved.

Further, according to a second aspect of the present invention, the connection is made by changing the weight value register used according to the address range, or by selectively using the external wait terminal and the internal wait control. Memory and I / O
Appropriate weight control can be performed on the device. Also,
Since a wait control register may be provided only in a space requiring internal weight control, the amount of hardware used can be reduced.

The signal from the external wait terminal is transferred to CP
Since the wait control signal is shared by the wait signal for U and the reset signal to the counter control means, an external terminal dedicated to resetting the wait control counter is not required, and an increase in the number of external terminals is avoided.

Further, according to the wait control method of the present invention, the maximum wait value is inserted into the bus cycle at the time of reset to secure an interface with a low-speed memory or I / O at the time of starting the CPU, and to execute the program after reset. By resetting the weight value to the optimum value, the external weight control circuit is simplified and the connection between the microprocessor, the memory and the I / O device is facilitated.

Further, according to the weight control method of the present invention, the weight value can be variably adjusted according to the divided address range, and appropriate weight control can be performed for each connected memory or I / O device. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a timing chart illustrating a bus cycle of a CPU 102.

FIG. 3 is a timing chart illustrating a bus cycle of a CPU 102 (wait insertion).

FIG. 4 is a timing chart for explaining an operation at the time of resetting a down counter 103;

FIG. 5 is a timing chart illustrating the operation of the down counter 103 when loading.

FIG. 6 is a timing chart illustrating the operation of the first exemplary embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the first embodiment of the present invention (when a wait release signal is input from outside while the down counter is counting).

FIG. 8 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of correspondence between an address space and weight control according to a second embodiment of the present invention.

[Explanation of symbols]

101 Microcomputer 102 CPU 103 Downcounter 104 Register for setting weight value (weight value register) 105, 106 OR gate 107 NOT gate (inverter) 108 Clock input (CLIKIN) terminal 109 Reset input (REST) terminal 110 Wait input terminal ( READYZ: Ready signal input terminal 111 Clock input of CPU 102 (CPUCLK) 112 Reset input of CPU 102 (CPURESET) 113 Ready input of CPU 102 (CPURESET) 114 Bus cycle start signal (BCYST) 115 Clock input of down counter 103 (CCLK) 116 Reset input of down counter 103 (CRESET) 117 Zero detection output of down counter 103 (CZERO) 118 Load signal input of down counter 103 (CLOAD) 119 Data input of down counter 103 (CDATA) 120 Bus control signal group 502 Weight setting 503, selector 504, 505, 506-509 AND gate 510, 511 OR gate T1 T1 Tate T2 T2 state

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 13/42

Claims (8)

(57) [Claims] 1. Insertion into a central processing unit and a bus cycle
It includes a register weight value is set, a counter, and a counter control unit for controlling the loading and counting of the count value to the counter, the bus cycle, if the counter is said register
Period for counting the Luo loaded count value, is configured to request the weight with respect to said central processing unit, at the time of reset, the register is initialized to the maximum weight value
And the maximum number of waits are inserted into the bus cycle.
After the reset, the central processing unit executes the instruction.
By setting a desired value to the register,
Wait values are inserted into the bus cycle.
And a weight control circuit for a microprocessor. 2. The method according to claim 1, wherein the release of the weight of said central processing unit is performed externally.
Has an external terminal for designating from the external terminal
When the input wait release signal and the counter
One of the signals output at the end of counting
The wait request to the central processing unit is released at the time of
2. The microprocessor according to claim 1, wherein:
Weight control circuit. 3. A central processing unit, and a register capable of setting a value by executing an instruction of the central processing unit.
Controlling a register, a counter, and loading and counting of a value to the counter;
Counter control means and bus cycle of the central processing unit
Requesting means for requesting a wait from the CPU, and externally designating cancellation of the wait of the central processing unit
A microprocessor with an external terminal, a for said counter control means, in said at the beginning a bus cycle
Based on the signal output from the central processing unit,
Control so that the count value is loaded into the counter
In the bus cycle, the wait requesting means
The signal input from the pin to specify wait release and the wait
A signal indicating the state of the counter for counting the number of sites;
Controlling a wait for the central processing unit based on a wait release signal input from the external terminal;
Any of the signals that the counter outputs at the end of counting
When it is active, the way to the central
The request is canceled.
Microprocessor wait control circuit. 4. The register has a maximum wait time upon reset.
Initialized to a value and the weight input from the external terminal
Reset according to the value that indicates the wait release state of the release signal
Not inserted into bus bus cycle / maximum
Number of waits inserted into the bus cycle, is selectively controlled
5. The micro according to claim 4, wherein:
Processor weight control circuit. 5. A central processing and apparatus, and the count value can be set variably counter, each value by executing instruction of the central processing unit can be set
Multiple values that hold weight values for each address range
Register and an address that detects the range of the divided address space.
It includes a scan range detection means, and in each bus cycle, the address range detecting means add
Address signal, one of the address ranges is selected, and the weight value corresponding to the selected address range is
The counter selectively from any one of the number registers
Loaded, and the counter is set for each address range in the bus cycle
The central processing for a period for counting the weight value set in
Configured to request weight from the device
A weight control circuit for a microprocessor. 6. The method according to claim 1, wherein the release of the weight of said central processing unit is performed externally.
Has an external terminal to specify from
The counter in the bus cycle for each address range
Counts the weight value set for each address range
Or the external terminal inputs a signal to the external terminal.
The wait to the central processing unit based on the
6. The control unit according to claim 5, wherein the control unit controls a write request signal.
The weight control circuit of the above microprocessor. 7. A counter whose count value can be set variably.
And the count value of the counter in a bus cycle.
During the period specified in
The microprocessor weight control method to be performed.
Therefore, when the microprocessor is reset, the counter
The maximum count value is set and the maximum number of waits is
And the number of waits in the bus cycle after reset is completed.
Micro, characterized in that it is set variably
Processor weight control method. 8. A counter whose count value can be set variably.
To detect the range of the address space divided into multiple
The number of waits is set in the dress range detecting means and the counter.
And a plurality of registers for setting the address range.
Address signal, one of the address ranges is selected, and the weight value corresponding to the selected address range is
The counter selectively from any one of the number registers
The way is variably set according to the division of the address space to be loaded and accessed.
Control of the microprocessor characterized by performing
Weight control method.