JP2770681B2 - Semiconductor substrate manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly, to a single crystal thin film SOI (Silicon On Ins.
and a method of manufacturing a semiconductor substrate.

[0002]

2. Description of the Related Art Single-crystal thin film SO using a bonding technique
As one of means for manufacturing an I (SOI film thickness: about 0.1 μm) substrate, for example, a method for manufacturing a semiconductor substrate disclosed in Japanese Patent Application Laid-Open No. 1-302837 is known. In the manufacturing method shown here, this step is formed as a history on the surface of the single crystal silicon substrate 11 having the step formed on one surface as shown in FIG. An oxide film 12 is formed, and a polycrystalline silicon layer is formed on the surface of the oxide film 12.
Deposit 13 In this case, the step formed on the surface of the silicon substrate 11 remains as it is on the surface of the polycrystalline silicon layer 13, and the surface of the polycrystalline silicon layer 13 is shown in FIG. By mirror polishing like
The surface is flattened.

When the surface of the polycrystalline silicon layer 13 thus deposited is planarized, another planarized surface of the polycrystalline silicon layer 13 is placed on the planarized surface of the polycrystalline silicon layer 13 as shown in FIG. A crystalline silicon substrate 14 is bonded (the silicon substrate 11 is shown upside down in this figure). Then, the back side of the first single-crystal silicon substrate 11 is selectively polished by using the step of the oxide film 12 as a stopper to obtain a desired SOI substrate as shown in FIG. In such a manufacturing method, the polycrystalline silicon layer 13 merely functions as an intermediate layer for flattening so that a step can be bonded.

If the polycrystalline silicon layer 13 of the semiconductor substrate manufactured as described above is used to control the characteristics of a device formed in a single-crystal thin-film SOI region as a buried electrode, the polycrystalline silicon The layer 13 must also be finely divided into desired areas and insulated.

However, in the case of the embodiment disclosed in the above publication, the thickness of the polycrystalline silicon layer 13 needs to be at least 1 μm or more. That is, as shown in FIG. 5A, the polycrystalline silicon layer 13 deposited by the normal CVD method or the like is
The average grain size of the polycrystal is different in the thickness direction. In particular, in the range 131 of about 0.5 to 1 μm from the surface of the oxide film 12, the crystal grows in a random direction. And very fine particle size. However, in the thicker range 132, the crystals
It is known that the grains grow in a direction substantially perpendicular to the surface of No. 12 and have a large grain size.

For example, a temperature of 610 is obtained by a low pressure CVD method.
In the case of a polycrystalline silicon layer formed at a temperature of 0.degree. C., the average grain size at a thickness from the oxide film surface to 0.5 .mu.m is about 0.1 .mu.m or less. The particle size is about 0.5 μm.

When the polycrystalline silicon layer is polished for flattening, the polishing rate of the polycrystalline silicon layer differs depending on the difference in grain size and the difference in the growth direction.
Polishing rate is lower than the polishing rate in the range 132, and the polished surface from the surface of the polycrystalline silicon layer 13 is in the range 131 and 132.
When it reaches the vicinity of the boundary, a step occurs again, and it becomes impossible to make the film thickness as thin as 1 μm or less on a flat surface.

Therefore, such a polycrystalline silicon layer 13
In order to divide the region, a thick polycrystalline silicon layer having a thickness of 1 μm or more is etched, and the stepped portion is made of an insulating material or a polycrystalline silicon layer so that the step that can be etched does not hinder a photo step or a film forming step in a later step. A step of embedding with crystalline silicon is required.

In addition, the chemical reaction rate of the polycrystalline silicon layer at the time of mirror polishing is higher at the grain boundary portion of the crystal than at the crystal surface, and therefore, along the grain boundary as shown in FIG. As a result, a concave portion 135 is easily formed, and the concave portion 135 becomes an unbonded portion when bonded to each other.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and when a semiconductor substrate is bonded to a surface of polycrystalline silicon, when the semiconductor substrate is bonded to the surface of the polycrystalline silicon, the particle is The difference in diameter can be substantially eliminated, and this polycrystalline silicon layer can be thinned to, for example, 1 μm or less, thereby simplifying the steps required for region division, and providing a thin film SOI substrate with a desired electrode. It is an object of the present invention to provide a method of manufacturing a semiconductor substrate which can be obtained.

[0011]

Means for Solving the Problems Claim 1 according to the present invention.
The method for manufacturing a semiconductor substrate described in
One surface with respect to a specific surface of the semiconductor single crystal substrate.
At least from the first step of the first distance and the first distance
Forming a dielectric layer having a second step at a far second distance
Dielectric layer forming step, and the dielectric layer forming step
On the surfaces of the first and second steps of the dielectric layer thus formed.
And the polycrystalline semiconductor layer forming step of forming a crystalline semiconductor layer, before
A flattening step of flattening the surface of serial polycrystalline semiconductor layer, before
A surface of the polycrystalline semiconductor layer planarized in the planarization step;
Ions are implanted into the surface of the polycrystalline semiconductor layer to make the surface amorphous.
Ion-implanting step, and the polymorphized amorphous state
Mirror forming step of mirror polishing the surface of the crystalline semiconductor layer
The second step on the dielectric by repeating
Semiconductor layer having a surface at a distance from a predetermined value or less
An amorphous semiconductor layer forming step of forming a the one main surface
The mirror-polished main surface of the mirror-polished support substrate,
A bonding step of bonding the amorphous semiconductor layer to the mirror-polished surface
And the semiconductor single crystal substrate joined to the support substrate
Is polished from the opposite surface of the support substrate to a predetermined thickness.
Polishing step. Also,
The method for manufacturing a semiconductor substrate according to claim 2 is a method for manufacturing a semiconductor single crystal.
On one side of the substrate, on a specific side of the semiconductor single crystal substrate
And a first step having at least a first distance and the first step
Dielectric having a second step at a second distance greater than the distance
A dielectric layer forming step of forming a layer, the dielectric layer formed Engineering
Of the first and second steps of the dielectric layer formed in
Polycrystalline silicon layer type forming a polycrystalline silicon layer on the surface
Forming step and flattening the surface of the polycrystalline silicon layer.
A supporting step and the polycrystal planarized in the planarizing step
Ions are implanted into the surface of the silicon layer,
Ion implantation process to make the surface of the
Polishing the surface of the polycrystalline silicon layer
Mirror formation step, by the repeated multiple times, the dielectric
A surface on the body whose distance from the second step is equal to or less than a predetermined value
Amorphous Silicon Layer Forming Amorphous Silicon Layer Having
And a supporting substrate having one main surface mirror-polished.
The mirror polishing main surface and the mirror surface of the amorphous silicon layer
A bonding step of bonding the polished surface, and a bonding step of bonding to the support substrate.
The semiconductor single crystal substrate, the opposite side of the support substrate
A polishing step of polishing from a surface to a predetermined thickness.
It is characterized by. A method for manufacturing a semiconductor substrate according to claim 3.
The method comprises the step of forming an amorphous semiconductor layer according to claim 1,
The distance from the second step is 1 μm or less on the dielectric layer.
The lower amorphous semiconductor layer is formed. Claim 4
2. The method for manufacturing a semiconductor substrate according to claim 1, wherein
Forming the second semiconductor layer on the dielectric layer.
Amorphous half with a distance from the difference of about 5000 Å
It forms a conductor layer . The semiconductor according to claim 5.
3. The method of manufacturing a substrate according to claim 2, wherein the method comprises:
The layer forming step includes the step of forming the second step on the dielectric layer.
It forms an amorphous silicon layer with a distance of 1 μm or less.
is there. The method of manufacturing a semiconductor substrate according to claim 6 is the method according to claim 6.
3. The step of forming an amorphous silicon layer according to item 2,
The distance from the second step is approximately 5000 Å on the layer.
It is for forming an amorphous silicon layer of the tromes. Contract
A method for manufacturing a semiconductor substrate according to claim 7 is a method for manufacturing a semiconductor substrate according to claim 1.
7. The method according to claim 6, wherein the supporting is performed before the joining step.
A polishing method for forming a polished surface dielectric layer on the mirror polished surface of the substrate.
The method is characterized by including a polished surface dielectric layer forming step.
The method of manufacturing a semiconductor substrate according to claim 8 is the method according to claims 1 to
8. Forming in the dielectric layer forming step according to claim 7.
The second step of the dielectric layer is formed by the semiconductor unit.
A second distance substantially parallel to the specific surface of the crystal substrate.
It is characterized by having a flat surface.

[0012]

According to the present invention, there is provided a method for manufacturing a semiconductor substrate.
According to the method, the amorphous portion of the polycrystalline semiconductor layer
No or very few grain boundaries, thus
The polishing rate is made uniform. Further, in the present invention, the amorphous half
When forming the conductor layer, the polycrystalline planarized in the planarization process
Ions are implanted into the surface of the semiconductor layer and the surface of the polycrystalline semiconductor layer is
An ion implantation step of making the surface amorphous, and
Mirror forming step of mirror polishing the surface of said polycrystalline semiconductor layer
The distance between the surface of the amorphous semiconductor layer and the second step is
Repeat a plurality of times until the value falls below a predetermined value. Because of this, always
Uniform ion implantation can be performed, and amorphous
Quality. At the same time, increase the polishing rate in the polishing surface.
Since the uniformity can be achieved, the formed amorphous semiconductor layer is amorphous
The condition is uniform and the surface is sufficiently flat. Yo
Thus, bonding can be performed with almost no unbonded portions. Further substrate
The thickness of the polycrystalline silicon layer that will be embedded inside
It can be as thin as several thousand angstroms.
According to the method for manufacturing a semiconductor substrate according to claim 3, amorphous
The semiconductor layer has a distance of 1 μm from the second step on the dielectric layer.
m or less, and the method of manufacturing a semiconductor substrate according to claim 4.
According to the description, the amorphous semiconductor layer has a second step on the dielectric layer.
Since their distance is about 5000 angstroms,
The thickness of the polycrystalline semiconductor layer that will be embedded in the plate
It can be as thin as several thousand angstroms.
According to the method for manufacturing a semiconductor substrate according to claim 5, amorphous
The silicon layer has a distance of 1 from the second step on the dielectric layer.
7. The method of manufacturing a semiconductor substrate according to claim 6, which is not more than μm.
According to the method, the amorphous silicon layer is formed on the dielectric layer in the second step.
The distance from the difference is about 5000 angstroms
A polycrystalline silicon layer that becomes embedded in the substrate
Film thickness of several thousand angstroms
it can. A method for manufacturing a semiconductor substrate according to claim 7.
For example, before the bonding process, the polishing surface
Form a dielectric layer. This makes it possible to
Mirror polishing with flatness, almost no unjoined parts
Combine. A method for manufacturing a semiconductor substrate according to claim 8.
According to the method, since it is formed in the dielectric layer forming step,
Equalize the thickness of the polycrystalline silicon layer
It can be one, to be sufficiently thin and thousands angstroms thickness
Can be

[0013]

An embodiment of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1A, an oxide film 22 is formed on a mirror surface of a first single crystal silicon substrate 21 having at least one surface mirror-polished by, for example, a LOCOS oxidation method. Causes a step to be formed. Here, the thickness of the thick region 221 of the oxide film 22 is, for example, about 0.6 μm, and the thickness of the thin region 222 is, for example, about 0.05 μm. The height is set to about 0.25 to 0.3 μm.

After the oxide film 22 having the steps is formed in this manner, as shown in FIG. 1B, a surface of the first silicon substrate 21 having the oxide film 22 is formed by, for example, a CVD method. A crystalline silicon layer 23 is deposited to a thickness of about 5 μm. In this case, an oxide film is formed on the surface of the polycrystalline silicon layer 23.
Although there is a step corresponding to the step 22, the surface of the polycrystalline silicon layer 23 is mirror-polished to be flattened as shown in FIG. In this flattened state, the thickness of the polycrystalline silicon layer 23 is
In the thick region 221, for example, the thickness is about 1 μm.

The polycrystalline silicon layer 23 thus planarized
Is formed, for example, boron is applied to the mirror-polished surface of the polycrystalline silicon layer 23 by 200K as shown in FIG.
Ion implantation is performed at a high concentration of “1 × 10 ¹⁶ cm ⁻² ” at eV. By performing the ion implantation in this manner, the area of about 0.6 μm in the surface portion of the polycrystalline silicon layer 23 becomes amorphous due to the damage of the ion implantation, and the amorphous silicon layer 231 is formed.
Is formed.

The amorphous silicon layer 231 on the surface of the polycrystalline silicon layer 23 is mirror-polished from its surface as shown in FIG. At this time,
The thickness of the composite layer of the polycrystalline silicon layer 23 and the amorphous silicon layer 231 is, for example, 500 in the thick region 221 of the oxide film 22.
The surface is thinned to about 0 angstroms and has a flat surface state to enable bonding.

If it is desired to further reduce the thickness of the composite layer of the polycrystalline silicon layer 23 and the amorphous silicon layer 231, the steps shown in FIGS. 1A and 1B may be repeated. Here, the ions to be implanted for amorphization can be made amorphous as much as possible by one ion implantation, and the resistance can be reduced in order to use the polycrystalline silicon layer 23 as an electrode later. Although boron is selected from the necessity, for example, phosphorus, arsenic, antimony or the like may be implanted. If the polycrystalline silicon layer 23 has already been doped with impurities and has a low resistance, or if there is no need to reduce the resistance, silicon may be implanted.

When the amorphous silicon layer 231 is formed on the surface of the polycrystalline silicon layer 23, the surface is oxidized to a thickness of about 0.1 μm as shown in FIG. Membrane 24
A second single-crystal silicon substrate 25 on which is formed is prepared.
The surface of the oxide film 24 of the silicon substrate 25 is mirror-polished, and a first single-crystal silicon substrate
The mirror-polished surface of the amorphous silicon layer 231 formed on the substrate 21 is bonded (in this figure, the first silicon substrate 21 is inverted). Then, the two substrates are joined and integrated by a heat treatment at 600 ° C. or higher.

In general, bonding a polycrystalline silicon and a single-crystal silicon substrate requires a high-temperature heat treatment at a temperature of 1000 ° C. or higher. It has been found that perfect bonding can be performed even at a relatively low temperature of about 600 ° C. (described in 28P-X-3 of the proceedings of the Joint Conference on Applied Physics in the Spring of 1991).

By performing such a low-temperature heat treatment, it is possible to prevent impurities of the polycrystalline silicon layer 23 from diffusing into the first single crystal silicon substrate 21 via the oxide film 24. Further, the amorphous silicon layer 231 is recrystallized by this heat treatment, and becomes a part of the polycrystalline silicon layer 23.

Next, as shown in FIG. 3A, selective polishing is performed from the back surface side of the first single crystal silicon substrate 21, and the thick region 221 of the oxide film 22 of the silicon substrate 21 is exposed. This polishing is performed until a thin region 222 of the oxide film 22 is formed.
The SOI region 26 of a single crystal thin film is formed on the substrate. At this time, the thickness of the single crystal thin film SOI region 26 is set to about 0.25 to 0.3 μm corresponding to the thickness of the step 223 of the oxide film 22 formed in the LOCOS oxidation step.

After the single crystal thin film SOI region 26 is formed in this manner, a part of the thick region 221 of the oxide film 22 is etched 27 as shown in FIG. Etching 27 leaving 23 about 0.1 μm,
The SOI region 26 and the polycrystalline silicon layer 23 are divided into desired regions.

Finally, as shown in FIG. 3C, the thickness of the thin film SOI region 26 is adjusted to a desired thickness of, for example, about 0.1 μm by thermal oxidation, Due to the oxidation, the surface of the polycrystalline silicon layer 23 that is exposed on the surface during the region division is oxidized and turned into an oxide film 28. Then, the polycrystalline silicon layer 23 is insulated and separated into a desired region. Note that when the surface of the polycrystalline silicon layer 23 is oxidized and changed to an oxide film 28,
The height of the step formed when dividing the area due to volume expansion is 1μ
m or less, the step of embedding this step is not required.

[0024]

As described above, according to the method of manufacturing a semiconductor substrate according to the present invention, the polycrystalline silicon layer serving as the intermediate layer can be made sufficiently thin and can be bonded at a low temperature. Therefore, it is possible to suppress the substrate from being curved due to the difference in thermal expansion coefficient between polycrystalline silicon and single-crystal silicon, and to effectively reduce the stress applied to the thin-film SOI layer. Variations in characteristics can be reliably suppressed, and device characteristics can be stabilized. Further, since the embedded electrode is formed below the SOI region, the controllability of the characteristics of the device formed in the SOI portion is also improved.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views for sequentially explaining manufacturing steps of a semiconductor device according to an embodiment of the present invention.

2 (A) to 2 (C) are cross-sectional views for sequentially explaining manufacturing steps subsequent to FIG. 1 (C).

3 (A) to 3 (C) are cross-sectional views for sequentially explaining manufacturing steps subsequent to FIG. 2 (C).

FIGS. 4A to 4D are cross-sectional views sequentially illustrating a conventional manufacturing process.

FIG. 5A is a cross-sectional view illustrating a polycrystalline silicon layer according to the conventional manufacturing method, and FIG. 5B is an enlarged view of the silicon layer.

[Explanation of symbols]

21: first single-crystal silicon substrate, 22: oxide film, 221: thick region, 222: thin region, 223: step, 24: oxide film, 25
.., A second single-crystal silicon substrate, 26, a single-crystal thin-film SOI region, 27, etching, and 28, an oxide film.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-62252 (JP, A) JP-A-1-305534 (JP, A) JP-A-3-265153 (JP, A) JP-A-4- 64249 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) H01L 21/76-21/765 H01L 21/304

Claims (8)

(57) [Claims] 1. A on one surface of the semiconductor single crystal substrate, said half
At least a first distance with respect to a specific surface of the conductor single crystal substrate
Of the first step and the second distance farther than the first distance
A dielectric layer forming step of forming a dielectric layer having a second step; and a step of forming the dielectric layer by the dielectric layer formed in the dielectric layer forming step.
First, multi forming a polycrystalline semiconductor layer on the surface of the second step
A crystalline semiconductor layer forming step, the polycrystalline and flattening step of flattening the surface of the semiconductor layer, the ions implanted into flattened surface of the polycrystalline semiconductor layer in the planarization step, the polycrystalline semiconductor layer Amorphous surface
Ion-implantation step for the
A mirror forming step of mirror polishing the surface of the crystalline semiconductor layer.
By repeating several times, the second step is formed on the dielectric.
Amorphous semiconductor having a surface whose distance from the difference is equal to or less than a predetermined value
An amorphous semiconductor layer forming step of forming a layer; and a bonding step of bonding the mirror-polished main surface of the support substrate having one main surface mirror-polished to the mirror-polished surface of the amorphous semiconductor layer. A polishing step of polishing the semiconductor single crystal substrate bonded to the support substrate to a predetermined thickness from a surface on the opposite side of the support substrate. (2)One side of the semiconductor single crystal substrate
At least a first distance with respect to a specific surface of the conductor single crystal substrate
Of the first step and the second distance farther than the first distance
Forming a dielectric layer having a second step
Process and The dielectric layer formed in the dielectric layer forming step
Forming a polycrystalline silicon layer on the surfaces of the first and second steps;
Forming a polycrystalline silicon layer, Flattening step for flattening the surface of the polycrystalline silicon layer
When, Of the polycrystalline silicon layer flattened in the flattening step
Ions are implanted into the surface to clean the surface of the polycrystalline silicon layer.
Amorphous ion implantation step and before amorphization
Mirror polishing for polishing the surface of the polycrystalline silicon layer
By repeating a plurality of times, the above-mentioned
Amorphous having a surface whose distance from the second step is equal to or less than a predetermined value
Forming an amorphous silicon layer to form a porous silicon layer; Mirror polishing of a supporting substrate having one main surface mirror-polished
The main surface and the amorphous The mirror-polished surface of the silicon layer
A joining process of joining, The semiconductor single crystal substrate bonded to the support substrate,
Polishing to a predetermined thickness from the opposite surface of the supporting substrate.
And a polishing process. How to manufacture semiconductor substrates
Law. 3. The method according to claim 1 , wherein the step of forming the amorphous semiconductor layer comprises the step of:
The distance from the second step is 1 μm or less on the conductor layer.
2. The method for manufacturing a semiconductor substrate according to claim 1 , wherein the method comprises forming a crystalline semiconductor layer . 4. The method according to claim 1 , wherein the step of forming the amorphous semiconductor layer comprises the step of:
The distance from the second step is approximately 5,000 on the conductor layer
A spheroidal amorphous semiconductor layer.
The method for manufacturing a semiconductor substrate according to claim 1 . 5. An amorphous silicon layer forming step,
The distance from the second step is 1 μm or less on the dielectric layer.
3. The method according to claim 2 , wherein an amorphous silicon layer is formed . 6. An amorphous silicon layer forming step,
The distance from the second step is approximately 5,000 on the dielectric layer.
Forming an amorphous silicon layer.
A method for manufacturing a semiconductor substrate according to claim 2 . 7. The method according to claim 1 , further comprising:
Polishing surface dielectric to form a polishing surface dielectric layer on the mirror polishing surface
4. The method according to claim 1, further comprising a body layer forming step.
The method for manufacturing a semiconductor substrate according to claim 6 . 8. The method according to claim 1, wherein the step of forming the dielectric layer comprises the step of:
The second step of the dielectric layer is formed on the semiconductor single crystal substrate.
A plane substantially parallel to the specific plane and at a second distance
The method according to any one of claims 1 to 7, wherein
Of manufacturing the semiconductor substrate described above.