JP2767518B2 - AFC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic frequency control (AFC) system for receiving a base station frequency used in a mobile station for digital communication and following the frequency to stabilize the frequency.
control) circuit.

[0002]

2. Description of the Related Art In general, a receiver of a mobile station uses a superheterodyne receiver and includes a local oscillator for converting a frequency from a reception frequency to an intermediate frequency. The local oscillator includes, for example, a reference oscillator such as a voltage control-temperature compensation crystal oscillator (hereinafter abbreviated as VC-TCXO) and a means (a multiplier circuit, a PLL synthesizer, etc.) for converting an oscillation frequency from the reference oscillator to an intermediate frequency. If the oscillation frequency of the local oscillator includes a deviation, the intermediate frequency deviates from a predetermined value, accurate demodulation cannot be performed, and the transmission frequency also deviates. Therefore, in order to stabilize the intermediate frequency following the reception frequency, it is necessary to remove a deviation from the oscillation frequency of the local oscillator. For this reason, an AFC circuit is inserted to correct the deviation of the oscillation frequency of the local oscillator.

FIG. 3 is a block diagram showing an example of the configuration of a double superheterodyne receiver provided with the above-mentioned AFC circuit. In FIG. 3, reference numeral 1 denotes a receiving antenna, reference numerals 2 and 3 denote mixers, reference numeral 4 denotes an amplifier, and reference numeral 5 denotes an amplifier. A sign determination circuit, 6 is a PLL synthesizer as a first local oscillator, 7 is an N frequency multiplier as a second local oscillator, 8 is a PLL synthesizer, 9 is a mixer, 10 is an amplifier, 11 is a transmitting antenna, and 20 is an AFC circuit. Show.

[0004] The mixer 2 is input first local oscillation frequency F _L1 from the PLL synthesizer 6, the mixer 3 second local oscillation frequency F _L2 from N multiplying circuit 7 is input, the input from the receiving antenna 1 signal F _R is converted into a first intermediate frequency F _IF1 via the mixer 2, a through mixer 3 2
The signal is converted into the intermediate frequency F _IF2 , amplified by the amplifier 4, input to the sign determination circuit 5, and subjected to sign judgment to obtain a demodulated output. In transmission, the transmission intermediate frequency F _IFT from the PLL synthesizer 8 is mixed with the output from the PLL synthesizer 6 by the mixer 9 and the output signal F _T is output from the transmission antenna 11.

Next, the AFC circuit 20 will be described. A
The FC circuit 20 includes a counter 21, an operation unit 22, a ROM 2,
3, D / A converter 24 is composed of a VC-TCXO25, intermediate frequency F by following the reception frequency F _R
IF1, F _IF2, F _IFT an order to stabilize, control is performed to correct the deviation of the oscillation frequency of the local oscillator. Hereinafter, this will be described.

If the deviation α is superimposed on the output f ₀ from the AFC circuit 20, the output of the PLL synthesizer 6 is FL ₁ (1 + α), and the output of the N multiplier 7 is _{FL 2} (1+
α), the output of PLL synthesizer 8 is F _IFT (1 + α)
Becomes Then, the first intermediate frequency including the deviation is represented by F ′
_IF1, 'if indicated by the _IF2, F' also the second intermediate frequency _{F IF1 = F L1 (1 +} α) -F R F = 'IF2 = F L2 (1 + α) -F' IF1 F L2 (1 + α) -F L1 ( 1 + α) + F _R = α (F _L2 −F _L1 ) + F _L2 −F _L1 + F _R Substituting _{F IF1 = F L1 -F R F} IF2 = F L2 -F IF1 = F L2 -F L1 + F R after expression, F _'IF2 = α expressed as _{(F IF2 -F R) + F} IF2. 'If during the gate time the _{IF2 G T = n / f 0} (1 + α) (n is the frequency division number) for counting, the count value D _A is, D _A = F' the intermediate frequency F _IF2 × G _T = {α (F _IF2 −F _R ) + F _IF2 ｝ × {n / f ₀ (1 + α)} = {F _IF2 (1 + α) −αF _R ｝ × {n / f ₀ (1 + α)} = n / f ₀ · (F _IF2 ) −αn / f ₀ (1 + α). Therefore, if brought closer the count value D _A to _{n / f 0 · (F IF2} ), you can control the oscillation frequency so that the deviation alpha also alpha → 0, and the deviation alpha · f ₀ eliminated.

That is, in the AFC circuit 20, the output frequency from the amplifier 4 is converted by the counter 21 into the VC-TCXO 2
The output frequency of 5 counts between the gate time that has n dividing, by the arithmetic unit 22 takes in the count value D _A, based on the content of _{ROM23, D B = a · {} n / f 0 · (F IF2) -D
Performs calculation of _A}, and outputs the correction data D _B. By the way, when the feedback control is not performed, D _B = a
- the D _A. Data D _B corrected by the feedback control is converted into a DC voltage of Anaroku by the D / A converter 24, is input to the VC-TCXO25, VC-
The oscillation frequency f _{0 of the} TCXO 25 is controlled. And V
The oscillation output of the C-TCXO 25 is the PLL synthesizer 6
And 8, are supplied to the N multiplying circuit 7.

As described above, the control is performed such that the deviation α · f ₀ of the oscillation frequency of the VC-TCXO 25 becomes 0, the tracking of the reception frequency F _R is ensured, and the reception of the transmission frequency F _T is further performed. Tracking to the frequency F _R (in the case of mobile radio, the transmission frequency of the base station) is ensured. Also, the oscillation frequency of each local oscillator is set to one reference oscillator VC-TCXO2
5 is used as a reference, so that the configuration is relatively simple.

[0009]

SUMMARY OF THE INVENTION The above conventional A
The FC circuit is configured and operates as described above. However, when fading in which the input level temporally decreases occurs when the reception input level is low, the input of the counter 21 when the input level is low is reduced by the natural noise. A completely random frequency results in an error in the count value of the counter 21, making it difficult to accurately control the oscillation frequency. Further, since the output from the amplifier 4 is not a rectangular wave but an analog signal, a conventional A
In the case of the FC circuit, there is a problem that the counter 21 may malfunction.

A significant problem arises, for example, when applied to US-specification digital cellular. That is, according to this specification, the frequency deviation allowed on the mobile station side while following the base station is a small value of ± 200 Hz (± 0.25 ppm because the RF frequency is in the 800 MHz band), and within 130 msec during handoff. Transmission must be started by pulling in the frequency of the VC-TCXO 25 within this frequency deviation, and the counting time in the counter 21 is very short. Therefore, for example, if the counting time of the intermediate frequency is 100 msec, one counting error becomes 10 Hz in the deviation of the oscillation frequency, and if there are more than 20 errors, the tolerance of ± 200 Hz cannot be satisfied. AFC circuit cannot be applied. The present invention has been made to solve the above problems.

[0011]

An AFC circuit according to the present invention comprises a comparator, a clock oscillator, and a logic circuit. The AFC circuit shapes an input intermediate frequency signal and detects a weak electric field of a received signal. Provided an intermediate frequency protection circuit that outputs a clock synchronized with the intermediate frequency and outputs a clock that self-oscillates only when the electric field is weak, and the output frequency of the intermediate frequency protection circuit is counted by a counter.

[0012]

According to the present invention, when a fading in which the input signal level temporally drops occurs, the comparator detects the fading and outputs a self-oscillated clock by the clock oscillator. However, counting of a completely random frequency of natural noise can be prevented, and accurate control of the oscillation frequency can be performed. Further, since the waveform of the input intermediate frequency signal is shaped by the comparator, malfunction of the digital circuit can be prevented.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 3 indicate the same or corresponding parts, and 26 indicates an intermediate frequency protection circuit. The intermediate frequency protection circuit 26 is composed of a comparator having hysteresis, a clock oscillator, and a logic circuit. The input intermediate frequency signal is shaped by a comparator, and the received signal is weakened by using the hysteresis of the comparator. Detects electric field. Then, normally, it operates so as to output a clock synchronized with the intermediate frequency and to output a clock that is self-oscillated only when the electric field is weak.

FIG. 2 is a waveform diagram for explaining the operation of the above-mentioned intermediate frequency protection circuit 26. When a fading in which the input level temporally decreases occurs when the received input level is low near the sensitivity, the input level becomes low. When the level drops, the output of the amplifier 4 has a level falling and a completely random frequency of natural noise as shown in FIG. When the waveform of this signal is shaped by a comparator with hysteresis, the waveform in the weak electric field has a small amplitude.
To become fence, is removed by this hysteresis, the output ing as in FIG. (B). That is, the reception input level
Becomes higher than a predetermined high level, the output of the comparator becomes H
Level and the received input level drops to a predetermined low level.
When the level falls below the level, the output of the comparator changes to L level.
To, removed completely random frequency during fading when fading is fixed to L level (or H-level).

The logic circuit in the intermediate frequency protection circuit 26 is
As shown in FIG. 3C, a clock pulse from a clock oscillator is normally output in synchronization with the rising edge of the output of the comparator. If the rising edge of the output of the comparator does not come within a predetermined time, the clock pulse is output at a frequency close to the intermediate frequency. A clock pulse of the oscillating clock oscillator is output to prevent missing pulses during fading. The output from the intermediate frequency protection circuit 26 is input to the counter 21 and the counter 2
Since 1 counts this output, it is possible to prevent a situation in which a completely random frequency is counted during fading, to eliminate the influence of fading, and to more accurately control the oscillation frequency of the VC-TCXO 25. Further, since the circuit configuration is simple and suitable for a mobile station, the size and simplification of the mobile station can be realized. further,
Since the output of the amplifier 4 is shaped into a rectangular wave by the comparator, no malfunction occurs even when this signal is input to the digital circuit.

[0016]

As described above, according to the present invention, when fading in which the input level falls with time, this is detected by the comparator and self-oscillated by the clock oscillator, so that even when fading occurs, natural noise is reduced. A situation in which a completely random frequency is counted can be prevented, and accurate control of the oscillation frequency can be performed. Further, since the waveform of the input intermediate frequency signal is shaped by the comparator, there is an effect that a malfunction of the digital circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a waveform chart showing an operation of the protection circuit shown in FIG.

FIG. 3 is a block diagram showing a conventional AFC circuit.

[Explanation of symbols]

 Reference Signs List 20 AFC circuit 21 Counter 22 Operation unit 23 ROM 24 D / A converter 25 VC-TCXO 26 Intermediate frequency protection circuit

Continuation of the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H03J 7/00-7/32 H03D 7/00

Claims (1)

(57) [Claims] 1. A feedback control circuit for inputting an intermediate frequency and controlling a local oscillator for stabilizing the intermediate frequency by following a reception frequency, which is used in a mobile station for digital communication. An AFC (automatic frequency controller) that has a control oscillator, counts intermediate frequencies with a counter, sequentially performs arithmetic processing in an arithmetic unit based on the count value, and controls the voltage-controlled oscillator while updating the arithmetic value.
ol) The circuit consists of a comparator with hysteresis, a clock oscillator and a logic circuit. The input intermediate frequency signal is shaped and the hysteresis of this comparator is used.
An intermediate frequency protection circuit that detects the weak electric field of the received signal and outputs a clock synchronized with the intermediate frequency and outputs a clock that self-oscillates only when the electric field is weak, and counts the output of this intermediate frequency protection circuit with a counter. Means for controlling the voltage-controlled oscillator while updating the operation value by performing an operation process sequentially in the operation unit based on the counted value.