JP2763118B2 - Loop communication system - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial application field) The present invention relates to a loop communication system.

(Prior art) With the progress of the information society, multiple information systems (bureaus)
Have been developed, for example, as a process control network system, an OA network system, and a factory automation network system, for realizing higher-level information processing by interconnecting the two via a data transmission path.

By the way, in recent years, there has been a demand for the development of a large-scale and advanced network that can integrate or combine various independently existing networks and perform more advanced information processing.

FIG. 2 shows an example of a loop communication system which has been receiving attention in recent years in response to such a demand.

The loop communication system shown in FIG. 1 is a system in which a control station 1 and stations 2, 3, and 4 are connected in a loop by a transmission path 5, and a frame is circulated on the transmission path 5 to perform communication between the stations. .

 FIG. 3 is a diagram showing the configuration of the above-described frame.

The frame shown in the figure has a time length of 125 μs per frame, and includes a frame header (FH) 6, a circuit switching area (CX) 9, and a packet switching area (PX) 10 configured with a unique pattern for frame synchronization. , A control area (CONT) 8 for storing connection information and maintenance operation information, and a boundary display value area (IV) 7 indicating a boundary between the circuit switching area (CX) 9 and the packet switching area (PX) 10. Further, data in a frame is constituted by a unit called a time slot, and a coding method such as an mB1C code (for example, an 8B1C code) or an mBnB code (for example, a 4B5B code) is used.

FIG. 4 is a block diagram showing the configuration of the stations 2, 3, and 4 described above.

The station shown in the figure includes an encoding circuit 11, a reception counter 12, a frame header detection circuit 13, a data processing unit 19, a transmission timing generation circuit 14, an encoding circuit 15, a frame header generation circuit 16, a selector 17, a waveform shaping circuit. Consists of 18.

The data received from the transmission path 5 is restored to the original data by the decoding circuit 11 and transmitted to the data processing unit 19 together with the control bits.

Here, the control bit is a bit released to a terminal connected to the station, and is used for controlling connection between terminals and for accommodating asynchronous terminals having different transmission speeds. The reception counter 12 counts the number of reception clocks and generates a reception timing. Further, the reception counter 12 is initialized when the frame header detection circuit 13 detects a frame header.

The data processing unit 19 analyzes the transmitted data, and if the data is addressed to the own station, captures the data. Otherwise, the data is directly transmitted to the encoding circuit 15 together with the control bits. If there is data to be transmitted, the data is inserted into the frame and transmitted to the encoding circuit 15 together with the control bits.

 The encoding circuit 15 encodes the transmitted data.

The data encoded in this manner is combined with the frame header generated from the frame header generation circuit 16 in accordance with the timing of the transmission timing generation circuit 14, and sent to the waveform shaping circuit 18.

The data combined with the frame header is retimed by the waveform shaping circuit 18 and sent out to the transmission line 5 together with the clock.

By the way, in such a communication system, a decoding circuit
Reference numeral 11 denotes a hardware configuration for separating received data transmitted from the transmission path 5 into data bits and control bits, and a coding circuit 15 for combining the data bits transmitted from the data processing unit 19 with the control bits. Because of the hardware configuration, the circuit switching area 9 and the packet switching area 10 need to adopt the same coding scheme, that is, a coding scheme including control bits.

However, in the packet switching area 10, since control bits are added to each time slot although control bits are unnecessary, the transmission efficiency in the packet switching area is low.

(Problems to be Solved by the Invention) As described above, in the above-described loop communication system, by adding a control bit to each time slot, connection control between terminals and accommodation of asynchronous terminals having different transmission speeds are possible. However, when the frame includes the circuit switching area and the packet switching area, unnecessary control bits are added in the packet switching area, so that the transmission efficiency is reduced.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a loop communication system capable of efficiently performing data transmission.

[Structure of the Invention] (Means for Solving the Problems) A loop communication system according to the present invention according to claim 1, wherein a plurality of stations including a control station are connected in a loop via a transmission path,
In a loop communication system in which a frame including a circuit switching area and a packet switching area circulates on the transmission path and performs communication between the stations, a coding scheme of the circuit switching area and a coding scheme of the packet switching area are different. Each station includes an encoding / decoding circuit corresponding to the coding system in the circuit switching area, and an encoding / decoding circuit corresponding to the coding system in the packet switching area. -The above-mentioned problem is solved by switching and using the decoding circuit.

The loop communication system of the present invention according to claim 2 connects a plurality of stations including a control station in a loop via a transmission path,
In a loop communication system in which a frame including a circuit switching area and a packet switching area circulates in the transmission path and performs communication between the stations, a coding scheme of the circuit switching area and a coding scheme of the packet switching area are different, and A control bit is added only to the circuit-switched area, and each of the stations performs an encoding /
By providing a decoding circuit and an encoding / decoding circuit corresponding to the encoding method of the packet switching area, and switching and using these encoding / decoding circuits according to the encoding method, the above-described problem is solved. Solved.

(Operation) In the present invention, since different coding methods can be supported, the coding method of the circuit switching area and the coding method of the packet switching area are different, and control bits may be added only to the circuit switching area. That is, since it is not necessary to add a control bit to the packet switching area, data transmission can be performed efficiently.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

The loop communication system according to this embodiment is the same as that shown in FIG. That is, in the loop communication system, the control station 1 and the stations 2, 3, and 4 are connected in a loop by the transmission path 5, and the transmission path 5 circulates a frame to perform communication between the stations.

The structure of the frame is the same as that shown in FIG. That is, this frame is 125
It has a time length of μs, and includes a frame header (FH) 6, a circuit switching area (CX) 9, a packet switching area (PX) 10, a connection information and a maintenance operation information, which are composed of a unique pattern for frame synchronization. It comprises a control area (CONT) 8 and a boundary display value area (IV) 7 indicating a boundary between the circuit switching area (CX) 9 and the packet switching area (PX) 10.

The data in the frame is composed of units called time slots, and the coding scheme is a control area (CO
9B1C code (8B1C +
4B5B code used in FFDI or the like is used for the control bit) and the packet switching area (PX) 10.

FIG. 1 is a block diagram showing the configuration of the stations 2, 3, and 4 according to this embodiment.

The station shown in FIG. 1 includes a receiving unit 21 for receiving data transmitted from the transmission line 5, a transmission unit 22 for transmitting data transmitted from a terminal or the like connected to the station to the transmission line 5, A timing signal generating section 23 for providing a predetermined timing signal to the section 21 and the transmitting section 22;
The main part is constituted by 22 and a data processing unit 24 serving as an interface with a terminal or the like connected to this station.

The receiving unit 21 includes a 5B / 4B decoding circuit 25 and a 9B1C decoding circuit 2.
6. It has a selector 27.

The 5B / 4B decoding circuit 25 transmits the 5B (5
) is converted into 4B (4 bit) data based on a reception clock transmitted (extracted) from the transmission line 5. The 9B1C decoding circuit 26 receives the 9B
The control bits are separated from the received data of 1C based on the received clock transmitted (extracted) from the transmission line 5. The selector 27 converts the received data to be transmitted to the data
Switching is made between the data transmitted from the / 4B decoding circuit 25 and the data transmitted from the 9B1C decoding circuit 26.
When the selector 27 uses the data transmitted from the 9B1C decoding circuit 26 as reception data to be transmitted to the data processing unit 24, the selector 27 also transmits the separated control bit data to the data processing unit 24.

The transmitting unit 22 includes a 9B1C encoding circuit 28 and a 4B / 5B encoding circuit 2.
9. A frame header (FH) generating circuit 30, a selector 31, and a waveform shaping circuit 32 are provided.

The 9B1C encoding circuit 28 is transmitted from the data processing unit 24.
9B1C combines the transmission data of 8B1C and the data of control bits.
To the transmission data. The 4B / 5B encoding circuit 29 converts 4B transmission data transmitted from the data processing unit 24 into 5B data. The frame header (FH) generating circuit 30 generates a frame header (FH) 6 (see FIG. 3) added to the head of the frame of the transmission data. The selector 31 switches the transmission data to be transmitted to the transmission line 5 between the data transmitted from the 9B1C encoding circuit 28 and the data transmitted from the 4B / 5B encoding circuit 29. The waveform shaping circuit 32
The transmission data transmitted from the selector 31 is retimed based on the reception clock transmitted (extracted) from the transmission line 5 and transmitted to the transmission line 5.

The timing signal generator 23 includes a decimal counter 33, a frame header (FH) detection circuit 34, a slot counter 35, a boundary display value area (IV) detection circuit 36, a transmission timing generation circuit
37 is provided.

The decimal counter 33 counts a reception clock and generates a reception timing signal. The frame header (FH) detection circuit 34 generates a frame header detection signal when detecting a frame header from a frame constituting the received data. The slot counter 35 counts the number of received bytes and, when counting the number of bytes corresponding to the boundary display value area (IV) 7, generates an IV value detection signal. In addition, decimal counter
33 and slot counter 35 are frame headers (FH)
The initialization is performed when a frame header detection signal is received from the detection circuit 34. When receiving the IV value detection signal from the slot counter 35, the boundary display value area (IV) detection circuit 36 fetches the received data, that is, the IV value at this timing, and controls switching by the above-described selector 27 according to the IV value. The transmission timing generating circuit 37 controls switching by the above-described selector 31 according to the timing on the receiving side and the IV value.

 Next, the operation of the station configured as described above will be described.

 First, the operation of the receiving unit 21 will be described.

The received data transmitted from the transmission path 5 is input to a 5B / 4B decoding circuit 25 and a 9B1C decoding circuit 26, where the data is converted.

By switching of the selector 27 controlled by the boundary display value area (IV) detection circuit 36, the 9B1C decoding circuit 26 up to the circuit exchange area (CX) 9 in the frame shown in FIG.
The received data and control bit data transmitted from the circuit switching area (CX) 9 are input to the data processing section 24, and the received data transmitted from the 4B / 5B decoding circuit 25 are input to the data processing section 24 from the circuit switching area (CX) 9. Is done.

The data processing unit 19 takes in the received data addressed to the own station, and otherwise sends it to the transmitting unit 22 as it is.

 Next, the operation of the transmitting section 22 will be described.

The transmission data transmitted from the data processing unit 24 is input to the 9B1C encoding circuit 28 and the 4B / 5B encoding circuit 29, where the data is converted.

By the switching of the selector 31 controlled by the transmission timing generation circuit 37, the transmission data transmitted from the 9B1C encoding circuit 28 is transmitted to the waveform shaping circuit 32 until the circuit switching area (CX) 9 in the frame shown in FIG. The transmission data transmitted by the 4B / 5B encoding circuit 29 is transmitted to the transmission line 5 through the waveform shaping circuit 32 from the circuit switching area (CX) 9.

As described above, in the communication system of this embodiment, the station has a hardware configuration corresponding to a frame having a different coding scheme, and switches according to the coding scheme of the frame. Even if codes and 4B5B codes coexist, this can be handled. For this reason, only the packet switching area 10 that does not require control bits can be set to the coding method using the 4B5B code, and efficient data transmission using the packet switching area is realized.

[Effects of the Invention] As described above, according to the present invention, a frame has regions with different coding schemes, and each station includes an encoding / decoding circuit corresponding to these different coding schemes. Since these encoding / decoding circuits are switched and used accordingly, efficient data transmission can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a station in a loop communication system according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of a loop communication system, FIG.
FIG. 4 is a diagram showing a configuration of a station in a conventional loop communication system. 1 control station 2, 3, 4 ... station 2, 3, 4, 5 ... transmission line, 9 ... circuit switching area (CX), 10 ... packet switching area (PX), 21 ... reception , 22 ... Transmitter, 23 ... Timing signal generator, 24 ... Data processor, 25 ... 5B / 4B
Decoding circuit, 26 ... 9B1C decoding circuit, 27 ... Selector,
28… 9B1C encoding circuit, 29… 4B / 5B encoding circuit, 30…
... Frame header (FH) generation circuit, 31 ... Selector, 32
…… Waveform shaping circuit, 33… Decimal counter, 34 …… Frame header (FH) detection circuit, 35 …… Slot counter, 36
...... Boundary display value area (IV) detection circuit, 37 ... Transmission timing generation circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-199541 (JP, A) JP-A-63-155831 (JP, A) JP-A-62-290239 (JP, A) JP-A-62-1990 262542 (JP, A) JP-A-62-88457 (JP, A) JP-A-60-84048 (JP, A) Technical report of IEICE (Technical Report of IEICE) SSE91-122, Vol. 91, No. 387, Tomio Kunikyo, et al. "400 Mbit / s Multimedia trunk LAN", PP. 55-60, December 18, 1991 (58) Fields investigated (Int. Cl. ⁶ , DB name) H04L 12/42-12/437 H04L 1/00 H04L 1/08-1/24 JICST file ( JOIS) WPI (DIALOG)

Claims (2)

(57) [Claims] 1. A loop communication in which a plurality of stations including a control station are connected in a loop via a transmission path, and a frame including a circuit switching area and a packet switching area is circulated on the transmission path to perform communication between the stations. In the system, a coding method of the circuit switching area and a coding method of the packet switching area are different, and each station has an encoding / decoding circuit corresponding to the coding method of the circuit switching area; and a code of the packet switching area. A loop-type communication system, comprising: an encoding / decoding circuit corresponding to a coding system, wherein said coding / decoding circuit is switched and used according to the coding system. 2. A loop communication in which a plurality of stations including a control station are connected in a loop via a transmission path, and a frame including a circuit switching area and a packet switching area is circulated on the transmission path to perform communication between the stations. In the system, the coding scheme of the circuit switching area and the coding scheme of the packet switching area are different, and a control bit is added only to the circuit switching area, and each of the stations has a code corresponding to the coding scheme of the circuit switching area. Encoding / decoding circuit, and an encoding / decoding circuit corresponding to the encoding system of the packet switching area, wherein the encoding / decoding circuit is switched and used according to the encoding system. Loop communication system.