JP2762441B2 - Coprocessor - Google Patents

Description

The present invention relates to a coprocessor tightly coupled to a CPU,
In particular, the present invention relates to a coprocessor in which the transfer method of operand data is improved to improve the efficiency of execution processing. [Prior Art] In order to improve the instruction processing capability of a CPU in an information processing device, a processing device different from the CPU is tightly coupled with the CPU.
There may be a configuration in which a part of the processing that should be performed by the CPU is taken over. This other processing device is called a co-processor (Co-processor), which improves the processing speed of instructions of the CPU and performs instruction processing (for example, floating-point arithmetic or the like) that cannot be processed by the CPU. To do. Since the coprocessor is used only for CPU expansion, the operation of the coprocessor is not controlled by software. That is, the transfer of data for operation and the transfer of commands for operation are not controlled by software like an input / output (I / O) device.
When the CPU detects an instruction that requires a coprocessor, data transfer is performed only between the CPU and the coprocessor. FIG. 5 is a block diagram showing an information processing apparatus using a conventional coprocessor of this type for performing a floating-point operation. The CPU 1, the memory 2, and the coprocessor 3 are connected via a shared data bus 4, and data transfer is performed between the CPU 1 and the memory 2 and between the CPU 1 and the coprocessor 3. The bus control circuit 5 interprets information STATUS relating to data transfer input from the CUP 1 and generates a read / write signal MSTB for the memory 2 and a read / write signal CPSTB for the coprocessor 3. When detecting that the CPU 1 executes the floating-point operation instruction, the CPU 1 reads the floating-point data in the memory 2 via the shared data bus 4 into the CPU 1 as operand data. Next, the CPU 1 transfers the command to the coprocessor 3 via the shared data bus 4, specifies the operation, and specifies the start of the operation. Then, the operand data read into the CPU 1 is transferred to the coprocessor 3, and the coprocessor 3 starts the operation of the operand data. When the operation of the coprocessor 3 is completed, the operation result is transferred from the coprocessor 3 to the CPU 1, and then the CPU 1 writes the result in the memory 2. When the CPU 1 outputs the STATUS signal, the bus control circuit 5 detects this STATUS signal and recognizes that the operand data to be transferred to the coprocessor 3 is read from the memory 2 to the CPU 1. Therefore, the bus control circuit 5 sends the memory 2
, And the write / read signal CPSTB for the coprocessor 3 are simultaneously generated, so that the operand data can be directly transferred from the memory 2 to the coprocessor 3 without passing through the CPU 1. FIG. 6 is a block diagram specifically showing the configuration of the conventional coprocessor 3. As shown in FIG. The shared data bus 4 is connected to the instruction register 6 and the operand buffer 8. The command transferred from the CPU 1 to the instruction decode unit 7 via the shared data bus 4 and the instruction register 6 is analyzed in the instruction decode unit 7 and the processing to be executed is notified to the instruction execution unit 9 which performs the arithmetic processing. The execution unit 9 performs a designated operation using the operand data stored in the operand buffer 8. The read / write control circuit 10 issues a strobe signal to the instruction register 6 and the operand buffer 8 based on the bus cycle information RD, WR, and CD specified from the outside, and controls the queuing of the operand buffer 8. Here, the RD signal indicates a read timing for the coprocessor 3, and the WR signal indicates a write timing. The CD signal indicates the type of the bus cycle. When CD = 0, it means the transfer of a command to the instruction register 6;
If = 1, it means transfer of operand data to the operand buffer 8. The DRQ signal indicates a data transfer request from the instruction execution unit 9 to the operand buffer 8, and the BSY signal indicates that valid operand data has not been transferred to the operand buffer 8. Next, the operation timing of the arithmetic processing of the conventional coprocessor will be described with reference to a timing chart shown in FIG. When the command is transferred to the instruction register 6 at the timing Tc, the instruction decoding unit 7 interprets the instruction, and at the timing Te, the instruction execution unit 9
Start In the instruction execution unit 9, when the processing advances to some extent and reaches the timing Tr 1, the processing requires operand data, so that a DRQ signal to the operand buffer 8 is issued. Since the BSY signal of the read / write control circuit 10 indicates that valid operand data is not stored in the operand buffer 8, the processing is suspended until timing To1. When the operand data is transferred to the operand buffer 8 at the timing To1, the BSY signal becomes inactive, and the processing suspended in the instruction execution unit 9 is continued. When the restarted processing reaches timing Tr2, the next operand data is required again,
The processing is suspended until the operand data is transferred to the operand buffer 8, that is, until the timing To2. In FIG. 7, the instruction execution unit 9
, The period during which the process is actually being performed is indicated by oblique lines, and the period during which the process is suspended is indicated by a blank. [Problems to be Solved by the Invention] However, in the conventional coprocessor, the seventh
As shown in the figure, the execution process of the instruction execution unit 9 is suspended for the time (t1 + t2) waiting for operand data to be transferred to the operand buffer 8, so that extra time is generated until an operation result is obtained. There is a problem that it is. The present invention has been made in view of such a problem, and an object of the present invention is to provide a coprocessor capable of eliminating the time during which execution processing is suspended and shortening the processing time. [Means for Solving the Problems] In the coprocessor of the present invention, a command specifying a type of operation and operand data to be operated are externally transferred by a single command in a coprocessor. At least one set of registers having a total word length necessary to store all the operand data to be transferred prior to the transfer of the command, and each register of the register group each time operand data is transferred are sequentially selected. Control means for storing the operand data, a command register for receiving an external command transfer, and an instruction execution unit for receiving the operand data transfer from the register group and processing an instruction based on the command stored in the command register. Command is externally transferred to the command register. Prior to this, all operand data are stored in the register group, and the instruction execution unit starts processing related to the instruction after the transfer of the command. [Operation] Each time operand data is transferred, the control means sequentially selects each register of the register group and stores the operand data. This register group has a total word length necessary to store all operand data to be processed by one command, and all operand data is stored by the control means. Then, when the command execution unit inputs the command,
Processing including manipulation of the operand data stored in the register group is started. As described above, when the instruction execution unit processes an instruction, all the operand data has already been stored in the register group, so that the processing is not suspended due to the non-transfer of the operand register. Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a coprocessor according to a first embodiment of the present invention. Three 32-bit operand registers that store 80-bit floating-point data
11, 12, 13 and the instruction register 6 are connected to the 32-bit shared data bus 4. The instruction register 6 temporarily holds the command transferred via the shared data bus 4 and outputs it to the instruction decoding unit 7. The instruction decode unit 7 analyzes the input command and notifies the instruction execution unit 14 of the contents of the processing. In the instruction execution unit 14, they are stored in the operand registers 11, 12, and 13.
The specified operation is processed collectively using 80-bit operand data. The operand register control circuit 15 issues a strobe signal to the instruction register 6 and the operand registers 11, 12, and 13 based on the bus cycle information RD, WR, and CD specified from the outside, and also issues a strobe signal to the operand registers 11, 12, and 13. Performs waiting control. Here, the RD signal indicates a read timing for the coprocessor 3, and the WR signal indicates a write timing. The CD signal indicates the type of the bus cycle. When CD = 0, it means the transfer of a command to the instruction register 6;
= 1 means transfer of operand data to operand registers 11, 12, and 13. The 2-bit address (A) signal is a signal for identifying each of the operand registers 11, 12, and 13, and is input in synchronization with a bus cycle for transferring operand data. When the address (A) signal is (00b), the operand data is transferred to the operand register 11, when it is (01b), it is transferred to the operand register 12, and when it is (10b), the operand data is transferred to the operand register 13. Show. Next, the operation of the coprocessor configured as described above will be described with reference to the operation timing chart of FIG. When the first 32-bit operand data whose address (A) signal is (00b) is transferred from the shared data bus 4 at the timing To1, this data is stored in the operand register 11. Next, at the timing To2, when the second 32-bit operand data whose address (A) signal is (01b) is transferred, this data is transferred to the operand register 12 and subsequently the address (A) signal is transmitted at the timing To3. When the third 32-bit operand data of (10b) is transferred, this data is stored in the operand register 13. Since the floating-point data to be processed has an 80-bit length, the upper 16 bits of the 32-bit operand data transferred in the third bus cycle are invalid data. Further, when the command is transferred to the instruction register 6 at the timing Tc, the instruction decode unit 7 interprets the command and instructs the instruction execution unit 14 to start processing at the timing Te. When the instruction execution unit 14 starts processing and, for example, requires operand data at the timing Tr1, Tr2, Tr3, since all of the 80-bit floating point data is stored in the operand registers 11, 12, and 13, The operand registers 11, 12, and 13 are capable of instructing the operand data regardless of whether the instruction execution unit 14 requests any of the 80 bits of 32-bit operand data or all of the 80 bits of data at the same time. It can be forwarded to the execution unit 14. Therefore, the suspension of the processing due to the non-transfer of the operand data does not occur, and the instruction execution unit 14 can perform the arithmetic processing continuously without interruption. In the present embodiment, the instruction execution unit 14 does not perform any processing during the period from the timing origin T0 to the timing Te at which the instruction execution unit 14 starts to be activated. Since the period can be overlapped, the non-operation time from the timing T0 to the timing Te is eliminated, and the instruction execution unit 14 can be used effectively. In the present embodiment, the transfer order of the operand data is the order corresponding to the operand registers 11, 12, and 13. However, regardless of this order, the operand data can be selected and transferred in an arbitrary order. Of course. FIG. 3 is a block diagram showing a coprocessor according to a second embodiment of the present invention. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. The strobe signal issued to the operand registers 11, 12, and 13 by the operand register control circuit 16 is input to the operand registers 11, 12, and 13 via the incrementer 17 and the decoder 18. The RD signal, the WR signal, and the CD signal are input to the operand register control circuit 16. The incrementer 17 is initialized to (00b) when the WR signal input to the operand register control circuit 16 becomes 1 and the CD signal becomes 0 (command transfer to the instruction register 6).
Then, the incrementer 17 outputs the operand registers 11, 12,
When the operand data is transferred to 13, it is detected by WR = 1 and CD = 1, and the content is updated by +1. When the operand data is transferred to the operand registers 11, 12, and 13, the decoder 18 generates a write strobe signal for each of the operand registers 11, 12, and 13 according to the contents of the incrementer 17. That is, at the time of the first operand data transfer, since the incrementer 17 is (00b), the decoder 18 generates a write strobe signal for the operand register 11. When this write strobe signal is generated, the incrementer 17 is immediately incremented by 1 to (01b). The write strobe signal for the operand register 12 is issued when the incrementer 17 is (01b), and the write strobe signal for the operand register 13 is issued when the incrementer 17 is (10b). As described above, in the second embodiment, when the transfer order of the operand data is fixed in advance, the operand register can be specified without externally designating the address information.
Operand data can be transferred to 11, 12, and 13.
Then, as in the first embodiment, in the second embodiment as well, the execution unit 14 can continuously process the instructions without interrupting the processing due to the untransferred data. FIG. 4 (a) shows a bus cycle when the CPU executes an instruction requiring a coprocessor in the first embodiment, and FIG. 4 (b) shows a bus cycle according to the second embodiment. 3 shows a bus cycle in the case. In the second embodiment, the CPU 1 does not need to indicate address information in order to select the operand registers 11, 12, and 13.
The bus cycle for transferring the operand data issued to the coprocessor from FIG. 5 can be omitted. That is, in the first embodiment, as shown in FIG. 4A, the operand data required by the coprocessor is once read into the CPU by the bus cycle Bm for reading the operand data from the memory 2. After that, the data is transferred to the coprocessor by the bus cycle Bo for operand data transfer and the bus cycle Bc for command transfer. On the other hand, in the second embodiment, as shown in FIG. 4 (b), the operand data is transferred to the coprocessor in synchronization with the bus cycle Bm, and the bus cycle Bo is not required. Thus, the use efficiency (throughput) of the instruction execution unit 14 can be further improved. [Effects of the Invention] As described above, according to the present invention, all operand data are stored in the register group by the control means.
Since all the operand data is stored in the register prior to the execution processing, the instruction execution unit can process the instruction without waiting for the transfer of the operand data, and the processing time is shortened. Efficiency is improved.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a coprocessor according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the coprocessor, and FIG. FIG. 4 is a block diagram showing a coprocessor according to a second embodiment of the present invention; FIGS. 4 (a) and 4 (b) are timing charts showing states of a data bus of an information processing apparatus to which the coprocessor is connected; FIG. 1 is a block diagram showing a configuration of an information processing apparatus having a coprocessor, FIG. 6 is a block diagram showing a conventional coprocessor, and FIG. 7 is a timing chart for explaining the operation of the conventional coprocessor. . 1; CPU, 2; memory, 3; coprocessor, 4; shared data bus, 5; bus control circuit, 6; instruction register, 7; instruction decode unit, 8; operand buffer, 9, 14; instruction execution unit, 10 ; Read / write control circuit, 11, 12, 13; operand register, 15, 16; operand register control circuit, 17;
Incrementer, 18; decoder

Claims (1)

(57) [Claims] In a coprocessor to which a command for specifying the type of operation and operand data to be operated are externally transferred, all operand data to be processed by one command are stored prior to the transfer of the command. At least one set of registers having a required total word length; control means for sequentially selecting each register of the register group and storing the operand data each time operand data is transferred; A command register that receives the operand data from the register group, and an instruction execution unit that processes an instruction based on the command stored in the command register. First, all operand data is stored in the register group. Paid to keep the coprocessor the instruction execution unit, characterized in that initiating the process relating to the command after the transfer of the command.