JP2761802B2 - Digital signal processing circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for performing ON (ON) / (OFF) control by an electronic switch. The present invention relates to a digital signal processing circuit whose off time can be set arbitrarily.

[Background Art] Conventionally, as a method of generating a pulse signal in a digital signal processing circuit, a change pattern of the pulse signal is previously written on a memory in a control circuit, and the pattern is changed by an output of a counter counted by a reference clock. A pattern specified by a predetermined address is read, and the pulse is generated by outputting the data.

[Problems to be Solved by the Invention] However, in the conventional pulse signal generation method, in order to generate a pulse signal with an arbitrary pulse width and an arbitrary frequency, the contents of all data in the memory are rewritten in advance. There are disadvantages that must be met.

The present invention has been made in view of the above-described drawbacks of the related art, and has been made in consideration of a digital signal processing that can output a desired pulse signal by merely setting a value corresponding to an arbitrary pulse width and an arbitrary frequency. It is intended to provide a circuit.

[Means for Solving the Problems] The present invention provides a reference clock generation unit for generating a reference clock, and selection of any of a monostable multivibrator circuit, an astable multivibrator circuit, and a pulse width modulation circuit from an output control unit. A selector that is switched by a command and generates an output signal in response to a trigger signal from the output control unit, a first counter that is started by the output of the selector and starts counting by the reference clock, A first register for storing and holding arbitrarily set data, and comparing the output of the first counter with the data stored and held in the first register. Delay time corresponding to the data set in the first register with respect to the trigger signal output from the section A first comparator that opens the gate only after a delay, a second register that arbitrarily presets and stores data different from the data stored and held in the first register by the output control unit, And a second counter which is started by the output of the comparator and starts counting by the reference clock, and compares the output of the second counter with the data stored and held in the second register to find that they match. A second comparator that outputs a reset signal when
Setting by the output of the first comparator;
A flip-flop that resets by the output of the second comparator, obtains a predetermined pulse signal p from the flip-flop, feeds it back to the selector, and stores and stores the signal in the first and second registers. In this configuration, the data can be repeatedly output.

Further, the output control unit according to the present invention is configured such that a pulse signal having an arbitrary frequency and a pulse width can be output by arbitrarily changing data values set in the first and second registers. is there.

Further, the output control unit according to the present invention is configured so that a pulse signal having an arbitrary frequency and an arbitrary duty ratio can be set to the data values set in the first and second registers.

Embodiment Next, an embodiment of a digital signal processing circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a Dizil signal processing circuit according to the present invention, and FIG. 2 is a diagram showing a pulse signal p and data 1 set in a D-register 3 and a D-register 6 in FIG.
FIG. 3 is a diagram showing a relationship between the pulse signals obtained in FIG. 2 and h.

In FIG. 1 to FIG.
Generates a reference clock for controlling timing in controlling the digital signal processing circuit according to the present embodiment. The output of the reference clock generator 1 is input to counters 4 and 7. The selector 2 is operated by a command from the output control unit 10 to control a monostable (monostable) multivibrator circuit, an astable (unstable)
The configuration is such that it can be switched by a selection command to select a multivibrator circuit or a pulse width modulation circuit. When the selector 2 is triggered by a trigger signal t output from the output control unit 10, the output of the selector 2 is input to the counter 4. Further, the output control unit 10
Controls the output form of the output pulse signal p by performing selection control of the above-described circuit of the selector 2 and setting of the pulse width by an external operating means or the like (not shown). The low-level data 1 shown in FIG. Is set to an OFF time, and is output to and stored in the D-register 3 as a memory holding unit.
The output of the D-register 3 is output to a comparator 5 as a comparing means. In this embodiment, the D-register 3 is constituted by a circuit of a plurality of bits.

The counter 4 stores the data 1 set in the D-register 3
The clock generated from the reference clock generator 1 is counted (counting means) for the off time (OFF), and is output to the comparator 5. And the comparator 5
Compares the set value of the D-register 3 with the count value of the counter 4, and when the values match, the counter 7 and the D-
Output to FF (D-flip-flop) 9. Since the output of the comparator 5 is also output to D-FF9 at the same time, the output signal s sets D-FF9. The set signal s causes the data h of the pulse signal p shown in FIG. 2 to rise. In this embodiment, D-FF9 is configured by a 1-bit circuit.

The output control unit 10 sets the ON time of the data h shown in FIG.
Output to the register 6 for storage. This D-register 6
Is output to a comparator 8 as comparison means. This D-register 6 is constituted by a circuit of a plurality of bits.

The counter 7 stores the data h set in the D-register 6.
The number of clocks generated from the reference clock generator 1 is counted for the ON time. And the comparator 8
Is output to the D-FF9 when the set value of the D-register 6 is compared with the count value of the counter 7 and the values match. This output signal becomes the reset signal r of D-FF9. The reset signal r causes the data h shown in FIG.
Falls. Therefore, this D-FF9 is set by the output signal s of the comparator 5, and
The desired data is output by resetting the output signal r. The output of the pulse signal p of D-FF9 is fed back so as to be input to the selector 2.

Next, the operation of the present embodiment having the above configuration will be described.

I. First, the operation of the monostable (monostable) multivibrator circuit will be described.

The output control unit 10 shown in FIG.
Is set in the D-register 3 and the on-time of the data h is set and stored in the D-register 6 in advance. Then, the selector 2 is selectively controlled so as to receive only the trigger signal t output from the output control unit 10. The counter 4 and the counter 7 are set so that the output is in a clear state.

Now, when the trigger signal t is input to the selector 2, the counter 4 starts counting by the clock generated from the reference clock generator 1. Thereafter, when the count value of the counter 4 matches the value set in the D-register 3,
The comparator 5 detects the coincidence. Since the comparator 5 outputs the data to the counter 7 and also to the D-FF9 at the same time, the counter 7 starts counting by the clock generated from the reference clock generator 1 upon being triggered, and the D-FF9 is set at the same time. Thus, the data h of the pulse signal p shown in FIG. 2 rises.

Thereafter, when the count value of the counter 7 matches the value of the data h set in the D-register 6, the comparator 8 detects the match and outputs it to the D-FF9. D-FF9
Is reset by the output signal r from the comparator 8, whereby the data h shown in FIG. 2 falls.

The ON time of the pulse signal h at this time is determined by the D-register 6
Is the time obtained by multiplying the value set in advance by the period of the reference clock 1, and the off time of the data 1 is obtained by multiplying the value set in the D-register 3 by the value of the clock generated from the reference clock generator 1. This is the time obtained by multiplying the period.

With the above operation, a series of pulse signals as shown in FIG. 2 are output once, and the operation as the monostable multivibrator is completed.

II. Next, the operation when performing an astable (unstable) multivibration circuit will be described.

First, the output control unit 10 shown in FIG. 1 designates an astable multivibrator circuit and selectively controls the selector 2. The output control unit 10 activates the first pulse output in response to the trigger signal t and causes the selector 2 to output the first pulse output.
The second and subsequent pulse outputs are selectively controlled so as to be activated by the pulse signal p fed back at the falling timing of the output p of the D-FF9.

In other words, the pulse signal p shown in FIG. 2 rises with the output of the data 1 stored in the D-register 3 and the D-FF 9 is set by the set signal s, and the data h stored in the D-register 6 As a result, the high-level data h shown in FIG. 2 is obtained by causing the D-FF 9 to fall by the reset signal r.
The selector 2 is again triggered by the pulse signal p, which is the output of the D-FF9, at the falling timing of, and the pulse signal p shown in FIG. 2 is obtained. By continuously performing this loop, the output of a pulse signal having an arbitrary frequency and pulse width as shown in FIG. 3 is continuously output as a pulse signal p by the D-FF9.

III. Next, the operation when performing the pulse width modulation circuit will be described.

The selector 2 is selectively controlled by the output control unit 10 shown in FIG. Then, the first pulse output of the selector 2 is activated by the trigger signal t, and the second and subsequent pulse outputs are selectively controlled at the falling timing of the output p of the D-FF9. When the output of the pulse signal p is performed continuously as shown in FIG. 3, the output p of the D-FF9 is fed back to the selector 2 as described above.

The D-register 3 and the D-register 6 are continuously commanded to the output control unit 10 by external operation means (not shown) every time the pulse width is modulated so as to always satisfy the following expression. Should be set to.

1 + h = constant (1) With this, a desired pulse signal p having the same frequency and a pulse width modulated at an arbitrary duty ratio is continuously converted to D-.
Obtained from FF9.

In this embodiment, the D-FF9 is a one-bit circuit. However, it is needless to say that a plurality of pits may be used, and the data of the pulse signal P may be used instead of the D-registers 3 and 6. As long as the width of h and 1 can be variably stored, it can be appropriately changed and used within the scope of the present embodiment.

[Effects of the Invention] As described above, according to the present invention, it is possible to obtain a desired pulse signal output simply by setting a pulse signal having an arbitrary pulse width and an arbitrary frequency in the memory holding means on the circuit. There is an effect that can be. Therefore, for example, on / off control of a timer and generation of a gate signal on an electronic circuit can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital signal processing circuit according to the present invention, FIG. 2 is a diagram showing a relationship between a pulse signal p and data 1 and h in FIG. 1, and FIG. , Second
It is a figure which shows the state in which the pulse signal obtained in the figure was continuously output. 1... Reference clock generator, 2... Selector, 3, 6.
D-register, 4,7 ... counter, 5,8 ... comparator, 9 ... D-FF, 10 ... output control unit.

Claims (3)

(57) [Claims] An output control section for switching between a reference clock generation section for generating a reference clock and a selection command for selecting one of a monostable multivibrator circuit, an astable multivibrator circuit, and a pulse width modulation circuit from an output control section; A selector that generates an output signal in response to a trigger signal from a unit, a first counter that is started by an output of the selector and starts counting by the reference clock, and stores and holds data arbitrarily set in advance by the output control unit. A first register to compare the output of the first counter with the data stored and held in the first register, and when the values of both match, a trigger signal output from the output control unit On the other hand, when the gate is opened with a delay of a delay time corresponding to the data set in the first register. A first comparator, a second register that arbitrarily sets and stores data different from the data stored and held in the first register in advance by the output control unit, and is activated by an output of the first comparator. A second counter that starts counting with the reference clock, and compares the output of the second counter with the data stored and held in the second register, and outputs a reset signal when they match. Setting by the output of the second comparator and the first comparator;
A flip-flop that resets by an output of the second comparator, and obtains a predetermined pulse signal p from the flip-flop and feeds it back to the selector to store and hold in the first and second registers. A digital signal processing circuit characterized in that the data can be repeatedly output. 2. An apparatus according to claim 1, wherein said output control section is capable of outputting a pulse signal having an arbitrary frequency and a pulse width by arbitrarily changing data values set in said first and second registers. The digital signal processing circuit according to claim 1, wherein: 3. The output control unit according to claim 1, wherein data values set in said first and second registers can be set to pulse signals having the same frequency and an arbitrary duty ratio. The digital signal processing circuit according to (1).